src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "util/u_slab.h"
  30 #include "r600.h"
  31 #include "r600_llvm.h"
  32 #include "r600_public.h"
  33 #include "r600_shader.h"
  34 #include "r600_resource.h"
  35 #include "evergreen_compute.h"
  36
  37 #define R600_MAX_CONST_BUFFERS 2
  38 #define R600_MAX_CONST_BUFFER_SIZE 4096
  39
  40 #ifdef PIPE_ARCH_BIG_ENDIAN
  41 #define R600_BIG_ENDIAN 1
  42 #else
  43 #define R600_BIG_ENDIAN 0
  44 #endif
  45
  46 enum r600_atom_flags {
  47         /* When set, atoms are added at the beginning of the dirty list
  48          * instead of the end. */
  49         EMIT_EARLY = (1 << 0)
  50 };
  51
  52 /* This encapsulates a state or an operation which can emitted into the GPU
  53  * command stream. It's not limited to states only, it can be used for anything
  54  * that wants to write commands into the CS (e.g. cache flushes). */
  55 struct r600_atom {
  56         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  57
  58         unsigned                num_dw;
  59         enum r600_atom_flags    flags;
  60         bool                    dirty;
  61
  62         struct list_head        head;
  63 };
  64
  65 /* This is an atom containing GPU commands that never change.
  66  * This is supposed to be copied directly into the CS. */
  67 struct r600_command_buffer {
  68         struct r600_atom atom;
  69         uint32_t *buf;
  70         unsigned max_num_dw;
  71         unsigned pkt_flags;
  72 };
  73
  74 struct r600_surface_sync_cmd {
  75         struct r600_atom atom;
  76         unsigned flush_flags; /* CP_COHER_CNTL */
  77 };
  78
  79 struct r600_db_misc_state {
  80         struct r600_atom atom;
  81         bool occlusion_query_enabled;
  82         bool flush_depthstencil_enabled;
  83 };
  84
  85 struct r600_cb_misc_state {
  86         struct r600_atom atom;
  87         unsigned cb_color_control; /* this comes from blend state */
  88         unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
  89         unsigned nr_cbufs;
  90         unsigned nr_ps_color_outputs;
  91         bool multiwrite;
  92         bool dual_src_blend;
  93 };
  94
  95 enum r600_pipe_state_id {
  96         R600_PIPE_STATE_BLEND = 0,
  97         R600_PIPE_STATE_BLEND_COLOR,
  98         R600_PIPE_STATE_CONFIG,
  99         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
 100         R600_PIPE_STATE_CLIP,
 101         R600_PIPE_STATE_SCISSOR,
 102         R600_PIPE_STATE_VIEWPORT,
 103         R600_PIPE_STATE_RASTERIZER,
 104         R600_PIPE_STATE_VGT,
 105         R600_PIPE_STATE_FRAMEBUFFER,
 106         R600_PIPE_STATE_DSA,
 107         R600_PIPE_STATE_STENCIL_REF,
 108         R600_PIPE_STATE_PS_SHADER,
 109         R600_PIPE_STATE_VS_SHADER,
 110         R600_PIPE_STATE_CONSTANT,
 111         R600_PIPE_STATE_SAMPLER,
 112         R600_PIPE_STATE_RESOURCE,
 113         R600_PIPE_STATE_POLYGON_OFFSET,
 114         R600_PIPE_STATE_FETCH_SHADER,
 115         R600_PIPE_STATE_SPI,
 116         R600_PIPE_NSTATES
 117 };
 118
 119 struct compute_memory_pool;
 120 void compute_memory_pool_delete(struct compute_memory_pool* pool);
 121 struct compute_memory_pool* compute_memory_pool_new(
 122         struct r600_screen *rscreen);
 123
 124 struct r600_pipe_fences {
 125         struct r600_resource            *bo;
 126         unsigned                        *data;
 127         unsigned                        next_index;
 128         /* linked list of preallocated blocks */
 129         struct list_head                blocks;
 130         /* linked list of freed fences */
 131         struct list_head                pool;
 132         pipe_mutex                      mutex;
 133 };
 134
 135 struct r600_screen {
 136         struct pipe_screen              screen;
 137         struct radeon_winsys            *ws;
 138         unsigned                        family;
 139         enum chip_class                 chip_class;
 140         struct radeon_info              info;
 141         bool                            has_streamout;
 142         struct r600_tiling_info         tiling_info;
 143         struct r600_pipe_fences         fences;
 144
 145         bool                            use_surface_alloc;
 146         int                             glsl_feature_level;
 147
 148         /*for compute global memory binding, we allocate stuff here, instead of
 149          * buffers.
 150          * XXX: Not sure if this is the best place for global_pool.  Also,
 151          * it's not thread safe, so it won't work with multiple contexts. */
 152         struct compute_memory_pool *global_pool;
 153 };
 154
 155 struct r600_pipe_sampler_view {
 156         struct pipe_sampler_view        base;
 157         struct r600_pipe_resource_state         state;
 158 };
 159
 160 struct r600_pipe_rasterizer {
 161         struct r600_pipe_state          rstate;
 162         boolean                         flatshade;
 163         boolean                         two_side;
 164         unsigned                        sprite_coord_enable;
 165         unsigned                        clip_plane_enable;
 166         unsigned                        pa_sc_line_stipple;
 167         unsigned                        pa_cl_clip_cntl;
 168         float                           offset_units;
 169         float                           offset_scale;
 170         bool                            scissor_enable;
 171 };
 172
 173 struct r600_pipe_blend {
 174         struct r600_pipe_state          rstate;
 175         unsigned                        cb_target_mask;
 176         unsigned                        cb_color_control;
 177         bool                            dual_src_blend;
 178 };
 179
 180 struct r600_pipe_dsa {
 181         struct r600_pipe_state          rstate;
 182         unsigned                        alpha_ref;
 183         ubyte                           valuemask[2];
 184         ubyte                           writemask[2];
 185         bool                            is_flush;
 186         unsigned                        sx_alpha_test_control;
 187 };
 188
 189 struct r600_vertex_element
 190 {
 191         unsigned                        count;
 192         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 193         struct r600_resource            *fetch_shader;
 194         unsigned                        fs_size;
 195         struct r600_pipe_state          rstate;
 196 };
 197
 198 struct r600_pipe_shader;
 199
 200 struct r600_pipe_shader_selector {
 201         struct r600_pipe_shader *current;
 202
 203         struct tgsi_token       *tokens;
 204         struct pipe_stream_output_info  so;
 205
 206         unsigned        num_shaders;
 207
 208         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 209         unsigned        type;
 210
 211         unsigned        nr_ps_max_color_exports;
 212 };
 213
 214 struct r600_pipe_shader {
 215         struct r600_pipe_shader_selector *selector;
 216         struct r600_pipe_shader *next_variant;
 217         struct r600_shader              shader;
 218         struct r600_pipe_state          rstate;
 219         struct r600_resource            *bo;
 220         struct r600_resource            *bo_fetch;
 221         struct r600_vertex_element      vertex_elements;
 222         unsigned        sprite_coord_enable;
 223         unsigned        flatshade;
 224         unsigned        pa_cl_vs_out_cntl;
 225         unsigned        nr_ps_color_outputs;
 226         unsigned        key;
 227         unsigned                db_shader_control;
 228         unsigned                ps_depth_export;
 229 };
 230
 231 struct r600_pipe_sampler_state {
 232         struct r600_pipe_state          rstate;
 233         boolean seamless_cube_map;
 234 };
 235
 236 /* needed for blitter save */
 237 #define NUM_TEX_UNITS 16
 238
 239 struct r600_textures_info {
 240         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 241         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 242         unsigned                        n_views;
 243         unsigned                        n_samplers;
 244         bool                            samplers_dirty;
 245         bool                            is_array_sampler[NUM_TEX_UNITS];
 246 };
 247
 248 struct r600_fence {
 249         struct pipe_reference           reference;
 250         unsigned                        index; /* in the shared bo */
 251         struct r600_resource            *sleep_bo;
 252         struct list_head                head;
 253 };
 254
 255 #define FENCE_BLOCK_SIZE 16
 256
 257 struct r600_fence_block {
 258         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 259         struct list_head                head;
 260 };
 261
 262 #define R600_CONSTANT_ARRAY_SIZE 256
 263 #define R600_RESOURCE_ARRAY_SIZE 160
 264
 265 struct r600_stencil_ref
 266 {
 267         ubyte ref_value[2];
 268         ubyte valuemask[2];
 269         ubyte writemask[2];
 270 };
 271
 272 struct r600_constbuf_state
 273 {
 274         struct r600_atom                atom;
 275         struct pipe_constant_buffer     cb[PIPE_MAX_CONSTANT_BUFFERS];
 276         uint32_t                        enabled_mask;
 277         uint32_t                        dirty_mask;
 278 };
 279
 280 struct r600_context {
 281         struct pipe_context             context;
 282         struct blitter_context          *blitter;
 283         enum radeon_family              family;
 284         enum chip_class                 chip_class;
 285         boolean                         has_vertex_cache;
 286         unsigned                        r6xx_num_clause_temp_gprs;
 287         void                            *custom_dsa_flush;
 288         struct r600_screen              *screen;
 289         struct radeon_winsys            *ws;
 290         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 291         struct r600_vertex_element      *vertex_elements;
 292         struct pipe_framebuffer_state   framebuffer;
 293         unsigned                        compute_cb_target_mask;
 294         unsigned                        sx_alpha_test_control;
 295         unsigned                        db_shader_control;
 296         unsigned                        pa_sc_line_stipple;
 297         unsigned                        pa_cl_clip_cntl;
 298         /* for saving when using blitter */
 299         struct pipe_stencil_ref         stencil_ref;
 300         struct pipe_viewport_state      viewport;
 301         struct pipe_clip_state          clip;
 302         struct r600_pipe_shader_selector        *ps_shader;
 303         struct r600_pipe_shader_selector        *vs_shader;
 304         struct r600_pipe_compute        *cs_shader;
 305         struct r600_pipe_rasterizer     *rasterizer;
 306         struct r600_pipe_state          vgt;
 307         struct r600_pipe_state          spi;
 308         struct pipe_query               *current_render_cond;
 309         unsigned                        current_render_cond_mode;
 310         struct pipe_query               *saved_render_cond;
 311         unsigned                        saved_render_cond_mode;
 312         /* shader information */
 313         boolean                         two_side;
 314         boolean                         spi_dirty;
 315         unsigned                        sprite_coord_enable;
 316         boolean                         flatshade;
 317         boolean                         export_16bpc;
 318         unsigned                        alpha_ref;
 319         boolean                         alpha_ref_dirty;
 320         unsigned                        nr_cbufs;
 321         struct r600_textures_info       vs_samplers;
 322         struct r600_textures_info       ps_samplers;
 323
 324         struct u_upload_mgr             *uploader;
 325         struct util_slab_mempool        pool_transfers;
 326         boolean                         have_depth_texture, have_depth_fb;
 327
 328         unsigned default_ps_gprs, default_vs_gprs;
 329
 330         /* States based on r600_atom. */
 331         struct list_head                dirty_states;
 332         struct r600_command_buffer      start_cs_cmd; /* invariant state mostly */
 333         /** Compute specific registers initializations.  The start_cs_cmd atom
 334          *  must be emitted before start_compute_cs_cmd. */
 335         struct r600_command_buffer      start_compute_cs_cmd;
 336         struct r600_surface_sync_cmd    surface_sync_cmd;
 337         struct r600_atom                r6xx_flush_and_inv_cmd;
 338         struct r600_cb_misc_state       cb_misc_state;
 339         struct r600_db_misc_state       db_misc_state;
 340         struct r600_atom                vertex_buffer_state;
 341         struct r600_constbuf_state      vs_constbuf_state;
 342         struct r600_constbuf_state      ps_constbuf_state;
 343
 344         struct radeon_winsys_cs *cs;
 345
 346         struct r600_range       *range;
 347         unsigned                nblocks;
 348         struct r600_block       **blocks;
 349         struct list_head        dirty;
 350         struct list_head        resource_dirty;
 351         struct list_head        enable_list;
 352         unsigned                pm4_dirty_cdwords;
 353         unsigned                ctx_pm4_ndwords;
 354
 355         /* The list of active queries. Only one query of each type can be active. */
 356         int                     num_occlusion_queries;
 357
 358         /* Manage queries in two separate groups:
 359          * The timer ones and the others (streamout, occlusion).
 360          *
 361          * We do this because we should only suspend non-timer queries for u_blitter,
 362          * and later if the non-timer queries are suspended, the context flush should
 363          * only suspend and resume the timer queries. */
 364         struct list_head        active_timer_queries;
 365         unsigned                num_cs_dw_timer_queries_suspend;
 366         struct list_head        active_nontimer_queries;
 367         unsigned                num_cs_dw_nontimer_queries_suspend;
 368
 369         unsigned                num_cs_dw_streamout_end;
 370
 371         unsigned                backend_mask;
 372         unsigned                max_db; /* for OQ */
 373         unsigned                flags;
 374         boolean                 predicate_drawing;
 375         struct r600_range       ps_resources;
 376         struct r600_range       vs_resources;
 377         int                     num_ps_resources, num_vs_resources;
 378
 379         unsigned                num_so_targets;
 380         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 381         boolean                 streamout_start;
 382         unsigned                streamout_append_bitmask;
 383
 384         /* There is no scissor enable bit on r6xx, so we must use a workaround.
 385          * These track the current scissor state. */
 386         bool                    scissor_enable;
 387         struct pipe_scissor_state scissor_state;
 388
 389         /* With rasterizer discard, there doesn't have to be a pixel shader.
 390          * In that case, we bind this one: */
 391         void                    *dummy_pixel_shader;
 392
 393         boolean                 dual_src_blend;
 394
 395         /* Vertex and index buffers. */
 396         bool                    vertex_buffers_dirty;
 397         struct pipe_index_buffer index_buffer;
 398         struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 399         unsigned                nr_vertex_buffers;
 400 };
 401
 402 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 403 {
 404         atom->emit(rctx, atom);
 405         atom->dirty = false;
 406         if (atom->head.next && atom->head.prev)
 407                 LIST_DELINIT(&atom->head);
 408 }
 409
 410 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 411 {
 412         if (!state->dirty) {
 413                 if (state->flags & EMIT_EARLY) {
 414                         LIST_ADD(&state->head, &rctx->dirty_states);
 415                 } else {
 416                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 417                 }
 418                 state->dirty = true;
 419         }
 420 }
 421
 422 /* evergreen_state.c */
 423 void evergreen_init_state_functions(struct r600_context *rctx);
 424 void evergreen_init_atom_start_cs(struct r600_context *rctx);
 425 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 426 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 427 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 428 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 429 void evergreen_polygon_offset_update(struct r600_context *rctx);
 430 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 431                                       enum pipe_format format,
 432                                       enum pipe_texture_target target,
 433                                       unsigned sample_count,
 434                                       unsigned usage);
 435 void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
 436                          const struct pipe_framebuffer_state *state, int cb);
 437
 438
 439 void evergreen_update_dual_export_state(struct r600_context * rctx);
 440
 441 /* r600_blit.c */
 442 void r600_init_blit_functions(struct r600_context *rctx);
 443 void r600_blit_uncompress_depth(struct pipe_context *ctx,
 444                 struct r600_resource_texture *texture,
 445                 struct r600_resource_texture *staging);
 446 void r600_flush_depth_textures(struct r600_context *rctx);
 447
 448 /* r600_buffer.c */
 449 bool r600_init_resource(struct r600_screen *rscreen,
 450                         struct r600_resource *res,
 451                         unsigned size, unsigned alignment,
 452                         unsigned bind, unsigned usage);
 453 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 454                                          const struct pipe_resource *templ);
 455
 456 /* r600_pipe.c */
 457 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 458                 unsigned flags);
 459
 460 /* r600_query.c */
 461 void r600_init_query_functions(struct r600_context *rctx);
 462 void r600_suspend_nontimer_queries(struct r600_context *ctx);
 463 void r600_resume_nontimer_queries(struct r600_context *ctx);
 464 void r600_suspend_timer_queries(struct r600_context *ctx);
 465 void r600_resume_timer_queries(struct r600_context *ctx);
 466
 467 /* r600_resource.c */
 468 void r600_init_context_resource_functions(struct r600_context *r600);
 469
 470 /* r600_shader.c */
 471 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 472 #ifdef HAVE_OPENCL
 473 int r600_compute_shader_create(struct pipe_context * ctx,
 474         LLVMModuleRef mod,  struct r600_bytecode * bytecode);
 475 #endif
 476 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 477
 478 /* r600_state.c */
 479 void r600_set_scissor_state(struct r600_context *rctx,
 480                             const struct pipe_scissor_state *state);
 481 void r600_update_sampler_states(struct r600_context *rctx);
 482 void r600_init_state_functions(struct r600_context *rctx);
 483 void r600_init_atom_start_cs(struct r600_context *rctx);
 484 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 485 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 486 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 487 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 488 void r600_polygon_offset_update(struct r600_context *rctx);
 489 void r600_adjust_gprs(struct r600_context *rctx);
 490 boolean r600_is_format_supported(struct pipe_screen *screen,
 491                                  enum pipe_format format,
 492                                  enum pipe_texture_target target,
 493                                  unsigned sample_count,
 494                                  unsigned usage);
 495 void r600_update_dual_export_state(struct r600_context * rctx);
 496
 497 /* r600_texture.c */
 498 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 499 void r600_init_surface_functions(struct r600_context *r600);
 500 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 501                                   const unsigned char *swizzle_view,
 502                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 503 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 504                                         unsigned level, unsigned layer);
 505
 506 /* r600_translate.c */
 507 void r600_translate_index_buffer(struct r600_context *r600,
 508                                  struct pipe_index_buffer *ib,
 509                                  unsigned count);
 510
 511 /* r600_state_common.c */
 512 void r600_init_atom(struct r600_atom *atom,
 513                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
 514                     unsigned num_dw, enum r600_atom_flags flags);
 515 void r600_init_common_atoms(struct r600_context *rctx);
 516 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 517 void r600_texture_barrier(struct pipe_context *ctx);
 518 void r600_set_index_buffer(struct pipe_context *ctx,
 519                            const struct pipe_index_buffer *ib);
 520 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 521                              const struct pipe_vertex_buffer *buffers);
 522 void *r600_create_vertex_elements(struct pipe_context *ctx,
 523                                   unsigned count,
 524                                   const struct pipe_vertex_element *elements);
 525 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 526 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 527 void r600_set_blend_color(struct pipe_context *ctx,
 528                           const struct pipe_blend_color *state);
 529 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 530 void r600_set_max_scissor(struct r600_context *rctx);
 531 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 532 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 533 void r600_sampler_view_destroy(struct pipe_context *ctx,
 534                                struct pipe_sampler_view *state);
 535 void r600_delete_state(struct pipe_context *ctx, void *state);
 536 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 537 void *r600_create_shader_state_ps(struct pipe_context *ctx,
 538                    const struct pipe_shader_state *state);
 539 void *r600_create_shader_state_vs(struct pipe_context *ctx,
 540                    const struct pipe_shader_state *state);
 541 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 542 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 543 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 544 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 545 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
 546 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 547                               struct pipe_constant_buffer *cb);
 548 struct pipe_stream_output_target *
 549 r600_create_so_target(struct pipe_context *ctx,
 550                       struct pipe_resource *buffer,
 551                       unsigned buffer_offset,
 552                       unsigned buffer_size);
 553 void r600_so_target_destroy(struct pipe_context *ctx,
 554                             struct pipe_stream_output_target *target);
 555 void r600_set_so_targets(struct pipe_context *ctx,
 556                          unsigned num_targets,
 557                          struct pipe_stream_output_target **targets,
 558                          unsigned append_bitmask);
 559 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 560                                const struct pipe_stencil_ref *state);
 561 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 562 uint32_t r600_translate_stencil_op(int s_op);
 563 uint32_t r600_translate_fill(uint32_t func);
 564 unsigned r600_tex_wrap(unsigned wrap);
 565 unsigned r600_tex_filter(unsigned filter);
 566 unsigned r600_tex_mipfilter(unsigned filter);
 567 unsigned r600_tex_compare(unsigned compare);
 568
 569 /*
 570  * Helpers for building command buffers
 571  */
 572
 573 #define PKT3_SET_CONFIG_REG     0x68
 574 #define PKT3_SET_CONTEXT_REG    0x69
 575 #define PKT3_SET_CTL_CONST      0x6F
 576 #define PKT3_SET_LOOP_CONST                    0x6C
 577
 578 #define R600_CONFIG_REG_OFFSET  0x08000
 579 #define R600_CONTEXT_REG_OFFSET 0x28000
 580 #define R600_CTL_CONST_OFFSET   0x3CFF0
 581 #define R600_LOOP_CONST_OFFSET                 0X0003E200
 582 #define EG_LOOP_CONST_OFFSET               0x0003A200
 583
 584 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 585 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 586 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
 587 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 588 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 589
 590 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
 591 {
 592         cb->buf[cb->atom.num_dw++] = value;
 593 }
 594
 595 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 596 {
 597         assert(reg < R600_CONTEXT_REG_OFFSET);
 598         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 599         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 600         cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 601 }
 602
 603 /**
 604  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 605  * shaders.
 606  */
 607 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 608 {
 609         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 610         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 611         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
 612         cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 613 }
 614
 615 /**
 616  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 617  * shaders.
 618  */
 619 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 620 {
 621         assert(reg >= R600_CTL_CONST_OFFSET);
 622         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 623         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
 624         cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 625 }
 626
 627 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 628 {
 629         assert(reg >= R600_LOOP_CONST_OFFSET);
 630         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 631         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 632         cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
 633 }
 634
 635 /**
 636  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 637  * shaders.
 638  */
 639 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 640 {
 641         assert(reg >= EG_LOOP_CONST_OFFSET);
 642         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 643         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
 644         cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
 645 }
 646
 647 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 648 {
 649         r600_store_config_reg_seq(cb, reg, 1);
 650         r600_store_value(cb, value);
 651 }
 652
 653 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 654 {
 655         r600_store_context_reg_seq(cb, reg, 1);
 656         r600_store_value(cb, value);
 657 }
 658
 659 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 660 {
 661         r600_store_ctl_const_seq(cb, reg, 1);
 662         r600_store_value(cb, value);
 663 }
 664
 665 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 666 {
 667         r600_store_loop_const_seq(cb, reg, 1);
 668         r600_store_value(cb, value);
 669 }
 670
 671 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 672 {
 673         eg_store_loop_const_seq(cb, reg, 1);
 674         r600_store_value(cb, value);
 675 }
 676
 677 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
 678 void r600_release_command_buffer(struct r600_command_buffer *cb);
 679
 680 /*
 681  * Helpers for emitting state into a command stream directly.
 682  */
 683
 684 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
 685                                              enum radeon_bo_usage usage)
 686 {
 687         assert(usage);
 688         return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
 689 }
 690
 691 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
 692 {
 693         cs->buf[cs->cdw++] = value;
 694 }
 695
 696 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 697 {
 698         assert(reg < R600_CONTEXT_REG_OFFSET);
 699         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 700         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 701         cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 702 }
 703
 704 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 705 {
 706         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 707         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 708         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 709         cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 710 }
 711
 712 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 713 {
 714         assert(reg >= R600_CTL_CONST_OFFSET);
 715         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 716         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 717         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 718 }
 719
 720 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 721 {
 722         r600_write_config_reg_seq(cs, reg, 1);
 723         r600_write_value(cs, value);
 724 }
 725
 726 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 727 {
 728         r600_write_context_reg_seq(cs, reg, 1);
 729         r600_write_value(cs, value);
 730 }
 731
 732 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 733 {
 734         r600_write_ctl_const_seq(cs, reg, 1);
 735         r600_write_value(cs, value);
 736 }
 737
 738 /*
 739  * common helpers
 740  */
 741 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 742 {
 743         return value * (1 << frac_bits);
 744 }
 745 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 746
 747 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 748 {
 749         if (filter <= 1)   return 0;
 750         if (filter <= 2)   return 1;
 751         if (filter <= 4)   return 2;
 752         if (filter <= 8)   return 3;
 753          /* else */        return 4;
 754 }
 755
 756 /* 12.4 fixed-point */
 757 static INLINE unsigned r600_pack_float_12p4(float x)
 758 {
 759         return x <= 0    ? 0 :
 760                x >= 4096 ? 0xffff : x * 16;
 761 }
 762
 763 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 764 {
 765         struct r600_screen *rscreen = (struct r600_screen*)screen;
 766         struct r600_resource *rresource = (struct r600_resource*)resource;
 767
 768         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 769 }
 770
 771 #endif