2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_slab.h"
31 #include "r600_llvm.h"
32 #include "r600_public.h"
33 #include "r600_shader.h"
34 #include "r600_resource.h"
35 #include "evergreen_compute.h"
37 #define R600_MAX_CONST_BUFFERS 2
38 #define R600_MAX_CONST_BUFFER_SIZE 4096
40 #ifdef PIPE_ARCH_BIG_ENDIAN
41 #define R600_BIG_ENDIAN 1
43 #define R600_BIG_ENDIAN 0
46 enum r600_atom_flags {
47 /* When set, atoms are added at the beginning of the dirty list
48 * instead of the end. */
52 /* This encapsulates a state or an operation which can emitted into the GPU
53 * command stream. It's not limited to states only, it can be used for anything
54 * that wants to write commands into the CS (e.g. cache flushes). */
56 void (*emit)(struct r600_context *ctx, struct r600_atom *state);
59 enum r600_atom_flags flags;
62 struct list_head head;
65 /* This is an atom containing GPU commands that never change.
66 * This is supposed to be copied directly into the CS. */
67 struct r600_command_buffer {
68 struct r600_atom atom;
74 struct r600_surface_sync_cmd {
75 struct r600_atom atom;
76 unsigned flush_flags; /* CP_COHER_CNTL */
79 struct r600_db_misc_state {
80 struct r600_atom atom;
81 bool occlusion_query_enabled;
82 bool flush_depthstencil_through_cb;
83 bool copy_depth, copy_stencil;
87 struct r600_cb_misc_state {
88 struct r600_atom atom;
89 unsigned cb_color_control; /* this comes from blend state */
90 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
92 unsigned nr_ps_color_outputs;
97 struct r600_alphatest_state {
98 struct r600_atom atom;
99 unsigned sx_alpha_test_control; /* this comes from dsa state */
100 unsigned sx_alpha_ref; /* this comes from dsa state */
102 bool cb0_export_16bpc; /* from set_framebuffer_state */
105 struct r600_cs_shader_state {
106 struct r600_atom atom;
107 struct r600_pipe_compute *shader;
110 struct r600_sample_mask {
111 struct r600_atom atom;
112 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
115 enum r600_pipe_state_id {
116 R600_PIPE_STATE_BLEND = 0,
117 R600_PIPE_STATE_BLEND_COLOR,
118 R600_PIPE_STATE_CONFIG,
119 R600_PIPE_STATE_SEAMLESS_CUBEMAP,
120 R600_PIPE_STATE_CLIP,
121 R600_PIPE_STATE_SCISSOR,
122 R600_PIPE_STATE_VIEWPORT,
123 R600_PIPE_STATE_RASTERIZER,
125 R600_PIPE_STATE_FRAMEBUFFER,
127 R600_PIPE_STATE_STENCIL_REF,
128 R600_PIPE_STATE_PS_SHADER,
129 R600_PIPE_STATE_VS_SHADER,
130 R600_PIPE_STATE_CONSTANT,
131 R600_PIPE_STATE_SAMPLER,
132 R600_PIPE_STATE_RESOURCE,
133 R600_PIPE_STATE_POLYGON_OFFSET,
134 R600_PIPE_STATE_FETCH_SHADER,
139 struct compute_memory_pool;
140 void compute_memory_pool_delete(struct compute_memory_pool* pool);
141 struct compute_memory_pool* compute_memory_pool_new(
142 struct r600_screen *rscreen);
144 struct r600_pipe_fences {
145 struct r600_resource *bo;
148 /* linked list of preallocated blocks */
149 struct list_head blocks;
150 /* linked list of freed fences */
151 struct list_head pool;
156 struct pipe_screen screen;
157 struct radeon_winsys *ws;
159 enum chip_class chip_class;
160 struct radeon_info info;
162 struct r600_tiling_info tiling_info;
163 struct r600_pipe_fences fences;
165 /*for compute global memory binding, we allocate stuff here, instead of
167 * XXX: Not sure if this is the best place for global_pool. Also,
168 * it's not thread safe, so it won't work with multiple contexts. */
169 struct compute_memory_pool *global_pool;
172 struct r600_pipe_sampler_view {
173 struct pipe_sampler_view base;
174 struct r600_resource *tex_resource;
175 uint32_t tex_resource_words[8];
178 struct r600_pipe_rasterizer {
179 struct r600_pipe_state rstate;
182 unsigned sprite_coord_enable;
183 unsigned clip_plane_enable;
184 unsigned pa_sc_line_stipple;
185 unsigned pa_cl_clip_cntl;
189 bool multisample_enable;
192 struct r600_pipe_blend {
193 struct r600_pipe_state rstate;
194 unsigned cb_target_mask;
195 unsigned cb_color_control;
200 struct r600_pipe_dsa {
201 struct r600_pipe_state rstate;
205 unsigned sx_alpha_test_control;
208 struct r600_vertex_element
211 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
212 struct r600_resource *fetch_shader;
214 struct r600_pipe_state rstate;
217 struct r600_pipe_shader;
219 struct r600_pipe_shader_selector {
220 struct r600_pipe_shader *current;
222 struct tgsi_token *tokens;
223 struct pipe_stream_output_info so;
225 unsigned num_shaders;
227 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
230 unsigned nr_ps_max_color_exports;
233 struct r600_pipe_shader {
234 struct r600_pipe_shader_selector *selector;
235 struct r600_pipe_shader *next_variant;
236 struct r600_shader shader;
237 struct r600_pipe_state rstate;
238 struct r600_resource *bo;
239 struct r600_resource *bo_fetch;
240 struct r600_vertex_element vertex_elements;
241 unsigned sprite_coord_enable;
243 unsigned pa_cl_vs_out_cntl;
244 unsigned nr_ps_color_outputs;
246 unsigned db_shader_control;
247 unsigned ps_depth_export;
250 struct r600_pipe_sampler_state {
251 uint32_t tex_sampler_words[3];
252 uint32_t border_color[4];
253 bool border_color_use;
254 bool seamless_cube_map;
257 /* needed for blitter save */
258 #define NUM_TEX_UNITS 16
260 struct r600_seamless_cube_map {
261 struct r600_atom atom;
265 struct r600_samplerview_state {
266 struct r600_atom atom;
267 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
268 uint32_t enabled_mask;
270 uint32_t compressed_depthtex_mask; /* which textures are depth */
273 struct r600_textures_info {
274 struct r600_samplerview_state views;
275 struct r600_atom atom_sampler;
276 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS];
278 bool is_array_sampler[NUM_TEX_UNITS];
282 struct pipe_reference reference;
283 unsigned index; /* in the shared bo */
284 struct r600_resource *sleep_bo;
285 struct list_head head;
288 #define FENCE_BLOCK_SIZE 16
290 struct r600_fence_block {
291 struct r600_fence fences[FENCE_BLOCK_SIZE];
292 struct list_head head;
295 #define R600_CONSTANT_ARRAY_SIZE 256
296 #define R600_RESOURCE_ARRAY_SIZE 160
298 struct r600_stencil_ref
305 struct r600_constbuf_state
307 struct r600_atom atom;
308 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
309 uint32_t enabled_mask;
313 struct r600_vertexbuf_state
315 struct r600_atom atom;
316 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
317 uint32_t enabled_mask; /* non-NULL buffers */
321 struct r600_context {
322 struct pipe_context context;
323 struct blitter_context *blitter;
324 enum radeon_family family;
325 enum chip_class chip_class;
326 boolean has_vertex_cache;
327 unsigned r6xx_num_clause_temp_gprs;
328 void *custom_dsa_flush;
329 void *custom_blend_resolve;
331 struct r600_screen *screen;
332 struct radeon_winsys *ws;
333 struct r600_pipe_state *states[R600_PIPE_NSTATES];
334 struct r600_vertex_element *vertex_elements;
335 struct pipe_framebuffer_state framebuffer;
336 unsigned compute_cb_target_mask;
337 unsigned db_shader_control;
338 unsigned pa_sc_line_stipple;
339 unsigned pa_cl_clip_cntl;
340 /* for saving when using blitter */
341 struct pipe_stencil_ref stencil_ref;
342 struct pipe_viewport_state viewport;
343 struct pipe_clip_state clip;
344 struct r600_pipe_shader_selector *ps_shader;
345 struct r600_pipe_shader_selector *vs_shader;
346 struct r600_pipe_rasterizer *rasterizer;
347 struct r600_pipe_state vgt;
348 struct r600_pipe_state spi;
349 struct pipe_query *current_render_cond;
350 unsigned current_render_cond_mode;
351 struct pipe_query *saved_render_cond;
352 unsigned saved_render_cond_mode;
353 /* shader information */
356 unsigned sprite_coord_enable;
358 boolean export_16bpc;
361 bool multisample_enable;
364 struct u_upload_mgr *uploader;
365 struct util_slab_mempool pool_transfers;
367 unsigned default_ps_gprs, default_vs_gprs;
369 /* States based on r600_atom. */
370 struct list_head dirty_states;
371 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
372 /** Compute specific registers initializations. The start_cs_cmd atom
373 * must be emitted before start_compute_cs_cmd. */
374 struct r600_command_buffer start_compute_cs_cmd;
375 struct r600_surface_sync_cmd surface_sync_cmd;
376 struct r600_atom r6xx_flush_and_inv_cmd;
377 struct r600_alphatest_state alphatest_state;
378 struct r600_cb_misc_state cb_misc_state;
379 struct r600_db_misc_state db_misc_state;
380 /** Vertex buffers for fetch shaders */
381 struct r600_vertexbuf_state vertex_buffer_state;
382 /** Vertex buffers for compute shaders */
383 struct r600_vertexbuf_state cs_vertex_buffer_state;
384 struct r600_constbuf_state vs_constbuf_state;
385 struct r600_constbuf_state ps_constbuf_state;
386 struct r600_textures_info vs_samplers;
387 struct r600_textures_info ps_samplers;
388 struct r600_seamless_cube_map seamless_cube_map;
389 struct r600_cs_shader_state cs_shader_state;
390 struct r600_sample_mask sample_mask;
392 /* current external blend state (from state tracker) */
393 struct r600_pipe_blend *blend;
394 /* state with disabled blending - used internally with blend_override */
395 struct r600_pipe_blend *no_blend;
397 /* 1 - override current blend state with no_blend, 0 - use external state */
398 unsigned blend_override;
400 struct radeon_winsys_cs *cs;
402 struct r600_range *range;
404 struct r600_block **blocks;
405 struct list_head dirty;
406 struct list_head enable_list;
407 unsigned pm4_dirty_cdwords;
408 unsigned ctx_pm4_ndwords;
410 /* The list of active queries. Only one query of each type can be active. */
411 int num_occlusion_queries;
413 /* Manage queries in two separate groups:
414 * The timer ones and the others (streamout, occlusion).
416 * We do this because we should only suspend non-timer queries for u_blitter,
417 * and later if the non-timer queries are suspended, the context flush should
418 * only suspend and resume the timer queries. */
419 struct list_head active_timer_queries;
420 unsigned num_cs_dw_timer_queries_suspend;
421 struct list_head active_nontimer_queries;
422 unsigned num_cs_dw_nontimer_queries_suspend;
424 unsigned num_cs_dw_streamout_end;
426 unsigned backend_mask;
427 unsigned max_db; /* for OQ */
429 boolean predicate_drawing;
431 unsigned num_so_targets;
432 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
433 boolean streamout_start;
434 unsigned streamout_append_bitmask;
436 /* There is no scissor enable bit on r6xx, so we must use a workaround.
437 * These track the current scissor state. */
439 struct pipe_scissor_state scissor_state;
441 /* With rasterizer discard, there doesn't have to be a pixel shader.
442 * In that case, we bind this one: */
443 void *dummy_pixel_shader;
445 boolean dual_src_blend;
448 struct pipe_index_buffer index_buffer;
451 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
453 atom->emit(rctx, atom);
455 if (atom->head.next && atom->head.prev)
456 LIST_DELINIT(&atom->head);
459 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
462 if (state->flags & EMIT_EARLY) {
463 LIST_ADD(&state->head, &rctx->dirty_states);
465 LIST_ADDTAIL(&state->head, &rctx->dirty_states);
471 /* evergreen_state.c */
472 void evergreen_init_common_regs(struct r600_command_buffer *cb,
473 enum chip_class ctx_chip_class,
474 enum radeon_family ctx_family,
477 void evergreen_init_state_functions(struct r600_context *rctx);
478 void evergreen_init_atom_start_cs(struct r600_context *rctx);
479 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
480 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
481 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
482 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
483 void *evergreen_create_resolve_blend(struct r600_context *rctx);
484 void evergreen_polygon_offset_update(struct r600_context *rctx);
485 boolean evergreen_is_format_supported(struct pipe_screen *screen,
486 enum pipe_format format,
487 enum pipe_texture_target target,
488 unsigned sample_count,
490 void evergreen_init_color_surface(struct r600_context *rctx,
491 struct r600_surface *surf);
492 void evergreen_update_dual_export_state(struct r600_context * rctx);
495 void r600_copy_buffer(struct pipe_context *ctx, struct
496 pipe_resource *dst, unsigned dstx,
497 struct pipe_resource *src, const struct pipe_box *src_box);
498 void r600_init_blit_functions(struct r600_context *rctx);
499 void r600_blit_decompress_depth(struct pipe_context *ctx,
500 struct r600_texture *texture,
501 struct r600_texture *staging,
502 unsigned first_level, unsigned last_level,
503 unsigned first_layer, unsigned last_layer,
504 unsigned first_sample, unsigned last_sample);
505 void r600_decompress_depth_textures(struct r600_context *rctx,
506 struct r600_samplerview_state *textures);
509 bool r600_init_resource(struct r600_screen *rscreen,
510 struct r600_resource *res,
511 unsigned size, unsigned alignment,
512 unsigned bind, unsigned usage);
513 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
514 const struct pipe_resource *templ);
517 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
521 void r600_init_query_functions(struct r600_context *rctx);
522 void r600_suspend_nontimer_queries(struct r600_context *ctx);
523 void r600_resume_nontimer_queries(struct r600_context *ctx);
524 void r600_suspend_timer_queries(struct r600_context *ctx);
525 void r600_resume_timer_queries(struct r600_context *ctx);
527 /* r600_resource.c */
528 void r600_init_context_resource_functions(struct r600_context *r600);
531 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
533 int r600_compute_shader_create(struct pipe_context * ctx,
534 LLVMModuleRef mod, struct r600_bytecode * bytecode);
536 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
539 void r600_set_scissor_state(struct r600_context *rctx,
540 const struct pipe_scissor_state *state);
541 void r600_init_state_functions(struct r600_context *rctx);
542 void r600_init_atom_start_cs(struct r600_context *rctx);
543 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
544 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
545 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
546 void *r600_create_db_flush_dsa(struct r600_context *rctx);
547 void r600_polygon_offset_update(struct r600_context *rctx);
548 void r600_adjust_gprs(struct r600_context *rctx);
549 boolean r600_is_format_supported(struct pipe_screen *screen,
550 enum pipe_format format,
551 enum pipe_texture_target target,
552 unsigned sample_count,
554 void r600_update_dual_export_state(struct r600_context * rctx);
557 void r600_init_screen_texture_functions(struct pipe_screen *screen);
558 void r600_init_surface_functions(struct r600_context *r600);
559 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
560 const unsigned char *swizzle_view,
561 uint32_t *word4_p, uint32_t *yuv_format_p);
562 unsigned r600_texture_get_offset(struct r600_texture *rtex,
563 unsigned level, unsigned layer);
565 /* r600_translate.c */
566 void r600_translate_index_buffer(struct r600_context *r600,
567 struct pipe_index_buffer *ib,
570 /* r600_state_common.c */
571 void r600_init_atom(struct r600_atom *atom,
572 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
573 unsigned num_dw, enum r600_atom_flags flags);
574 void r600_init_common_atoms(struct r600_context *rctx);
575 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
576 void r600_texture_barrier(struct pipe_context *ctx);
577 void r600_set_index_buffer(struct pipe_context *ctx,
578 const struct pipe_index_buffer *ib);
579 void r600_vertex_buffers_dirty(struct r600_context *rctx);
580 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
581 const struct pipe_vertex_buffer *input);
582 void r600_sampler_views_dirty(struct r600_context *rctx,
583 struct r600_samplerview_state *state);
584 void r600_set_sampler_views(struct pipe_context *pipe,
588 struct pipe_sampler_view **views);
589 void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states);
590 void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states);
591 void *r600_create_vertex_elements(struct pipe_context *ctx,
593 const struct pipe_vertex_element *elements);
594 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
595 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
596 void r600_set_blend_color(struct pipe_context *ctx,
597 const struct pipe_blend_color *state);
598 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
599 void r600_set_max_scissor(struct r600_context *rctx);
600 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
601 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
602 void r600_sampler_view_destroy(struct pipe_context *ctx,
603 struct pipe_sampler_view *state);
604 void r600_delete_sampler(struct pipe_context *ctx, void *state);
605 void r600_delete_state(struct pipe_context *ctx, void *state);
606 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
607 void *r600_create_shader_state_ps(struct pipe_context *ctx,
608 const struct pipe_shader_state *state);
609 void *r600_create_shader_state_vs(struct pipe_context *ctx,
610 const struct pipe_shader_state *state);
611 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
612 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
613 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
614 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
615 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
616 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
617 struct pipe_constant_buffer *cb);
618 struct pipe_stream_output_target *
619 r600_create_so_target(struct pipe_context *ctx,
620 struct pipe_resource *buffer,
621 unsigned buffer_offset,
622 unsigned buffer_size);
623 void r600_so_target_destroy(struct pipe_context *ctx,
624 struct pipe_stream_output_target *target);
625 void r600_set_so_targets(struct pipe_context *ctx,
626 unsigned num_targets,
627 struct pipe_stream_output_target **targets,
628 unsigned append_bitmask);
629 void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask);
630 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
631 const struct pipe_stencil_ref *state);
632 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
633 uint32_t r600_translate_stencil_op(int s_op);
634 uint32_t r600_translate_fill(uint32_t func);
635 unsigned r600_tex_wrap(unsigned wrap);
636 unsigned r600_tex_filter(unsigned filter);
637 unsigned r600_tex_mipfilter(unsigned filter);
638 unsigned r600_tex_compare(unsigned compare);
641 * Helpers for building command buffers
644 #define PKT3_SET_CONFIG_REG 0x68
645 #define PKT3_SET_CONTEXT_REG 0x69
646 #define PKT3_SET_CTL_CONST 0x6F
647 #define PKT3_SET_LOOP_CONST 0x6C
649 #define R600_CONFIG_REG_OFFSET 0x08000
650 #define R600_CONTEXT_REG_OFFSET 0x28000
651 #define R600_CTL_CONST_OFFSET 0x3CFF0
652 #define R600_LOOP_CONST_OFFSET 0X0003E200
653 #define EG_LOOP_CONST_OFFSET 0x0003A200
655 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
656 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
657 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
658 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
659 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
661 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
663 /*Evergreen Compute packet3*/
664 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
666 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
668 cb->buf[cb->atom.num_dw++] = value;
671 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
673 assert(reg < R600_CONTEXT_REG_OFFSET);
674 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
675 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
676 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
680 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
683 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
685 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
686 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
687 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
688 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
692 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
695 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
697 assert(reg >= R600_CTL_CONST_OFFSET);
698 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
699 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
700 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
703 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
705 assert(reg >= R600_LOOP_CONST_OFFSET);
706 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
707 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
708 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
712 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
715 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
717 assert(reg >= EG_LOOP_CONST_OFFSET);
718 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
719 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
720 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
723 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
725 r600_store_config_reg_seq(cb, reg, 1);
726 r600_store_value(cb, value);
729 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
731 r600_store_context_reg_seq(cb, reg, 1);
732 r600_store_value(cb, value);
735 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
737 r600_store_ctl_const_seq(cb, reg, 1);
738 r600_store_value(cb, value);
741 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
743 r600_store_loop_const_seq(cb, reg, 1);
744 r600_store_value(cb, value);
747 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
749 eg_store_loop_const_seq(cb, reg, 1);
750 r600_store_value(cb, value);
753 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
754 void r600_release_command_buffer(struct r600_command_buffer *cb);
757 * Helpers for emitting state into a command stream directly.
760 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
761 enum radeon_bo_usage usage)
764 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
767 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
769 cs->buf[cs->cdw++] = value;
772 static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
774 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
775 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
779 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
781 assert(reg < R600_CONTEXT_REG_OFFSET);
782 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
783 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
784 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
787 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
789 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
790 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
791 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
792 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
795 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
797 r600_write_context_reg_seq(cs, reg, num);
798 /* Set the compute bit on the packet header */
799 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
802 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
804 assert(reg >= R600_CTL_CONST_OFFSET);
805 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
806 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
807 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
810 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
812 r600_write_config_reg_seq(cs, reg, 1);
813 r600_write_value(cs, value);
816 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
818 r600_write_context_reg_seq(cs, reg, 1);
819 r600_write_value(cs, value);
822 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
824 r600_write_compute_context_reg_seq(cs, reg, 1);
825 r600_write_value(cs, value);
828 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
830 r600_write_ctl_const_seq(cs, reg, 1);
831 r600_write_value(cs, value);
837 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
839 return value * (1 << frac_bits);
841 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
843 static inline unsigned r600_tex_aniso_filter(unsigned filter)
845 if (filter <= 1) return 0;
846 if (filter <= 2) return 1;
847 if (filter <= 4) return 2;
848 if (filter <= 8) return 3;
852 /* 12.4 fixed-point */
853 static INLINE unsigned r600_pack_float_12p4(float x)
856 x >= 4096 ? 0xffff : x * 16;
859 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
861 struct r600_screen *rscreen = (struct r600_screen*)screen;
862 struct r600_resource *rresource = (struct r600_resource*)resource;
864 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);