src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "util/u_slab.h"
  30 #include "r600.h"
  31 #include "r600_llvm.h"
  32 #include "r600_public.h"
  33 #include "r600_shader.h"
  34 #include "r600_resource.h"
  35 #include "evergreen_compute.h"
  36
  37 #define R600_MAX_CONST_BUFFERS 2
  38 #define R600_MAX_CONST_BUFFER_SIZE 4096
  39
  40 #ifdef PIPE_ARCH_BIG_ENDIAN
  41 #define R600_BIG_ENDIAN 1
  42 #else
  43 #define R600_BIG_ENDIAN 0
  44 #endif
  45
  46 enum r600_atom_flags {
  47         /* When set, atoms are added at the beginning of the dirty list
  48          * instead of the end. */
  49         EMIT_EARLY = (1 << 0)
  50 };
  51
  52 /* This encapsulates a state or an operation which can emitted into the GPU
  53  * command stream. It's not limited to states only, it can be used for anything
  54  * that wants to write commands into the CS (e.g. cache flushes). */
  55 struct r600_atom {
  56         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  57
  58         unsigned                num_dw;
  59         enum r600_atom_flags    flags;
  60         bool                    dirty;
  61
  62         struct list_head        head;
  63 };
  64
  65 /* This is an atom containing GPU commands that never change.
  66  * This is supposed to be copied directly into the CS. */
  67 struct r600_command_buffer {
  68         struct r600_atom atom;
  69         uint32_t *buf;
  70         unsigned max_num_dw;
  71         unsigned pkt_flags;
  72 };
  73
  74 struct r600_surface_sync_cmd {
  75         struct r600_atom atom;
  76         unsigned flush_flags; /* CP_COHER_CNTL */
  77 };
  78
  79 struct r600_db_misc_state {
  80         struct r600_atom atom;
  81         bool occlusion_query_enabled;
  82         bool flush_depthstencil_enabled;
  83 };
  84
  85 enum r600_pipe_state_id {
  86         R600_PIPE_STATE_BLEND = 0,
  87         R600_PIPE_STATE_BLEND_COLOR,
  88         R600_PIPE_STATE_CONFIG,
  89         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  90         R600_PIPE_STATE_CLIP,
  91         R600_PIPE_STATE_SCISSOR,
  92         R600_PIPE_STATE_VIEWPORT,
  93         R600_PIPE_STATE_RASTERIZER,
  94         R600_PIPE_STATE_VGT,
  95         R600_PIPE_STATE_FRAMEBUFFER,
  96         R600_PIPE_STATE_DSA,
  97         R600_PIPE_STATE_STENCIL_REF,
  98         R600_PIPE_STATE_PS_SHADER,
  99         R600_PIPE_STATE_VS_SHADER,
 100         R600_PIPE_STATE_CONSTANT,
 101         R600_PIPE_STATE_SAMPLER,
 102         R600_PIPE_STATE_RESOURCE,
 103         R600_PIPE_STATE_POLYGON_OFFSET,
 104         R600_PIPE_STATE_FETCH_SHADER,
 105         R600_PIPE_STATE_SPI,
 106         R600_PIPE_NSTATES
 107 };
 108
 109 struct compute_memory_pool;
 110 void compute_memory_pool_delete(struct compute_memory_pool* pool);
 111 struct compute_memory_pool* compute_memory_pool_new(
 112         int64_t initial_size_in_dw,
 113         struct r600_screen *rscreen);
 114
 115 struct r600_pipe_fences {
 116         struct r600_resource            *bo;
 117         unsigned                        *data;
 118         unsigned                        next_index;
 119         /* linked list of preallocated blocks */
 120         struct list_head                blocks;
 121         /* linked list of freed fences */
 122         struct list_head                pool;
 123         pipe_mutex                      mutex;
 124 };
 125
 126 struct r600_screen {
 127         struct pipe_screen              screen;
 128         struct radeon_winsys            *ws;
 129         unsigned                        family;
 130         enum chip_class                 chip_class;
 131         struct radeon_info              info;
 132         bool                            has_streamout;
 133         struct r600_tiling_info         tiling_info;
 134         struct r600_pipe_fences         fences;
 135
 136         bool                            use_surface_alloc;
 137         int                             glsl_feature_level;
 138
 139         /*for compute global memory binding, we allocate stuff here, instead of
 140          * buffers.
 141          * XXX: Not sure if this is the best place for global_pool.  Also,
 142          * it's not thread safe, so it won't work with multiple contexts. */
 143         struct compute_memory_pool *global_pool;
 144 };
 145
 146 struct r600_pipe_sampler_view {
 147         struct pipe_sampler_view        base;
 148         struct r600_pipe_resource_state         state;
 149 };
 150
 151 struct r600_pipe_rasterizer {
 152         struct r600_pipe_state          rstate;
 153         boolean                         flatshade;
 154         boolean                         two_side;
 155         unsigned                        sprite_coord_enable;
 156         unsigned                        clip_plane_enable;
 157         unsigned                        pa_sc_line_stipple;
 158         unsigned                        pa_cl_clip_cntl;
 159         float                           offset_units;
 160         float                           offset_scale;
 161         bool                            scissor_enable;
 162 };
 163
 164 struct r600_pipe_blend {
 165         struct r600_pipe_state          rstate;
 166         unsigned                        cb_target_mask;
 167         unsigned                        cb_color_control;
 168         bool                            dual_src_blend;
 169 };
 170
 171 struct r600_pipe_dsa {
 172         struct r600_pipe_state          rstate;
 173         unsigned                        alpha_ref;
 174         ubyte                           valuemask[2];
 175         ubyte                           writemask[2];
 176         bool                            is_flush;
 177         unsigned                        sx_alpha_test_control;
 178 };
 179
 180 struct r600_vertex_element
 181 {
 182         unsigned                        count;
 183         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 184         struct r600_resource            *fetch_shader;
 185         unsigned                        fs_size;
 186         struct r600_pipe_state          rstate;
 187 };
 188
 189 struct r600_pipe_shader;
 190
 191 struct r600_pipe_shader_selector {
 192         struct r600_pipe_shader *current;
 193
 194         struct tgsi_token       *tokens;
 195         struct pipe_stream_output_info  so;
 196
 197         unsigned        num_shaders;
 198
 199         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 200         unsigned        type;
 201
 202         unsigned        nr_ps_max_color_exports;
 203 };
 204
 205 struct r600_pipe_shader {
 206         struct r600_pipe_shader_selector *selector;
 207         struct r600_pipe_shader *next_variant;
 208         struct r600_shader              shader;
 209         struct r600_pipe_state          rstate;
 210         struct r600_resource            *bo;
 211         struct r600_resource            *bo_fetch;
 212         struct r600_vertex_element      vertex_elements;
 213         unsigned        sprite_coord_enable;
 214         unsigned        flatshade;
 215         unsigned        pa_cl_vs_out_cntl;
 216         unsigned        ps_cb_shader_mask;
 217         unsigned        key;
 218         unsigned                db_shader_control;
 219         unsigned                ps_depth_export;
 220 };
 221
 222 struct r600_pipe_sampler_state {
 223         struct r600_pipe_state          rstate;
 224         boolean seamless_cube_map;
 225 };
 226
 227 /* needed for blitter save */
 228 #define NUM_TEX_UNITS 16
 229
 230 struct r600_textures_info {
 231         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 232         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 233         unsigned                        n_views;
 234         unsigned                        n_samplers;
 235         bool                            samplers_dirty;
 236         bool                            is_array_sampler[NUM_TEX_UNITS];
 237 };
 238
 239 struct r600_fence {
 240         struct pipe_reference           reference;
 241         unsigned                        index; /* in the shared bo */
 242         struct r600_resource            *sleep_bo;
 243         struct list_head                head;
 244 };
 245
 246 #define FENCE_BLOCK_SIZE 16
 247
 248 struct r600_fence_block {
 249         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 250         struct list_head                head;
 251 };
 252
 253 #define R600_CONSTANT_ARRAY_SIZE 256
 254 #define R600_RESOURCE_ARRAY_SIZE 160
 255
 256 struct r600_stencil_ref
 257 {
 258         ubyte ref_value[2];
 259         ubyte valuemask[2];
 260         ubyte writemask[2];
 261 };
 262
 263 struct r600_constbuf_state
 264 {
 265         struct r600_atom                atom;
 266         struct pipe_constant_buffer     cb[PIPE_MAX_CONSTANT_BUFFERS];
 267         uint32_t                        enabled_mask;
 268         uint32_t                        dirty_mask;
 269 };
 270
 271 struct r600_context {
 272         struct pipe_context             context;
 273         struct blitter_context          *blitter;
 274         enum radeon_family              family;
 275         enum chip_class                 chip_class;
 276         boolean                         has_vertex_cache;
 277         unsigned                        r6xx_num_clause_temp_gprs;
 278         void                            *custom_dsa_flush;
 279         struct r600_screen              *screen;
 280         struct radeon_winsys            *ws;
 281         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 282         struct r600_vertex_element      *vertex_elements;
 283         struct pipe_framebuffer_state   framebuffer;
 284         unsigned                        cb_target_mask;
 285         unsigned                        fb_cb_shader_mask;
 286         unsigned                        sx_alpha_test_control;
 287         unsigned                        cb_shader_mask;
 288         unsigned                        db_shader_control;
 289         unsigned                        cb_color_control;
 290         unsigned                        pa_sc_line_stipple;
 291         unsigned                        pa_cl_clip_cntl;
 292         /* for saving when using blitter */
 293         struct pipe_stencil_ref         stencil_ref;
 294         struct pipe_viewport_state      viewport;
 295         struct pipe_clip_state          clip;
 296         struct r600_pipe_shader_selector        *ps_shader;
 297         struct r600_pipe_shader_selector        *vs_shader;
 298         struct r600_pipe_compute        *cs_shader;
 299         struct r600_pipe_rasterizer     *rasterizer;
 300         struct r600_pipe_state          vgt;
 301         struct r600_pipe_state          spi;
 302         struct pipe_query               *current_render_cond;
 303         unsigned                        current_render_cond_mode;
 304         struct pipe_query               *saved_render_cond;
 305         unsigned                        saved_render_cond_mode;
 306         /* shader information */
 307         boolean                         two_side;
 308         boolean                         spi_dirty;
 309         unsigned                        sprite_coord_enable;
 310         boolean                         flatshade;
 311         boolean                         export_16bpc;
 312         unsigned                        alpha_ref;
 313         boolean                         alpha_ref_dirty;
 314         unsigned                        nr_cbufs;
 315         struct r600_textures_info       vs_samplers;
 316         struct r600_textures_info       ps_samplers;
 317
 318         struct u_upload_mgr             *uploader;
 319         struct util_slab_mempool        pool_transfers;
 320         boolean                         have_depth_texture, have_depth_fb;
 321
 322         unsigned default_ps_gprs, default_vs_gprs;
 323
 324         /* States based on r600_atom. */
 325         struct list_head                dirty_states;
 326         struct r600_command_buffer      start_cs_cmd; /* invariant state mostly */
 327         struct r600_surface_sync_cmd    surface_sync_cmd;
 328         struct r600_atom                r6xx_flush_and_inv_cmd;
 329         struct r600_db_misc_state       db_misc_state;
 330         struct r600_atom                vertex_buffer_state;
 331         struct r600_constbuf_state      vs_constbuf_state;
 332         struct r600_constbuf_state      ps_constbuf_state;
 333
 334         struct radeon_winsys_cs *cs;
 335
 336         struct r600_range       *range;
 337         unsigned                nblocks;
 338         struct r600_block       **blocks;
 339         struct list_head        dirty;
 340         struct list_head        resource_dirty;
 341         struct list_head        enable_list;
 342         unsigned                pm4_dirty_cdwords;
 343         unsigned                ctx_pm4_ndwords;
 344
 345         /* The list of active queries. Only one query of each type can be active. */
 346         int                     num_occlusion_queries;
 347
 348         /* Manage queries in two separate groups:
 349          * The timer ones and the others (streamout, occlusion).
 350          *
 351          * We do this because we should only suspend non-timer queries for u_blitter,
 352          * and later if the non-timer queries are suspended, the context flush should
 353          * only suspend and resume the timer queries. */
 354         struct list_head        active_timer_queries;
 355         unsigned                num_cs_dw_timer_queries_suspend;
 356         struct list_head        active_nontimer_queries;
 357         unsigned                num_cs_dw_nontimer_queries_suspend;
 358
 359         unsigned                num_cs_dw_streamout_end;
 360
 361         unsigned                backend_mask;
 362         unsigned                max_db; /* for OQ */
 363         unsigned                flags;
 364         boolean                 predicate_drawing;
 365         struct r600_range       ps_resources;
 366         struct r600_range       vs_resources;
 367         int                     num_ps_resources, num_vs_resources;
 368
 369         unsigned                num_so_targets;
 370         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 371         boolean                 streamout_start;
 372         unsigned                streamout_append_bitmask;
 373
 374         /* There is no scissor enable bit on r6xx, so we must use a workaround.
 375          * These track the current scissor state. */
 376         bool                    scissor_enable;
 377         struct pipe_scissor_state scissor_state;
 378
 379         /* With rasterizer discard, there doesn't have to be a pixel shader.
 380          * In that case, we bind this one: */
 381         void                    *dummy_pixel_shader;
 382
 383         boolean                 dual_src_blend;
 384
 385         /* Vertex and index buffers. */
 386         bool                    vertex_buffers_dirty;
 387         struct pipe_index_buffer index_buffer;
 388         struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 389         unsigned                nr_vertex_buffers;
 390 };
 391
 392 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 393 {
 394         atom->emit(rctx, atom);
 395         atom->dirty = false;
 396         if (atom->head.next && atom->head.prev)
 397                 LIST_DELINIT(&atom->head);
 398 }
 399
 400 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 401 {
 402         if (!state->dirty) {
 403                 if (state->flags & EMIT_EARLY) {
 404                         LIST_ADD(&state->head, &rctx->dirty_states);
 405                 } else {
 406                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 407                 }
 408                 state->dirty = true;
 409         }
 410 }
 411
 412 /* evergreen_state.c */
 413 void evergreen_init_state_functions(struct r600_context *rctx);
 414 void evergreen_init_atom_start_cs(struct r600_context *rctx);
 415 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 416 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 417 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 418 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 419 void evergreen_polygon_offset_update(struct r600_context *rctx);
 420 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 421                                       enum pipe_format format,
 422                                       enum pipe_texture_target target,
 423                                       unsigned sample_count,
 424                                       unsigned usage);
 425
 426 void evergreen_update_dual_export_state(struct r600_context * rctx);
 427
 428 /* r600_blit.c */
 429 void r600_init_blit_functions(struct r600_context *rctx);
 430 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 431 void r600_flush_depth_textures(struct r600_context *rctx);
 432
 433 /* r600_buffer.c */
 434 bool r600_init_resource(struct r600_screen *rscreen,
 435                         struct r600_resource *res,
 436                         unsigned size, unsigned alignment,
 437                         unsigned bind, unsigned usage);
 438 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 439                                          const struct pipe_resource *templ);
 440
 441 /* r600_pipe.c */
 442 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 443                 unsigned flags);
 444
 445 /* r600_query.c */
 446 void r600_init_query_functions(struct r600_context *rctx);
 447 void r600_suspend_nontimer_queries(struct r600_context *ctx);
 448 void r600_resume_nontimer_queries(struct r600_context *ctx);
 449 void r600_suspend_timer_queries(struct r600_context *ctx);
 450 void r600_resume_timer_queries(struct r600_context *ctx);
 451
 452 /* r600_resource.c */
 453 void r600_init_context_resource_functions(struct r600_context *r600);
 454
 455 /* r600_shader.c */
 456 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 457 #ifdef HAVE_OPENCL
 458 int r600_compute_shader_create(struct pipe_context * ctx,
 459         LLVMModuleRef mod,  struct r600_bytecode * bytecode);
 460 #endif
 461 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 462
 463 /* r600_state.c */
 464 void r600_set_scissor_state(struct r600_context *rctx,
 465                             const struct pipe_scissor_state *state);
 466 void r600_update_sampler_states(struct r600_context *rctx);
 467 void r600_init_state_functions(struct r600_context *rctx);
 468 void r600_init_atom_start_cs(struct r600_context *rctx);
 469 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 470 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 471 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 472 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 473 void r600_polygon_offset_update(struct r600_context *rctx);
 474 void r600_adjust_gprs(struct r600_context *rctx);
 475 boolean r600_is_format_supported(struct pipe_screen *screen,
 476                                  enum pipe_format format,
 477                                  enum pipe_texture_target target,
 478                                  unsigned sample_count,
 479                                  unsigned usage);
 480 void r600_update_dual_export_state(struct r600_context * rctx);
 481
 482 /* r600_texture.c */
 483 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 484 void r600_init_surface_functions(struct r600_context *r600);
 485 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 486                                   const unsigned char *swizzle_view,
 487                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 488 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 489                                         unsigned level, unsigned layer);
 490
 491 /* r600_translate.c */
 492 void r600_translate_index_buffer(struct r600_context *r600,
 493                                  struct pipe_index_buffer *ib,
 494                                  unsigned count);
 495
 496 /* r600_state_common.c */
 497 void r600_init_atom(struct r600_atom *atom,
 498                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
 499                     unsigned num_dw, enum r600_atom_flags flags);
 500 void r600_init_common_atoms(struct r600_context *rctx);
 501 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 502 void r600_texture_barrier(struct pipe_context *ctx);
 503 void r600_set_index_buffer(struct pipe_context *ctx,
 504                            const struct pipe_index_buffer *ib);
 505 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 506                              const struct pipe_vertex_buffer *buffers);
 507 void *r600_create_vertex_elements(struct pipe_context *ctx,
 508                                   unsigned count,
 509                                   const struct pipe_vertex_element *elements);
 510 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 511 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 512 void r600_set_blend_color(struct pipe_context *ctx,
 513                           const struct pipe_blend_color *state);
 514 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 515 void r600_set_max_scissor(struct r600_context *rctx);
 516 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 517 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 518 void r600_sampler_view_destroy(struct pipe_context *ctx,
 519                                struct pipe_sampler_view *state);
 520 void r600_delete_state(struct pipe_context *ctx, void *state);
 521 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 522 void *r600_create_shader_state_ps(struct pipe_context *ctx,
 523                    const struct pipe_shader_state *state);
 524 void *r600_create_shader_state_vs(struct pipe_context *ctx,
 525                    const struct pipe_shader_state *state);
 526 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 527 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 528 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 529 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 530 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
 531 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 532                               struct pipe_constant_buffer *cb);
 533 struct pipe_stream_output_target *
 534 r600_create_so_target(struct pipe_context *ctx,
 535                       struct pipe_resource *buffer,
 536                       unsigned buffer_offset,
 537                       unsigned buffer_size);
 538 void r600_so_target_destroy(struct pipe_context *ctx,
 539                             struct pipe_stream_output_target *target);
 540 void r600_set_so_targets(struct pipe_context *ctx,
 541                          unsigned num_targets,
 542                          struct pipe_stream_output_target **targets,
 543                          unsigned append_bitmask);
 544 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 545                                const struct pipe_stencil_ref *state);
 546 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 547 uint32_t r600_translate_stencil_op(int s_op);
 548 uint32_t r600_translate_fill(uint32_t func);
 549 unsigned r600_tex_wrap(unsigned wrap);
 550 unsigned r600_tex_filter(unsigned filter);
 551 unsigned r600_tex_mipfilter(unsigned filter);
 552 unsigned r600_tex_compare(unsigned compare);
 553
 554 /*
 555  * Helpers for building command buffers
 556  */
 557
 558 #define PKT3_SET_CONFIG_REG     0x68
 559 #define PKT3_SET_CONTEXT_REG    0x69
 560 #define PKT3_SET_CTL_CONST      0x6F
 561 #define PKT3_SET_LOOP_CONST                    0x6C
 562
 563 #define R600_CONFIG_REG_OFFSET  0x08000
 564 #define R600_CONTEXT_REG_OFFSET 0x28000
 565 #define R600_CTL_CONST_OFFSET   0x3CFF0
 566 #define R600_LOOP_CONST_OFFSET                 0X0003E200
 567 #define EG_LOOP_CONST_OFFSET               0x0003A200
 568
 569 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 570 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 571 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
 572 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 573 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 574
 575 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
 576 {
 577         cb->buf[cb->atom.num_dw++] = value;
 578 }
 579
 580 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 581 {
 582         assert(reg < R600_CONTEXT_REG_OFFSET);
 583         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 584         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 585         cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 586 }
 587
 588 /**
 589  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 590  * shaders.
 591  */
 592 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 593 {
 594         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 595         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 596         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
 597         cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 598 }
 599
 600 /**
 601  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 602  * shaders.
 603  */
 604 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 605 {
 606         assert(reg >= R600_CTL_CONST_OFFSET);
 607         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 608         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
 609         cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 610 }
 611
 612 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 613 {
 614         assert(reg >= R600_LOOP_CONST_OFFSET);
 615         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 616         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 617         cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
 618 }
 619
 620 /**
 621  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 622  * shaders.
 623  */
 624 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 625 {
 626         assert(reg >= EG_LOOP_CONST_OFFSET);
 627         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 628         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
 629         cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
 630 }
 631
 632 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 633 {
 634         r600_store_config_reg_seq(cb, reg, 1);
 635         r600_store_value(cb, value);
 636 }
 637
 638 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 639 {
 640         r600_store_context_reg_seq(cb, reg, 1);
 641         r600_store_value(cb, value);
 642 }
 643
 644 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 645 {
 646         r600_store_ctl_const_seq(cb, reg, 1);
 647         r600_store_value(cb, value);
 648 }
 649
 650 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 651 {
 652         r600_store_loop_const_seq(cb, reg, 1);
 653         r600_store_value(cb, value);
 654 }
 655
 656 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 657 {
 658         eg_store_loop_const_seq(cb, reg, 1);
 659         r600_store_value(cb, value);
 660 }
 661
 662 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
 663 void r600_release_command_buffer(struct r600_command_buffer *cb);
 664
 665 /*
 666  * Helpers for emitting state into a command stream directly.
 667  */
 668
 669 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
 670                                              enum radeon_bo_usage usage)
 671 {
 672         assert(usage);
 673         return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
 674 }
 675
 676 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
 677 {
 678         cs->buf[cs->cdw++] = value;
 679 }
 680
 681 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 682 {
 683         assert(reg < R600_CONTEXT_REG_OFFSET);
 684         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 685         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 686         cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 687 }
 688
 689 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 690 {
 691         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 692         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 693         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 694         cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 695 }
 696
 697 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 698 {
 699         assert(reg >= R600_CTL_CONST_OFFSET);
 700         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 701         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 702         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 703 }
 704
 705 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 706 {
 707         r600_write_config_reg_seq(cs, reg, 1);
 708         r600_write_value(cs, value);
 709 }
 710
 711 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 712 {
 713         r600_write_context_reg_seq(cs, reg, 1);
 714         r600_write_value(cs, value);
 715 }
 716
 717 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 718 {
 719         r600_write_ctl_const_seq(cs, reg, 1);
 720         r600_write_value(cs, value);
 721 }
 722
 723 /*
 724  * common helpers
 725  */
 726 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 727 {
 728         return value * (1 << frac_bits);
 729 }
 730 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 731
 732 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 733 {
 734         if (filter <= 1)   return 0;
 735         if (filter <= 2)   return 1;
 736         if (filter <= 4)   return 2;
 737         if (filter <= 8)   return 3;
 738          /* else */        return 4;
 739 }
 740
 741 /* 12.4 fixed-point */
 742 static INLINE unsigned r600_pack_float_12p4(float x)
 743 {
 744         return x <= 0    ? 0 :
 745                x >= 4096 ? 0xffff : x * 16;
 746 }
 747
 748 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 749 {
 750         struct r600_screen *rscreen = (struct r600_screen*)screen;
 751         struct r600_resource *rresource = (struct r600_resource*)resource;
 752
 753         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 754 }
 755
 756 #endif