2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../../winsys/radeon/drm/radeon_winsys.h"
31 #include "pipe/p_state.h"
32 #include "pipe/p_screen.h"
33 #include "pipe/p_context.h"
34 #include "util/u_math.h"
35 #include "util/u_slab.h"
36 #include "util/u_vbuf.h"
38 #include "r600_public.h"
39 #include "r600_shader.h"
40 #include "r600_resource.h"
42 #define R600_MAX_CONST_BUFFERS 2
43 #define R600_MAX_CONST_BUFFER_SIZE 4096
45 #ifdef PIPE_ARCH_BIG_ENDIAN
46 #define R600_BIG_ENDIAN 1
48 #define R600_BIG_ENDIAN 0
51 enum r600_pipe_state_id {
52 R600_PIPE_STATE_BLEND = 0,
53 R600_PIPE_STATE_BLEND_COLOR,
54 R600_PIPE_STATE_CONFIG,
55 R600_PIPE_STATE_SEAMLESS_CUBEMAP,
57 R600_PIPE_STATE_SCISSOR,
58 R600_PIPE_STATE_VIEWPORT,
59 R600_PIPE_STATE_RASTERIZER,
61 R600_PIPE_STATE_FRAMEBUFFER,
63 R600_PIPE_STATE_STENCIL_REF,
64 R600_PIPE_STATE_PS_SHADER,
65 R600_PIPE_STATE_VS_SHADER,
66 R600_PIPE_STATE_CONSTANT,
67 R600_PIPE_STATE_SAMPLER,
68 R600_PIPE_STATE_RESOURCE,
69 R600_PIPE_STATE_POLYGON_OFFSET,
70 R600_PIPE_STATE_FETCH_SHADER,
74 struct r600_pipe_fences {
75 struct r600_resource *bo;
78 /* linked list of preallocated blocks */
79 struct list_head blocks;
80 /* linked list of freed fences */
81 struct list_head pool;
86 struct pipe_screen screen;
87 struct radeon_winsys *ws;
89 enum chip_class chip_class;
90 struct radeon_info info;
91 struct r600_tiling_info tiling_info;
92 struct util_slab_mempool pool_buffers;
93 struct r600_pipe_fences fences;
95 unsigned num_contexts;
97 /* for thread-safe write accessing to num_contexts */
98 pipe_mutex mutex_num_contexts;
101 struct r600_pipe_sampler_view {
102 struct pipe_sampler_view base;
103 struct r600_pipe_resource_state state;
106 struct r600_pipe_rasterizer {
107 struct r600_pipe_state rstate;
110 unsigned sprite_coord_enable;
111 unsigned clip_plane_enable;
112 unsigned pa_sc_line_stipple;
113 unsigned pa_su_sc_mode_cntl;
114 unsigned pa_cl_clip_cntl;
119 struct r600_pipe_blend {
120 struct r600_pipe_state rstate;
121 unsigned cb_target_mask;
122 unsigned cb_color_control;
125 struct r600_pipe_dsa {
126 struct r600_pipe_state rstate;
128 unsigned db_render_override;
129 unsigned db_render_control;
134 struct r600_vertex_element
137 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
138 struct u_vbuf_elements *vmgr_elements;
139 struct r600_resource *fetch_shader;
141 struct r600_pipe_state rstate;
142 /* if offset is to big for fetch instructio we need to alterate
143 * offset of vertex buffer, record here the offset need to add
145 unsigned vbuffer_need_offset;
146 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS];
149 struct r600_pipe_shader {
150 struct r600_shader shader;
151 struct r600_pipe_state rstate;
152 struct r600_resource *bo;
153 struct r600_resource *bo_fetch;
154 struct r600_vertex_element vertex_elements;
155 struct tgsi_token *tokens;
156 unsigned sprite_coord_enable;
158 unsigned pa_cl_vs_out_cntl;
159 struct pipe_stream_output_info so;
162 struct r600_pipe_sampler_state {
163 struct r600_pipe_state rstate;
164 boolean seamless_cube_map;
167 /* needed for blitter save */
168 #define NUM_TEX_UNITS 16
170 struct r600_textures_info {
171 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
172 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS];
176 bool is_array_sampler[NUM_TEX_UNITS];
180 struct pipe_reference reference;
181 unsigned index; /* in the shared bo */
182 struct list_head head;
185 #define FENCE_BLOCK_SIZE 16
187 struct r600_fence_block {
188 struct r600_fence fences[FENCE_BLOCK_SIZE];
189 struct list_head head;
192 #define R600_CONSTANT_ARRAY_SIZE 256
193 #define R600_RESOURCE_ARRAY_SIZE 160
195 struct r600_stencil_ref
202 struct r600_context {
203 struct pipe_context context;
204 struct blitter_context *blitter;
205 enum radeon_family family;
206 enum chip_class chip_class;
207 unsigned r6xx_num_clause_temp_gprs;
208 void *custom_dsa_flush;
209 struct r600_screen *screen;
210 struct radeon_winsys *ws;
211 struct r600_pipe_state *states[R600_PIPE_NSTATES];
212 struct r600_vertex_element *vertex_elements;
213 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
214 struct pipe_framebuffer_state framebuffer;
215 unsigned cb_target_mask;
216 unsigned cb_color_control;
217 unsigned pa_sc_line_stipple;
218 unsigned pa_su_sc_mode_cntl;
219 unsigned pa_cl_clip_cntl;
220 /* for saving when using blitter */
221 struct pipe_stencil_ref stencil_ref;
222 struct pipe_viewport_state viewport;
223 struct pipe_clip_state clip;
224 struct r600_pipe_state config;
225 struct r600_pipe_shader *ps_shader;
226 struct r600_pipe_shader *vs_shader;
227 struct r600_pipe_state vs_const_buffer;
228 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
229 struct r600_pipe_state ps_const_buffer;
230 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
231 struct r600_pipe_rasterizer *rasterizer;
232 struct r600_pipe_state vgt;
233 struct r600_pipe_state spi;
234 struct pipe_query *current_render_cond;
235 unsigned current_render_cond_mode;
236 struct pipe_query *saved_render_cond;
237 unsigned saved_render_cond_mode;
238 /* shader information */
240 unsigned sprite_coord_enable;
241 boolean export_16bpc;
243 boolean alpha_ref_dirty;
245 struct r600_textures_info vs_samplers;
246 struct r600_textures_info ps_samplers;
248 struct u_vbuf *vbuf_mgr;
249 struct util_slab_mempool pool_transfers;
250 boolean have_depth_texture, have_depth_fb;
252 unsigned default_ps_gprs, default_vs_gprs;
254 /* Below are variables from the old r600_context.
256 struct radeon_winsys_cs *cs;
258 struct r600_range *range;
260 struct r600_block **blocks;
261 struct list_head dirty;
262 struct list_head resource_dirty;
263 struct list_head enable_list;
264 unsigned pm4_dirty_cdwords;
265 unsigned ctx_pm4_ndwords;
266 unsigned init_dwords;
269 struct r600_resource **bo;
272 unsigned pm4_cdwords;
274 /* The list of active queries. Only one query of each type can be active. */
275 struct list_head active_query_list;
276 unsigned num_cs_dw_queries_suspend;
277 unsigned num_cs_dw_streamout_end;
279 unsigned backend_mask;
280 unsigned max_db; /* for OQ */
281 unsigned num_dest_buffers;
283 boolean predicate_drawing;
284 struct r600_range ps_resources;
285 struct r600_range vs_resources;
286 struct r600_range fs_resources;
287 int num_ps_resources, num_vs_resources, num_fs_resources;
289 unsigned num_so_targets;
290 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
291 boolean streamout_start;
292 unsigned streamout_append_bitmask;
293 unsigned *vs_so_stride_in_dw;
296 /* evergreen_state.c */
297 void evergreen_init_state_functions(struct r600_context *rctx);
298 void evergreen_init_config(struct r600_context *rctx);
299 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
300 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
301 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
302 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
303 void evergreen_polygon_offset_update(struct r600_context *rctx);
304 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
305 struct r600_pipe_resource_state *rstate);
306 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
307 struct r600_pipe_resource_state *rstate,
308 struct r600_resource *rbuffer,
309 unsigned offset, unsigned stride,
310 enum radeon_bo_usage usage);
311 boolean evergreen_is_format_supported(struct pipe_screen *screen,
312 enum pipe_format format,
313 enum pipe_texture_target target,
314 unsigned sample_count,
318 void r600_init_blit_functions(struct r600_context *rctx);
319 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
320 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
321 void r600_flush_depth_textures(struct r600_context *rctx);
324 bool r600_init_resource(struct r600_screen *rscreen,
325 struct r600_resource *res,
326 unsigned size, unsigned alignment,
327 unsigned bind, unsigned usage);
328 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
329 const struct pipe_resource *templ);
330 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
331 void *ptr, unsigned bytes,
333 void r600_upload_index_buffer(struct r600_context *rctx,
334 struct pipe_index_buffer *ib, unsigned count);
338 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
342 void r600_init_query_functions(struct r600_context *rctx);
344 /* r600_resource.c */
345 void r600_init_context_resource_functions(struct r600_context *r600);
348 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
349 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
350 int r600_find_vs_semantic_index(struct r600_shader *vs,
351 struct r600_shader *ps, int id);
354 void r600_update_sampler_states(struct r600_context *rctx);
355 void r600_init_state_functions(struct r600_context *rctx);
356 void r600_init_config(struct r600_context *rctx);
357 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
358 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
359 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
360 void *r600_create_db_flush_dsa(struct r600_context *rctx);
361 void r600_polygon_offset_update(struct r600_context *rctx);
362 void r600_pipe_init_buffer_resource(struct r600_context *rctx,
363 struct r600_pipe_resource_state *rstate);
364 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
365 struct r600_resource *rbuffer,
366 unsigned offset, unsigned stride,
367 enum radeon_bo_usage usage);
368 void r600_adjust_gprs(struct r600_context *rctx);
369 boolean r600_is_format_supported(struct pipe_screen *screen,
370 enum pipe_format format,
371 enum pipe_texture_target target,
372 unsigned sample_count,
376 void r600_init_screen_texture_functions(struct pipe_screen *screen);
377 void r600_init_surface_functions(struct r600_context *r600);
378 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
379 const unsigned char *swizzle_view,
380 uint32_t *word4_p, uint32_t *yuv_format_p);
381 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
382 unsigned level, unsigned layer);
384 /* r600_translate.c */
385 void r600_translate_index_buffer(struct r600_context *r600,
386 struct pipe_index_buffer *ib,
389 /* r600_state_common.c */
390 void r600_set_index_buffer(struct pipe_context *ctx,
391 const struct pipe_index_buffer *ib);
392 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
393 const struct pipe_vertex_buffer *buffers);
394 void *r600_create_vertex_elements(struct pipe_context *ctx,
396 const struct pipe_vertex_element *elements);
397 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
398 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
399 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
400 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
401 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
402 void r600_sampler_view_destroy(struct pipe_context *ctx,
403 struct pipe_sampler_view *state);
404 void r600_delete_state(struct pipe_context *ctx, void *state);
405 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
406 void *r600_create_shader_state(struct pipe_context *ctx,
407 const struct pipe_shader_state *state);
408 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
409 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
410 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
411 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
412 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
413 struct pipe_resource *buffer);
414 struct pipe_stream_output_target *
415 r600_create_so_target(struct pipe_context *ctx,
416 struct pipe_resource *buffer,
417 unsigned buffer_offset,
418 unsigned buffer_size);
419 void r600_so_target_destroy(struct pipe_context *ctx,
420 struct pipe_stream_output_target *target);
421 void r600_set_so_targets(struct pipe_context *ctx,
422 unsigned num_targets,
423 struct pipe_stream_output_target **targets,
424 unsigned append_bitmask);
425 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
426 const struct pipe_stencil_ref *state);
427 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
432 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
434 return value * (1 << frac_bits);
436 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
438 static inline unsigned r600_tex_aniso_filter(unsigned filter)
440 if (filter <= 1) return 0;
441 if (filter <= 2) return 1;
442 if (filter <= 4) return 2;
443 if (filter <= 8) return 3;
447 /* 12.4 fixed-point */
448 static INLINE unsigned r600_pack_float_12p4(float x)
451 x >= 4096 ? 0xffff : x * 16;