src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30
  31 #include "pipe/p_state.h"
  32 #include "pipe/p_screen.h"
  33 #include "pipe/p_context.h"
  34 #include "util/u_math.h"
  35 #include "util/u_slab.h"
  36 #include "util/u_vbuf.h"
  37 #include "r600.h"
  38 #include "r600_public.h"
  39 #include "r600_shader.h"
  40 #include "r600_resource.h"
  41
  42 #define R600_MAX_CONST_BUFFERS 2
  43 #define R600_MAX_CONST_BUFFER_SIZE 4096
  44
  45 #ifdef PIPE_ARCH_BIG_ENDIAN
  46 #define R600_BIG_ENDIAN 1
  47 #else
  48 #define R600_BIG_ENDIAN 0
  49 #endif
  50
  51 enum r600_atom_flags {
  52         /* When set, atoms are added at the beginning of the dirty list
  53          * instead of the end. */
  54         EMIT_EARLY = (1 << 0)
  55 };
  56
  57 /* This encapsulates a state or an operation which can emitted into the GPU
  58  * command stream. It's not limited to states only, it can be used for anything
  59  * that wants to write commands into the CS (e.g. cache flushes). */
  60 struct r600_atom {
  61         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  62
  63         unsigned                num_dw;
  64         enum r600_atom_flags    flags;
  65         bool                    dirty;
  66
  67         struct list_head        head;
  68 };
  69
  70 enum r600_pipe_state_id {
  71         R600_PIPE_STATE_BLEND = 0,
  72         R600_PIPE_STATE_BLEND_COLOR,
  73         R600_PIPE_STATE_CONFIG,
  74         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  75         R600_PIPE_STATE_CLIP,
  76         R600_PIPE_STATE_SCISSOR,
  77         R600_PIPE_STATE_VIEWPORT,
  78         R600_PIPE_STATE_RASTERIZER,
  79         R600_PIPE_STATE_VGT,
  80         R600_PIPE_STATE_FRAMEBUFFER,
  81         R600_PIPE_STATE_DSA,
  82         R600_PIPE_STATE_STENCIL_REF,
  83         R600_PIPE_STATE_PS_SHADER,
  84         R600_PIPE_STATE_VS_SHADER,
  85         R600_PIPE_STATE_CONSTANT,
  86         R600_PIPE_STATE_SAMPLER,
  87         R600_PIPE_STATE_RESOURCE,
  88         R600_PIPE_STATE_POLYGON_OFFSET,
  89         R600_PIPE_STATE_FETCH_SHADER,
  90         R600_PIPE_NSTATES
  91 };
  92
  93 struct r600_pipe_fences {
  94         struct r600_resource            *bo;
  95         unsigned                        *data;
  96         unsigned                        next_index;
  97         /* linked list of preallocated blocks */
  98         struct list_head                blocks;
  99         /* linked list of freed fences */
 100         struct list_head                pool;
 101         pipe_mutex                      mutex;
 102 };
 103
 104 struct r600_screen {
 105         struct pipe_screen              screen;
 106         struct radeon_winsys            *ws;
 107         unsigned                        family;
 108         enum chip_class                 chip_class;
 109         struct radeon_info              info;
 110         struct r600_tiling_info         tiling_info;
 111         struct util_slab_mempool        pool_buffers;
 112         struct r600_pipe_fences         fences;
 113
 114         unsigned                        num_contexts;
 115
 116         /* for thread-safe write accessing to num_contexts */
 117         pipe_mutex                      mutex_num_contexts;
 118 };
 119
 120 struct r600_pipe_sampler_view {
 121         struct pipe_sampler_view        base;
 122         struct r600_pipe_resource_state         state;
 123 };
 124
 125 struct r600_pipe_rasterizer {
 126         struct r600_pipe_state          rstate;
 127         boolean                         flatshade;
 128         boolean                         two_side;
 129         unsigned                        sprite_coord_enable;
 130         unsigned                        clip_plane_enable;
 131         unsigned                        pa_sc_line_stipple;
 132         unsigned                        pa_su_sc_mode_cntl;
 133         unsigned                        pa_cl_clip_cntl;
 134         float                           offset_units;
 135         float                           offset_scale;
 136 };
 137
 138 struct r600_pipe_blend {
 139         struct r600_pipe_state          rstate;
 140         unsigned                        cb_target_mask;
 141         unsigned                        cb_color_control;
 142 };
 143
 144 struct r600_pipe_dsa {
 145         struct r600_pipe_state          rstate;
 146         unsigned                        alpha_ref;
 147         unsigned                        db_render_override;
 148         unsigned                        db_render_control;
 149         ubyte                           valuemask[2];
 150         ubyte                           writemask[2];
 151 };
 152
 153 struct r600_vertex_element
 154 {
 155         unsigned                        count;
 156         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 157         struct u_vbuf_elements          *vmgr_elements;
 158         struct r600_resource            *fetch_shader;
 159         unsigned                        fs_size;
 160         struct r600_pipe_state          rstate;
 161         /* if offset is to big for fetch instructio we need to alterate
 162          * offset of vertex buffer, record here the offset need to add
 163          */
 164         unsigned                        vbuffer_need_offset;
 165         unsigned                        vbuffer_offset[PIPE_MAX_ATTRIBS];
 166 };
 167
 168 struct r600_pipe_shader {
 169         struct r600_shader              shader;
 170         struct r600_pipe_state          rstate;
 171         struct r600_resource            *bo;
 172         struct r600_resource            *bo_fetch;
 173         struct r600_vertex_element      vertex_elements;
 174         struct tgsi_token               *tokens;
 175         unsigned        sprite_coord_enable;
 176         unsigned        flatshade;
 177         unsigned        pa_cl_vs_out_cntl;
 178         struct pipe_stream_output_info  so;
 179 };
 180
 181 struct r600_pipe_sampler_state {
 182         struct r600_pipe_state          rstate;
 183         boolean seamless_cube_map;
 184 };
 185
 186 /* needed for blitter save */
 187 #define NUM_TEX_UNITS 16
 188
 189 struct r600_textures_info {
 190         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 191         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 192         unsigned                        n_views;
 193         unsigned                        n_samplers;
 194         bool                            samplers_dirty;
 195         bool                            is_array_sampler[NUM_TEX_UNITS];
 196 };
 197
 198 struct r600_fence {
 199         struct pipe_reference           reference;
 200         unsigned                        index; /* in the shared bo */
 201         struct list_head                head;
 202 };
 203
 204 #define FENCE_BLOCK_SIZE 16
 205
 206 struct r600_fence_block {
 207         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 208         struct list_head                head;
 209 };
 210
 211 #define R600_CONSTANT_ARRAY_SIZE 256
 212 #define R600_RESOURCE_ARRAY_SIZE 160
 213
 214 struct r600_stencil_ref
 215 {
 216         ubyte ref_value[2];
 217         ubyte valuemask[2];
 218         ubyte writemask[2];
 219 };
 220
 221 struct r600_context {
 222         struct pipe_context             context;
 223         struct blitter_context          *blitter;
 224         enum radeon_family              family;
 225         enum chip_class                 chip_class;
 226         unsigned                        r6xx_num_clause_temp_gprs;
 227         void                            *custom_dsa_flush;
 228         struct r600_screen              *screen;
 229         struct radeon_winsys            *ws;
 230         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 231         struct r600_vertex_element      *vertex_elements;
 232         struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
 233         struct pipe_framebuffer_state   framebuffer;
 234         unsigned                        cb_target_mask;
 235         unsigned                        cb_color_control;
 236         unsigned                        pa_sc_line_stipple;
 237         unsigned                        pa_su_sc_mode_cntl;
 238         unsigned                        pa_cl_clip_cntl;
 239         /* for saving when using blitter */
 240         struct pipe_stencil_ref         stencil_ref;
 241         struct pipe_viewport_state      viewport;
 242         struct pipe_clip_state          clip;
 243         struct r600_pipe_state          config;
 244         struct r600_pipe_shader         *ps_shader;
 245         struct r600_pipe_shader         *vs_shader;
 246         struct r600_pipe_state          vs_const_buffer;
 247         struct r600_pipe_resource_state         vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
 248         struct r600_pipe_state          ps_const_buffer;
 249         struct r600_pipe_resource_state         ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
 250         struct r600_pipe_rasterizer     *rasterizer;
 251         struct r600_pipe_state          vgt;
 252         struct r600_pipe_state          spi;
 253         struct pipe_query               *current_render_cond;
 254         unsigned                        current_render_cond_mode;
 255         struct pipe_query               *saved_render_cond;
 256         unsigned                        saved_render_cond_mode;
 257         /* shader information */
 258         boolean                         two_side;
 259         unsigned                        sprite_coord_enable;
 260         boolean                         export_16bpc;
 261         unsigned                        alpha_ref;
 262         boolean                         alpha_ref_dirty;
 263         unsigned                        nr_cbufs;
 264         struct r600_textures_info       vs_samplers;
 265         struct r600_textures_info       ps_samplers;
 266
 267         struct u_vbuf                   *vbuf_mgr;
 268         struct util_slab_mempool        pool_transfers;
 269         boolean                         have_depth_texture, have_depth_fb;
 270
 271         unsigned default_ps_gprs, default_vs_gprs;
 272
 273         /* States based on r600_state. */
 274         struct list_head                dirty_states;
 275
 276         /* Below are variables from the old r600_context.
 277          */
 278         struct radeon_winsys_cs *cs;
 279
 280         struct r600_range       *range;
 281         unsigned                nblocks;
 282         struct r600_block       **blocks;
 283         struct list_head        dirty;
 284         struct list_head        resource_dirty;
 285         struct list_head        enable_list;
 286         unsigned                pm4_dirty_cdwords;
 287         unsigned                ctx_pm4_ndwords;
 288         unsigned                init_dwords;
 289
 290         unsigned                creloc;
 291         struct r600_resource    **bo;
 292
 293         /* The list of active queries. Only one query of each type can be active. */
 294         struct list_head        active_query_list;
 295         unsigned                num_cs_dw_queries_suspend;
 296         unsigned                num_cs_dw_streamout_end;
 297
 298         unsigned                backend_mask;
 299         unsigned                max_db; /* for OQ */
 300         unsigned                num_dest_buffers;
 301         unsigned                flags;
 302         boolean                 predicate_drawing;
 303         struct r600_range       ps_resources;
 304         struct r600_range       vs_resources;
 305         struct r600_range       fs_resources;
 306         int                     num_ps_resources, num_vs_resources, num_fs_resources;
 307
 308         unsigned                num_so_targets;
 309         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 310         boolean                 streamout_start;
 311         unsigned                streamout_append_bitmask;
 312         unsigned                *vs_so_stride_in_dw;
 313 };
 314
 315 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 316 {
 317         atom->emit(rctx, atom);
 318         atom->dirty = false;
 319         if (atom->head.next && atom->head.prev)
 320                 LIST_DELINIT(&atom->head);
 321 }
 322
 323 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 324 {
 325         if (!state->dirty) {
 326                 if (state->flags & EMIT_EARLY) {
 327                         LIST_ADD(&state->head, &rctx->dirty_states);
 328                 } else {
 329                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 330                 }
 331                 state->dirty = true;
 332         }
 333 }
 334
 335 /* evergreen_state.c */
 336 void evergreen_init_state_functions(struct r600_context *rctx);
 337 void evergreen_init_config(struct r600_context *rctx);
 338 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 339 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 340 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 341 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 342 void evergreen_polygon_offset_update(struct r600_context *rctx);
 343 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
 344                                          struct r600_pipe_resource_state *rstate);
 345 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
 346                                         struct r600_pipe_resource_state *rstate,
 347                                         struct r600_resource *rbuffer,
 348                                         unsigned offset, unsigned stride,
 349                                         enum radeon_bo_usage usage);
 350 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 351                                       enum pipe_format format,
 352                                       enum pipe_texture_target target,
 353                                       unsigned sample_count,
 354                                       unsigned usage);
 355
 356 /* r600_blit.c */
 357 void r600_init_blit_functions(struct r600_context *rctx);
 358 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 359 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 360 void r600_flush_depth_textures(struct r600_context *rctx);
 361
 362 /* r600_buffer.c */
 363 bool r600_init_resource(struct r600_screen *rscreen,
 364                         struct r600_resource *res,
 365                         unsigned size, unsigned alignment,
 366                         unsigned bind, unsigned usage);
 367 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 368                                          const struct pipe_resource *templ);
 369 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
 370                                               void *ptr, unsigned bytes,
 371                                               unsigned bind);
 372 void r600_upload_index_buffer(struct r600_context *rctx,
 373                               struct pipe_index_buffer *ib, unsigned count);
 374
 375
 376 /* r600_pipe.c */
 377 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 378                 unsigned flags);
 379
 380 /* r600_query.c */
 381 void r600_init_query_functions(struct r600_context *rctx);
 382
 383 /* r600_resource.c */
 384 void r600_init_context_resource_functions(struct r600_context *r600);
 385
 386 /* r600_shader.c */
 387 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 388 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 389 int r600_find_vs_semantic_index(struct r600_shader *vs,
 390                                 struct r600_shader *ps, int id);
 391
 392 /* r600_state.c */
 393 void r600_update_sampler_states(struct r600_context *rctx);
 394 void r600_init_state_functions(struct r600_context *rctx);
 395 void r600_init_config(struct r600_context *rctx);
 396 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 397 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 398 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 399 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 400 void r600_polygon_offset_update(struct r600_context *rctx);
 401 void r600_pipe_init_buffer_resource(struct r600_context *rctx,
 402                                     struct r600_pipe_resource_state *rstate);
 403 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
 404                                    struct r600_resource *rbuffer,
 405                                    unsigned offset, unsigned stride,
 406                                    enum radeon_bo_usage usage);
 407 void r600_adjust_gprs(struct r600_context *rctx);
 408 boolean r600_is_format_supported(struct pipe_screen *screen,
 409                                  enum pipe_format format,
 410                                  enum pipe_texture_target target,
 411                                  unsigned sample_count,
 412                                  unsigned usage);
 413
 414 /* r600_texture.c */
 415 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 416 void r600_init_surface_functions(struct r600_context *r600);
 417 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 418                                   const unsigned char *swizzle_view,
 419                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 420 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 421                                         unsigned level, unsigned layer);
 422
 423 /* r600_translate.c */
 424 void r600_translate_index_buffer(struct r600_context *r600,
 425                                  struct pipe_index_buffer *ib,
 426                                  unsigned count);
 427
 428 /* r600_state_common.c */
 429 void r600_set_index_buffer(struct pipe_context *ctx,
 430                            const struct pipe_index_buffer *ib);
 431 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 432                              const struct pipe_vertex_buffer *buffers);
 433 void *r600_create_vertex_elements(struct pipe_context *ctx,
 434                                   unsigned count,
 435                                   const struct pipe_vertex_element *elements);
 436 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 437 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 438 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 439 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 440 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 441 void r600_sampler_view_destroy(struct pipe_context *ctx,
 442                                struct pipe_sampler_view *state);
 443 void r600_delete_state(struct pipe_context *ctx, void *state);
 444 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 445 void *r600_create_shader_state(struct pipe_context *ctx,
 446                                const struct pipe_shader_state *state);
 447 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 448 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 449 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 450 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 451 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 452                               struct pipe_resource *buffer);
 453 struct pipe_stream_output_target *
 454 r600_create_so_target(struct pipe_context *ctx,
 455                       struct pipe_resource *buffer,
 456                       unsigned buffer_offset,
 457                       unsigned buffer_size);
 458 void r600_so_target_destroy(struct pipe_context *ctx,
 459                             struct pipe_stream_output_target *target);
 460 void r600_set_so_targets(struct pipe_context *ctx,
 461                          unsigned num_targets,
 462                          struct pipe_stream_output_target **targets,
 463                          unsigned append_bitmask);
 464 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 465                                const struct pipe_stencil_ref *state);
 466 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 467
 468 /*
 469  * common helpers
 470  */
 471 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 472 {
 473         return value * (1 << frac_bits);
 474 }
 475 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 476
 477 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 478 {
 479         if (filter <= 1)   return 0;
 480         if (filter <= 2)   return 1;
 481         if (filter <= 4)   return 2;
 482         if (filter <= 8)   return 3;
 483          /* else */        return 4;
 484 }
 485
 486 /* 12.4 fixed-point */
 487 static INLINE unsigned r600_pack_float_12p4(float x)
 488 {
 489         return x <= 0    ? 0 :
 490                x >= 4096 ? 0xffff : x * 16;
 491 }
 492
 493 #endif