2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../../winsys/radeon/drm/radeon_winsys.h"
31 #include "pipe/p_state.h"
32 #include "pipe/p_screen.h"
33 #include "pipe/p_context.h"
34 #include "util/u_math.h"
35 #include "util/u_slab.h"
36 #include "util/u_vbuf.h"
38 #include "r600_public.h"
39 #include "r600_shader.h"
40 #include "r600_resource.h"
42 #define R600_MAX_CONST_BUFFERS 2
43 #define R600_MAX_CONST_BUFFER_SIZE 4096
45 #ifdef PIPE_ARCH_BIG_ENDIAN
46 #define R600_BIG_ENDIAN 1
48 #define R600_BIG_ENDIAN 0
51 enum r600_pipe_state_id {
52 R600_PIPE_STATE_BLEND = 0,
53 R600_PIPE_STATE_BLEND_COLOR,
54 R600_PIPE_STATE_CONFIG,
55 R600_PIPE_STATE_SEAMLESS_CUBEMAP,
57 R600_PIPE_STATE_SCISSOR,
58 R600_PIPE_STATE_VIEWPORT,
59 R600_PIPE_STATE_RASTERIZER,
61 R600_PIPE_STATE_FRAMEBUFFER,
63 R600_PIPE_STATE_STENCIL_REF,
64 R600_PIPE_STATE_PS_SHADER,
65 R600_PIPE_STATE_VS_SHADER,
66 R600_PIPE_STATE_CONSTANT,
67 R600_PIPE_STATE_SAMPLER,
68 R600_PIPE_STATE_RESOURCE,
69 R600_PIPE_STATE_POLYGON_OFFSET,
70 R600_PIPE_STATE_FETCH_SHADER,
74 struct r600_pipe_fences {
75 struct r600_resource *bo;
78 /* linked list of preallocated blocks */
79 struct list_head blocks;
80 /* linked list of freed fences */
81 struct list_head pool;
86 struct pipe_screen screen;
87 struct radeon_winsys *ws;
89 enum chip_class chip_class;
90 struct radeon_info info;
91 struct r600_tiling_info tiling_info;
92 struct util_slab_mempool pool_buffers;
93 struct r600_pipe_fences fences;
95 unsigned num_contexts;
97 /* for thread-safe write accessing to num_contexts */
98 pipe_mutex mutex_num_contexts;
101 struct r600_pipe_sampler_view {
102 struct pipe_sampler_view base;
103 struct r600_pipe_resource_state state;
106 struct r600_pipe_rasterizer {
107 struct r600_pipe_state rstate;
110 unsigned sprite_coord_enable;
111 unsigned clip_plane_enable;
112 unsigned pa_sc_line_stipple;
117 struct r600_pipe_blend {
118 struct r600_pipe_state rstate;
119 unsigned cb_target_mask;
120 unsigned cb_color_control;
123 struct r600_pipe_dsa {
124 struct r600_pipe_state rstate;
130 struct r600_vertex_element
133 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
134 struct u_vbuf_elements *vmgr_elements;
135 struct r600_resource *fetch_shader;
137 struct r600_pipe_state rstate;
138 /* if offset is to big for fetch instructio we need to alterate
139 * offset of vertex buffer, record here the offset need to add
141 unsigned vbuffer_need_offset;
142 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS];
145 struct r600_pipe_shader {
146 struct r600_shader shader;
147 struct r600_pipe_state rstate;
148 struct r600_resource *bo;
149 struct r600_resource *bo_fetch;
150 struct r600_vertex_element vertex_elements;
151 struct tgsi_token *tokens;
152 unsigned sprite_coord_enable;
154 struct pipe_stream_output_info so;
157 struct r600_pipe_sampler_state {
158 struct r600_pipe_state rstate;
159 boolean seamless_cube_map;
162 /* needed for blitter save */
163 #define NUM_TEX_UNITS 16
165 struct r600_textures_info {
166 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
167 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS];
171 bool is_array_sampler[NUM_TEX_UNITS];
175 struct pipe_reference reference;
176 unsigned index; /* in the shared bo */
177 struct list_head head;
180 #define FENCE_BLOCK_SIZE 16
182 struct r600_fence_block {
183 struct r600_fence fences[FENCE_BLOCK_SIZE];
184 struct list_head head;
187 #define R600_CONSTANT_ARRAY_SIZE 256
188 #define R600_RESOURCE_ARRAY_SIZE 160
190 struct r600_stencil_ref
197 struct r600_pipe_context {
198 struct pipe_context context;
199 struct blitter_context *blitter;
200 enum radeon_family family;
201 enum chip_class chip_class;
202 unsigned r6xx_num_clause_temp_gprs;
203 void *custom_dsa_flush;
204 struct r600_screen *screen;
205 struct radeon_winsys *ws;
206 struct r600_pipe_state *states[R600_PIPE_NSTATES];
207 struct r600_context ctx;
208 struct r600_vertex_element *vertex_elements;
209 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
210 struct pipe_framebuffer_state framebuffer;
211 unsigned cb_target_mask;
212 unsigned cb_color_control;
213 unsigned pa_sc_line_stipple;
214 /* for saving when using blitter */
215 struct pipe_stencil_ref stencil_ref;
216 struct pipe_viewport_state viewport;
217 struct pipe_clip_state clip;
218 struct r600_pipe_state config;
219 struct r600_pipe_shader *ps_shader;
220 struct r600_pipe_shader *vs_shader;
221 struct r600_pipe_state vs_const_buffer;
222 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
223 struct r600_pipe_state ps_const_buffer;
224 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
225 struct r600_pipe_rasterizer *rasterizer;
226 struct r600_pipe_state vgt;
227 struct r600_pipe_state spi;
228 struct pipe_query *current_render_cond;
229 unsigned current_render_cond_mode;
230 struct pipe_query *saved_render_cond;
231 unsigned saved_render_cond_mode;
232 /* shader information */
234 unsigned user_clip_plane_enable;
235 unsigned clip_dist_enable;
236 unsigned sprite_coord_enable;
237 boolean export_16bpc;
239 boolean alpha_ref_dirty;
241 struct r600_textures_info vs_samplers;
242 struct r600_textures_info ps_samplers;
244 struct u_vbuf *vbuf_mgr;
245 struct util_slab_mempool pool_transfers;
246 boolean have_depth_texture, have_depth_fb;
248 unsigned default_ps_gprs, default_vs_gprs;
251 /* evergreen_state.c */
252 void evergreen_init_state_functions(struct r600_pipe_context *rctx);
253 void evergreen_init_config(struct r600_pipe_context *rctx);
254 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
255 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
256 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
257 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx);
258 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx);
259 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
260 struct r600_pipe_resource_state *rstate);
261 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
262 struct r600_pipe_resource_state *rstate,
263 struct r600_resource *rbuffer,
264 unsigned offset, unsigned stride,
265 enum radeon_bo_usage usage);
266 boolean evergreen_is_format_supported(struct pipe_screen *screen,
267 enum pipe_format format,
268 enum pipe_texture_target target,
269 unsigned sample_count,
273 void r600_init_blit_functions(struct r600_pipe_context *rctx);
274 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
275 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
276 void r600_flush_depth_textures(struct r600_pipe_context *rctx);
279 bool r600_init_resource(struct r600_screen *rscreen,
280 struct r600_resource *res,
281 unsigned size, unsigned alignment,
282 unsigned bind, unsigned usage);
283 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
284 const struct pipe_resource *templ);
285 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
286 void *ptr, unsigned bytes,
288 void r600_upload_index_buffer(struct r600_pipe_context *rctx,
289 struct pipe_index_buffer *ib, unsigned count);
293 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
297 void r600_init_query_functions(struct r600_pipe_context *rctx);
299 /* r600_resource.c */
300 void r600_init_context_resource_functions(struct r600_pipe_context *r600);
303 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
304 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
305 int r600_find_vs_semantic_index(struct r600_shader *vs,
306 struct r600_shader *ps, int id);
309 void r600_update_sampler_states(struct r600_pipe_context *rctx);
310 void r600_init_state_functions(struct r600_pipe_context *rctx);
311 void r600_init_config(struct r600_pipe_context *rctx);
312 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
313 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
314 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
315 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx);
316 void r600_polygon_offset_update(struct r600_pipe_context *rctx);
317 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
318 struct r600_pipe_resource_state *rstate);
319 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
320 struct r600_resource *rbuffer,
321 unsigned offset, unsigned stride,
322 enum radeon_bo_usage usage);
323 void r600_adjust_gprs(struct r600_pipe_context *rctx);
324 boolean r600_is_format_supported(struct pipe_screen *screen,
325 enum pipe_format format,
326 enum pipe_texture_target target,
327 unsigned sample_count,
331 void r600_init_screen_texture_functions(struct pipe_screen *screen);
332 void r600_init_surface_functions(struct r600_pipe_context *r600);
333 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
334 const unsigned char *swizzle_view,
335 uint32_t *word4_p, uint32_t *yuv_format_p);
336 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
337 unsigned level, unsigned layer);
339 /* r600_translate.c */
340 void r600_translate_index_buffer(struct r600_pipe_context *r600,
341 struct pipe_index_buffer *ib,
344 /* r600_state_common.c */
345 void r600_set_index_buffer(struct pipe_context *ctx,
346 const struct pipe_index_buffer *ib);
347 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
348 const struct pipe_vertex_buffer *buffers);
349 void *r600_create_vertex_elements(struct pipe_context *ctx,
351 const struct pipe_vertex_element *elements);
352 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
353 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
354 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
355 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
356 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
357 void r600_sampler_view_destroy(struct pipe_context *ctx,
358 struct pipe_sampler_view *state);
359 void r600_delete_state(struct pipe_context *ctx, void *state);
360 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
361 void *r600_create_shader_state(struct pipe_context *ctx,
362 const struct pipe_shader_state *state);
363 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
364 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
365 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
366 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
367 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
368 struct pipe_resource *buffer);
369 struct pipe_stream_output_target *
370 r600_create_so_target(struct pipe_context *ctx,
371 struct pipe_resource *buffer,
372 unsigned buffer_offset,
373 unsigned buffer_size);
374 void r600_so_target_destroy(struct pipe_context *ctx,
375 struct pipe_stream_output_target *target);
376 void r600_set_so_targets(struct pipe_context *ctx,
377 unsigned num_targets,
378 struct pipe_stream_output_target **targets,
379 unsigned append_bitmask);
380 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
381 const struct pipe_stencil_ref *state);
382 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
387 static INLINE u32 S_FIXED(float value, u32 frac_bits)
389 return value * (1 << frac_bits);
391 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
393 static inline unsigned r600_tex_aniso_filter(unsigned filter)
395 if (filter <= 1) return 0;
396 if (filter <= 2) return 1;
397 if (filter <= 4) return 2;
398 if (filter <= 8) return 3;
402 /* 12.4 fixed-point */
403 static INLINE unsigned r600_pack_float_12p4(float x)
406 x >= 4096 ? 0xffff : x * 16;