src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "util/u_blitter.h"
  30 #include "util/u_slab.h"
  31 #include "r600.h"
  32 #include "r600_llvm.h"
  33 #include "r600_public.h"
  34 #include "r600_shader.h"
  35 #include "r600_resource.h"
  36 #include "evergreen_compute.h"
  37
  38 #define R600_MAX_CONST_BUFFERS 2
  39 #define R600_MAX_CONST_BUFFER_SIZE 4096
  40
  41 #ifdef PIPE_ARCH_BIG_ENDIAN
  42 #define R600_BIG_ENDIAN 1
  43 #else
  44 #define R600_BIG_ENDIAN 0
  45 #endif
  46
  47 enum r600_atom_flags {
  48         /* When set, atoms are added at the beginning of the dirty list
  49          * instead of the end. */
  50         EMIT_EARLY = (1 << 0)
  51 };
  52
  53 /* This encapsulates a state or an operation which can emitted into the GPU
  54  * command stream. It's not limited to states only, it can be used for anything
  55  * that wants to write commands into the CS (e.g. cache flushes). */
  56 struct r600_atom {
  57         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  58
  59         unsigned                num_dw;
  60         enum r600_atom_flags    flags;
  61         bool                    dirty;
  62
  63         struct list_head        head;
  64 };
  65
  66 /* This is an atom containing GPU commands that never change.
  67  * This is supposed to be copied directly into the CS. */
  68 struct r600_command_buffer {
  69         struct r600_atom atom;
  70         uint32_t *buf;
  71         unsigned max_num_dw;
  72         unsigned pkt_flags;
  73 };
  74
  75 struct r600_surface_sync_cmd {
  76         struct r600_atom atom;
  77         unsigned flush_flags; /* CP_COHER_CNTL */
  78 };
  79
  80 struct r600_db_misc_state {
  81         struct r600_atom atom;
  82         bool occlusion_query_enabled;
  83         bool flush_depthstencil_through_cb;
  84         bool copy_depth, copy_stencil;
  85         unsigned copy_sample;
  86 };
  87
  88 struct r600_cb_misc_state {
  89         struct r600_atom atom;
  90         unsigned cb_color_control; /* this comes from blend state */
  91         unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
  92         unsigned nr_cbufs;
  93         unsigned nr_ps_color_outputs;
  94         bool multiwrite;
  95         bool dual_src_blend;
  96 };
  97
  98 struct r600_alphatest_state {
  99         struct r600_atom atom;
 100         unsigned sx_alpha_test_control; /* this comes from dsa state */
 101         unsigned sx_alpha_ref; /* this comes from dsa state */
 102         bool bypass;
 103         bool cb0_export_16bpc; /* from set_framebuffer_state */
 104 };
 105
 106 struct r600_cs_shader_state {
 107         struct r600_atom atom;
 108         struct r600_pipe_compute *shader;
 109 };
 110
 111 struct r600_sample_mask {
 112         struct r600_atom atom;
 113         uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
 114 };
 115
 116 enum r600_pipe_state_id {
 117         R600_PIPE_STATE_BLEND = 0,
 118         R600_PIPE_STATE_BLEND_COLOR,
 119         R600_PIPE_STATE_CONFIG,
 120         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
 121         R600_PIPE_STATE_CLIP,
 122         R600_PIPE_STATE_SCISSOR,
 123         R600_PIPE_STATE_VIEWPORT,
 124         R600_PIPE_STATE_RASTERIZER,
 125         R600_PIPE_STATE_VGT,
 126         R600_PIPE_STATE_FRAMEBUFFER,
 127         R600_PIPE_STATE_DSA,
 128         R600_PIPE_STATE_STENCIL_REF,
 129         R600_PIPE_STATE_PS_SHADER,
 130         R600_PIPE_STATE_VS_SHADER,
 131         R600_PIPE_STATE_CONSTANT,
 132         R600_PIPE_STATE_SAMPLER,
 133         R600_PIPE_STATE_RESOURCE,
 134         R600_PIPE_STATE_POLYGON_OFFSET,
 135         R600_PIPE_STATE_FETCH_SHADER,
 136         R600_PIPE_STATE_SPI,
 137         R600_PIPE_NSTATES
 138 };
 139
 140 struct compute_memory_pool;
 141 void compute_memory_pool_delete(struct compute_memory_pool* pool);
 142 struct compute_memory_pool* compute_memory_pool_new(
 143         struct r600_screen *rscreen);
 144
 145 struct r600_pipe_fences {
 146         struct r600_resource            *bo;
 147         unsigned                        *data;
 148         unsigned                        next_index;
 149         /* linked list of preallocated blocks */
 150         struct list_head                blocks;
 151         /* linked list of freed fences */
 152         struct list_head                pool;
 153         pipe_mutex                      mutex;
 154 };
 155
 156 struct r600_screen {
 157         struct pipe_screen              screen;
 158         struct radeon_winsys            *ws;
 159         unsigned                        family;
 160         enum chip_class                 chip_class;
 161         struct radeon_info              info;
 162         bool                            has_streamout;
 163         struct r600_tiling_info         tiling_info;
 164         struct r600_pipe_fences         fences;
 165
 166         /*for compute global memory binding, we allocate stuff here, instead of
 167          * buffers.
 168          * XXX: Not sure if this is the best place for global_pool.  Also,
 169          * it's not thread safe, so it won't work with multiple contexts. */
 170         struct compute_memory_pool *global_pool;
 171 };
 172
 173 struct r600_pipe_sampler_view {
 174         struct pipe_sampler_view        base;
 175         struct r600_resource            *tex_resource;
 176         uint32_t                        tex_resource_words[8];
 177 };
 178
 179 struct r600_pipe_rasterizer {
 180         struct r600_pipe_state          rstate;
 181         boolean                         flatshade;
 182         boolean                         two_side;
 183         unsigned                        sprite_coord_enable;
 184         unsigned                        clip_plane_enable;
 185         unsigned                        pa_sc_line_stipple;
 186         unsigned                        pa_cl_clip_cntl;
 187         float                           offset_units;
 188         float                           offset_scale;
 189         bool                            scissor_enable;
 190         bool                            multisample_enable;
 191 };
 192
 193 struct r600_pipe_blend {
 194         struct r600_pipe_state          rstate;
 195         unsigned                        cb_target_mask;
 196         unsigned                        cb_color_control;
 197         bool                            dual_src_blend;
 198         bool                            alpha_to_one;
 199 };
 200
 201 struct r600_pipe_dsa {
 202         struct r600_pipe_state          rstate;
 203         unsigned                        alpha_ref;
 204         ubyte                           valuemask[2];
 205         ubyte                           writemask[2];
 206         unsigned                        sx_alpha_test_control;
 207 };
 208
 209 struct r600_vertex_element
 210 {
 211         unsigned                        count;
 212         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 213         struct r600_resource            *fetch_shader;
 214         unsigned                        fs_size;
 215         struct r600_pipe_state          rstate;
 216 };
 217
 218 struct r600_pipe_shader;
 219
 220 struct r600_pipe_shader_selector {
 221         struct r600_pipe_shader *current;
 222
 223         struct tgsi_token       *tokens;
 224         struct pipe_stream_output_info  so;
 225
 226         unsigned        num_shaders;
 227
 228         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 229         unsigned        type;
 230
 231         unsigned        nr_ps_max_color_exports;
 232 };
 233
 234 struct r600_pipe_shader {
 235         struct r600_pipe_shader_selector *selector;
 236         struct r600_pipe_shader *next_variant;
 237         struct r600_shader              shader;
 238         struct r600_pipe_state          rstate;
 239         struct r600_resource            *bo;
 240         struct r600_resource            *bo_fetch;
 241         struct r600_vertex_element      vertex_elements;
 242         unsigned        sprite_coord_enable;
 243         unsigned        flatshade;
 244         unsigned        pa_cl_vs_out_cntl;
 245         unsigned        nr_ps_color_outputs;
 246         unsigned        key;
 247         unsigned                db_shader_control;
 248         unsigned                ps_depth_export;
 249 };
 250
 251 struct r600_pipe_sampler_state {
 252         uint32_t                        tex_sampler_words[3];
 253         uint32_t                        border_color[4];
 254         bool                            border_color_use;
 255         bool                            seamless_cube_map;
 256 };
 257
 258 /* needed for blitter save */
 259 #define NUM_TEX_UNITS 16
 260
 261 struct r600_seamless_cube_map {
 262         struct r600_atom                atom;
 263         bool                            enabled;
 264 };
 265
 266 struct r600_samplerview_state {
 267         struct r600_atom                atom;
 268         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 269         uint32_t                        enabled_mask;
 270         uint32_t                        dirty_mask;
 271         uint32_t                        compressed_depthtex_mask; /* which textures are depth */
 272         uint32_t                        compressed_colortex_mask;
 273 };
 274
 275 struct r600_textures_info {
 276         struct r600_samplerview_state   views;
 277         struct r600_atom                atom_sampler;
 278         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 279         unsigned                        n_samplers;
 280         bool                            is_array_sampler[NUM_TEX_UNITS];
 281 };
 282
 283 struct r600_fence {
 284         struct pipe_reference           reference;
 285         unsigned                        index; /* in the shared bo */
 286         struct r600_resource            *sleep_bo;
 287         struct list_head                head;
 288 };
 289
 290 #define FENCE_BLOCK_SIZE 16
 291
 292 struct r600_fence_block {
 293         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 294         struct list_head                head;
 295 };
 296
 297 #define R600_CONSTANT_ARRAY_SIZE 256
 298 #define R600_RESOURCE_ARRAY_SIZE 160
 299
 300 struct r600_stencil_ref
 301 {
 302         ubyte ref_value[2];
 303         ubyte valuemask[2];
 304         ubyte writemask[2];
 305 };
 306
 307 struct r600_constbuf_state
 308 {
 309         struct r600_atom                atom;
 310         struct pipe_constant_buffer     cb[PIPE_MAX_CONSTANT_BUFFERS];
 311         uint32_t                        enabled_mask;
 312         uint32_t                        dirty_mask;
 313 };
 314
 315 struct r600_vertexbuf_state
 316 {
 317         struct r600_atom                atom;
 318         struct pipe_vertex_buffer       vb[PIPE_MAX_ATTRIBS];
 319         uint32_t                        enabled_mask; /* non-NULL buffers */
 320         uint32_t                        dirty_mask;
 321 };
 322
 323 struct r600_context {
 324         struct pipe_context             context;
 325         struct blitter_context          *blitter;
 326         enum radeon_family              family;
 327         enum chip_class                 chip_class;
 328         boolean                         has_vertex_cache;
 329         unsigned                        r6xx_num_clause_temp_gprs;
 330         void                            *custom_dsa_flush;
 331         void                            *custom_blend_resolve;
 332         void                            *custom_blend_decompress;
 333
 334         struct r600_screen              *screen;
 335         struct radeon_winsys            *ws;
 336         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 337         struct r600_vertex_element      *vertex_elements;
 338         struct pipe_framebuffer_state   framebuffer;
 339         unsigned                        compressed_cb_mask;
 340         unsigned                        compute_cb_target_mask;
 341         unsigned                        db_shader_control;
 342         unsigned                        pa_sc_line_stipple;
 343         unsigned                        pa_cl_clip_cntl;
 344         /* for saving when using blitter */
 345         struct pipe_stencil_ref         stencil_ref;
 346         struct pipe_viewport_state      viewport;
 347         struct pipe_clip_state          clip;
 348         struct r600_pipe_shader_selector        *ps_shader;
 349         struct r600_pipe_shader_selector        *vs_shader;
 350         struct r600_pipe_rasterizer     *rasterizer;
 351         struct r600_pipe_state          vgt;
 352         struct r600_pipe_state          spi;
 353         struct pipe_query               *current_render_cond;
 354         unsigned                        current_render_cond_mode;
 355         struct pipe_query               *saved_render_cond;
 356         unsigned                        saved_render_cond_mode;
 357         /* shader information */
 358         boolean                         two_side;
 359         boolean                         spi_dirty;
 360         unsigned                        sprite_coord_enable;
 361         boolean                         flatshade;
 362         boolean                         export_16bpc;
 363         unsigned                        nr_cbufs;
 364         bool                            alpha_to_one;
 365         bool                            multisample_enable;
 366         bool                            cb0_is_integer;
 367
 368         struct u_upload_mgr             *uploader;
 369         struct util_slab_mempool        pool_transfers;
 370
 371         unsigned default_ps_gprs, default_vs_gprs;
 372
 373         /* States based on r600_atom. */
 374         struct list_head                dirty_states;
 375         struct r600_command_buffer      start_cs_cmd; /* invariant state mostly */
 376         /** Compute specific registers initializations.  The start_cs_cmd atom
 377          *  must be emitted before start_compute_cs_cmd. */
 378         struct r600_command_buffer      start_compute_cs_cmd;
 379         struct r600_surface_sync_cmd    surface_sync_cmd;
 380         struct r600_atom                r6xx_flush_and_inv_cmd;
 381         struct r600_alphatest_state     alphatest_state;
 382         struct r600_cb_misc_state       cb_misc_state;
 383         struct r600_db_misc_state       db_misc_state;
 384         /** Vertex buffers for fetch shaders */
 385         struct r600_vertexbuf_state     vertex_buffer_state;
 386         /** Vertex buffers for compute shaders */
 387         struct r600_vertexbuf_state     cs_vertex_buffer_state;
 388         struct r600_constbuf_state      vs_constbuf_state;
 389         struct r600_constbuf_state      ps_constbuf_state;
 390         struct r600_textures_info       vs_samplers;
 391         struct r600_textures_info       ps_samplers;
 392         struct r600_seamless_cube_map   seamless_cube_map;
 393         struct r600_cs_shader_state     cs_shader_state;
 394         struct r600_sample_mask         sample_mask;
 395
 396         /* current external blend state (from state tracker) */
 397         struct r600_pipe_blend          *blend;
 398         /* state with disabled blending - used internally with blend_override */
 399         struct r600_pipe_blend          *no_blend;
 400
 401         /* 1 - override current blend state with no_blend, 0 - use external state */
 402         unsigned        blend_override;
 403
 404         struct radeon_winsys_cs *cs;
 405
 406         struct r600_range       *range;
 407         unsigned                nblocks;
 408         struct r600_block       **blocks;
 409         struct list_head        dirty;
 410         struct list_head        enable_list;
 411         unsigned                pm4_dirty_cdwords;
 412         unsigned                ctx_pm4_ndwords;
 413
 414         /* The list of active queries. Only one query of each type can be active. */
 415         int                     num_occlusion_queries;
 416
 417         /* Manage queries in two separate groups:
 418          * The timer ones and the others (streamout, occlusion).
 419          *
 420          * We do this because we should only suspend non-timer queries for u_blitter,
 421          * and later if the non-timer queries are suspended, the context flush should
 422          * only suspend and resume the timer queries. */
 423         struct list_head        active_timer_queries;
 424         unsigned                num_cs_dw_timer_queries_suspend;
 425         struct list_head        active_nontimer_queries;
 426         unsigned                num_cs_dw_nontimer_queries_suspend;
 427
 428         unsigned                num_cs_dw_streamout_end;
 429
 430         unsigned                backend_mask;
 431         unsigned                max_db; /* for OQ */
 432         unsigned                flags;
 433         boolean                 predicate_drawing;
 434
 435         unsigned                num_so_targets;
 436         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 437         boolean                 streamout_start;
 438         unsigned                streamout_append_bitmask;
 439
 440         /* There is no scissor enable bit on r6xx, so we must use a workaround.
 441          * These track the current scissor state. */
 442         bool                    scissor_enable;
 443         struct pipe_scissor_state scissor_state;
 444
 445         /* With rasterizer discard, there doesn't have to be a pixel shader.
 446          * In that case, we bind this one: */
 447         void                    *dummy_pixel_shader;
 448
 449         boolean                 dual_src_blend;
 450
 451         /* Index buffer. */
 452         struct pipe_index_buffer index_buffer;
 453 };
 454
 455 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 456 {
 457         atom->emit(rctx, atom);
 458         atom->dirty = false;
 459         if (atom->head.next && atom->head.prev)
 460                 LIST_DELINIT(&atom->head);
 461 }
 462
 463 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 464 {
 465         if (!state->dirty) {
 466                 if (state->flags & EMIT_EARLY) {
 467                         LIST_ADD(&state->head, &rctx->dirty_states);
 468                 } else {
 469                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 470                 }
 471                 state->dirty = true;
 472         }
 473 }
 474
 475 /* evergreen_state.c */
 476 void evergreen_init_common_regs(struct r600_command_buffer *cb,
 477                                 enum chip_class ctx_chip_class,
 478                                 enum radeon_family ctx_family,
 479                                 int ctx_drm_minor);
 480
 481 void evergreen_init_state_functions(struct r600_context *rctx);
 482 void evergreen_init_atom_start_cs(struct r600_context *rctx);
 483 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 484 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 485 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 486 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 487 void *evergreen_create_resolve_blend(struct r600_context *rctx);
 488 void *evergreen_create_decompress_blend(struct r600_context *rctx);
 489 void evergreen_polygon_offset_update(struct r600_context *rctx);
 490 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 491                                       enum pipe_format format,
 492                                       enum pipe_texture_target target,
 493                                       unsigned sample_count,
 494                                       unsigned usage);
 495 void evergreen_init_color_surface(struct r600_context *rctx,
 496                                   struct r600_surface *surf);
 497 void evergreen_update_dual_export_state(struct r600_context * rctx);
 498
 499 /* r600_blit.c */
 500 void r600_copy_buffer(struct pipe_context *ctx, struct
 501                       pipe_resource *dst, unsigned dstx,
 502                       struct pipe_resource *src, const struct pipe_box *src_box);
 503 void r600_init_blit_functions(struct r600_context *rctx);
 504 void r600_blit_decompress_depth(struct pipe_context *ctx,
 505                 struct r600_texture *texture,
 506                 struct r600_texture *staging,
 507                 unsigned first_level, unsigned last_level,
 508                 unsigned first_layer, unsigned last_layer,
 509                 unsigned first_sample, unsigned last_sample);
 510 void r600_decompress_depth_textures(struct r600_context *rctx,
 511                                     struct r600_samplerview_state *textures);
 512 void r600_decompress_color_textures(struct r600_context *rctx,
 513                                     struct r600_samplerview_state *textures);
 514
 515 /* r600_buffer.c */
 516 bool r600_init_resource(struct r600_screen *rscreen,
 517                         struct r600_resource *res,
 518                         unsigned size, unsigned alignment,
 519                         unsigned bind, unsigned usage);
 520 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 521                                          const struct pipe_resource *templ);
 522
 523 /* r600_pipe.c */
 524 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 525                 unsigned flags);
 526
 527 /* r600_query.c */
 528 void r600_init_query_functions(struct r600_context *rctx);
 529 void r600_suspend_nontimer_queries(struct r600_context *ctx);
 530 void r600_resume_nontimer_queries(struct r600_context *ctx);
 531 void r600_suspend_timer_queries(struct r600_context *ctx);
 532 void r600_resume_timer_queries(struct r600_context *ctx);
 533
 534 /* r600_resource.c */
 535 void r600_init_context_resource_functions(struct r600_context *r600);
 536
 537 /* r600_shader.c */
 538 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 539 #ifdef HAVE_OPENCL
 540 int r600_compute_shader_create(struct pipe_context * ctx,
 541         LLVMModuleRef mod,  struct r600_bytecode * bytecode);
 542 #endif
 543 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 544
 545 /* r600_state.c */
 546 void r600_set_scissor_state(struct r600_context *rctx,
 547                             const struct pipe_scissor_state *state);
 548 void r600_init_state_functions(struct r600_context *rctx);
 549 void r600_init_atom_start_cs(struct r600_context *rctx);
 550 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 551 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 552 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 553 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 554 void *r600_create_resolve_blend(struct r600_context *rctx);
 555 void *r600_create_decompress_blend(struct r600_context *rctx);
 556 void r600_polygon_offset_update(struct r600_context *rctx);
 557 void r600_adjust_gprs(struct r600_context *rctx);
 558 boolean r600_is_format_supported(struct pipe_screen *screen,
 559                                  enum pipe_format format,
 560                                  enum pipe_texture_target target,
 561                                  unsigned sample_count,
 562                                  unsigned usage);
 563 void r600_update_dual_export_state(struct r600_context * rctx);
 564
 565 /* r600_texture.c */
 566 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 567 void r600_init_surface_functions(struct r600_context *r600);
 568 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 569                                   const unsigned char *swizzle_view,
 570                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 571 unsigned r600_texture_get_offset(struct r600_texture *rtex,
 572                                         unsigned level, unsigned layer);
 573
 574 /* r600_translate.c */
 575 void r600_translate_index_buffer(struct r600_context *r600,
 576                                  struct pipe_index_buffer *ib,
 577                                  unsigned count);
 578
 579 /* r600_state_common.c */
 580 void r600_init_atom(struct r600_atom *atom,
 581                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
 582                     unsigned num_dw, enum r600_atom_flags flags);
 583 void r600_init_common_atoms(struct r600_context *rctx);
 584 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 585 void r600_texture_barrier(struct pipe_context *ctx);
 586 void r600_set_index_buffer(struct pipe_context *ctx,
 587                            const struct pipe_index_buffer *ib);
 588 void r600_vertex_buffers_dirty(struct r600_context *rctx);
 589 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 590                              const struct pipe_vertex_buffer *input);
 591 void r600_sampler_views_dirty(struct r600_context *rctx,
 592                               struct r600_samplerview_state *state);
 593 void r600_set_sampler_views(struct pipe_context *pipe,
 594                             unsigned shader,
 595                             unsigned start,
 596                             unsigned count,
 597                             struct pipe_sampler_view **views);
 598 void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states);
 599 void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states);
 600 void *r600_create_vertex_elements(struct pipe_context *ctx,
 601                                   unsigned count,
 602                                   const struct pipe_vertex_element *elements);
 603 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 604 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 605 void r600_set_blend_color(struct pipe_context *ctx,
 606                           const struct pipe_blend_color *state);
 607 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 608 void r600_set_max_scissor(struct r600_context *rctx);
 609 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 610 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 611 void r600_sampler_view_destroy(struct pipe_context *ctx,
 612                                struct pipe_sampler_view *state);
 613 void r600_delete_sampler(struct pipe_context *ctx, void *state);
 614 void r600_delete_state(struct pipe_context *ctx, void *state);
 615 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 616 void *r600_create_shader_state_ps(struct pipe_context *ctx,
 617                    const struct pipe_shader_state *state);
 618 void *r600_create_shader_state_vs(struct pipe_context *ctx,
 619                    const struct pipe_shader_state *state);
 620 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 621 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 622 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 623 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 624 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
 625 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 626                               struct pipe_constant_buffer *cb);
 627 struct pipe_stream_output_target *
 628 r600_create_so_target(struct pipe_context *ctx,
 629                       struct pipe_resource *buffer,
 630                       unsigned buffer_offset,
 631                       unsigned buffer_size);
 632 void r600_so_target_destroy(struct pipe_context *ctx,
 633                             struct pipe_stream_output_target *target);
 634 void r600_set_so_targets(struct pipe_context *ctx,
 635                          unsigned num_targets,
 636                          struct pipe_stream_output_target **targets,
 637                          unsigned append_bitmask);
 638 void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask);
 639 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 640                                const struct pipe_stencil_ref *state);
 641 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 642 void r600_draw_rectangle(struct blitter_context *blitter,
 643                          unsigned x1, unsigned y1, unsigned x2, unsigned y2, float depth,
 644                          enum blitter_attrib_type type, const union pipe_color_union *attrib);
 645 uint32_t r600_translate_stencil_op(int s_op);
 646 uint32_t r600_translate_fill(uint32_t func);
 647 unsigned r600_tex_wrap(unsigned wrap);
 648 unsigned r600_tex_filter(unsigned filter);
 649 unsigned r600_tex_mipfilter(unsigned filter);
 650 unsigned r600_tex_compare(unsigned compare);
 651
 652 /*
 653  * Helpers for building command buffers
 654  */
 655
 656 #define PKT3_SET_CONFIG_REG     0x68
 657 #define PKT3_SET_CONTEXT_REG    0x69
 658 #define PKT3_SET_CTL_CONST      0x6F
 659 #define PKT3_SET_LOOP_CONST                    0x6C
 660
 661 #define R600_CONFIG_REG_OFFSET  0x08000
 662 #define R600_CONTEXT_REG_OFFSET 0x28000
 663 #define R600_CTL_CONST_OFFSET   0x3CFF0
 664 #define R600_LOOP_CONST_OFFSET                 0X0003E200
 665 #define EG_LOOP_CONST_OFFSET               0x0003A200
 666
 667 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 668 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 669 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
 670 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 671 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 672
 673 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
 674
 675 /*Evergreen Compute packet3*/
 676 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
 677
 678 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
 679 {
 680         cb->buf[cb->atom.num_dw++] = value;
 681 }
 682
 683 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 684 {
 685         assert(reg < R600_CONTEXT_REG_OFFSET);
 686         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 687         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 688         cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 689 }
 690
 691 /**
 692  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 693  * shaders.
 694  */
 695 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 696 {
 697         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 698         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 699         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
 700         cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 701 }
 702
 703 /**
 704  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 705  * shaders.
 706  */
 707 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 708 {
 709         assert(reg >= R600_CTL_CONST_OFFSET);
 710         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 711         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
 712         cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 713 }
 714
 715 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 716 {
 717         assert(reg >= R600_LOOP_CONST_OFFSET);
 718         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 719         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 720         cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
 721 }
 722
 723 /**
 724  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 725  * shaders.
 726  */
 727 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 728 {
 729         assert(reg >= EG_LOOP_CONST_OFFSET);
 730         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 731         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
 732         cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
 733 }
 734
 735 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 736 {
 737         r600_store_config_reg_seq(cb, reg, 1);
 738         r600_store_value(cb, value);
 739 }
 740
 741 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 742 {
 743         r600_store_context_reg_seq(cb, reg, 1);
 744         r600_store_value(cb, value);
 745 }
 746
 747 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 748 {
 749         r600_store_ctl_const_seq(cb, reg, 1);
 750         r600_store_value(cb, value);
 751 }
 752
 753 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 754 {
 755         r600_store_loop_const_seq(cb, reg, 1);
 756         r600_store_value(cb, value);
 757 }
 758
 759 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 760 {
 761         eg_store_loop_const_seq(cb, reg, 1);
 762         r600_store_value(cb, value);
 763 }
 764
 765 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
 766 void r600_release_command_buffer(struct r600_command_buffer *cb);
 767
 768 /*
 769  * Helpers for emitting state into a command stream directly.
 770  */
 771
 772 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
 773                                              enum radeon_bo_usage usage)
 774 {
 775         assert(usage);
 776         return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
 777 }
 778
 779 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
 780 {
 781         cs->buf[cs->cdw++] = value;
 782 }
 783
 784 static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
 785 {
 786         assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
 787         memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
 788         cs->cdw += num;
 789 }
 790
 791 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 792 {
 793         assert(reg < R600_CONTEXT_REG_OFFSET);
 794         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 795         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 796         cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 797 }
 798
 799 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 800 {
 801         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 802         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 803         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 804         cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 805 }
 806
 807 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 808 {
 809         r600_write_context_reg_seq(cs, reg, num);
 810         /* Set the compute bit on the packet header */
 811         cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
 812 }
 813
 814 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 815 {
 816         assert(reg >= R600_CTL_CONST_OFFSET);
 817         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 818         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 819         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 820 }
 821
 822 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 823 {
 824         r600_write_config_reg_seq(cs, reg, 1);
 825         r600_write_value(cs, value);
 826 }
 827
 828 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 829 {
 830         r600_write_context_reg_seq(cs, reg, 1);
 831         r600_write_value(cs, value);
 832 }
 833
 834 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 835 {
 836         r600_write_compute_context_reg_seq(cs, reg, 1);
 837         r600_write_value(cs, value);
 838 }
 839
 840 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 841 {
 842         r600_write_ctl_const_seq(cs, reg, 1);
 843         r600_write_value(cs, value);
 844 }
 845
 846 /*
 847  * common helpers
 848  */
 849 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 850 {
 851         return value * (1 << frac_bits);
 852 }
 853 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 854
 855 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 856 {
 857         if (filter <= 1)   return 0;
 858         if (filter <= 2)   return 1;
 859         if (filter <= 4)   return 2;
 860         if (filter <= 8)   return 3;
 861          /* else */        return 4;
 862 }
 863
 864 /* 12.4 fixed-point */
 865 static INLINE unsigned r600_pack_float_12p4(float x)
 866 {
 867         return x <= 0    ? 0 :
 868                x >= 4096 ? 0xffff : x * 16;
 869 }
 870
 871 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 872 {
 873         struct r600_screen *rscreen = (struct r600_screen*)screen;
 874         struct r600_resource *rresource = (struct r600_resource*)resource;
 875
 876         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 877 }
 878
 879 #endif