src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30
  31 #include "pipe/p_state.h"
  32 #include "pipe/p_screen.h"
  33 #include "pipe/p_context.h"
  34 #include "util/u_math.h"
  35 #include "util/u_slab.h"
  36 #include "util/u_vbuf.h"
  37 #include "r600.h"
  38 #include "r600_public.h"
  39 #include "r600_shader.h"
  40 #include "r600_resource.h"
  41
  42 #define R600_MAX_CONST_BUFFERS 2
  43 #define R600_MAX_CONST_BUFFER_SIZE 4096
  44
  45 #ifdef PIPE_ARCH_BIG_ENDIAN
  46 #define R600_BIG_ENDIAN 1
  47 #else
  48 #define R600_BIG_ENDIAN 0
  49 #endif
  50
  51 enum r600_atom_flags {
  52         /* When set, atoms are added at the beginning of the dirty list
  53          * instead of the end. */
  54         EMIT_EARLY = (1 << 0)
  55 };
  56
  57 /* This encapsulates a state or an operation which can emitted into the GPU
  58  * command stream. It's not limited to states only, it can be used for anything
  59  * that wants to write commands into the CS (e.g. cache flushes). */
  60 struct r600_atom {
  61         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  62
  63         unsigned                num_dw;
  64         enum r600_atom_flags    flags;
  65         bool                    dirty;
  66
  67         struct list_head        head;
  68 };
  69
  70 /* This is an atom containing GPU commands that never change.
  71  * This is supposed to be copied directly into the CS. */
  72 struct r600_command_buffer {
  73         struct r600_atom atom;
  74         uint32_t *buf;
  75         unsigned max_num_dw;
  76 };
  77
  78 struct r600_atom_surface_sync {
  79         struct r600_atom atom;
  80         unsigned flush_flags; /* CP_COHER_CNTL */
  81 };
  82
  83 enum r600_pipe_state_id {
  84         R600_PIPE_STATE_BLEND = 0,
  85         R600_PIPE_STATE_BLEND_COLOR,
  86         R600_PIPE_STATE_CONFIG,
  87         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  88         R600_PIPE_STATE_CLIP,
  89         R600_PIPE_STATE_SCISSOR,
  90         R600_PIPE_STATE_VIEWPORT,
  91         R600_PIPE_STATE_RASTERIZER,
  92         R600_PIPE_STATE_VGT,
  93         R600_PIPE_STATE_FRAMEBUFFER,
  94         R600_PIPE_STATE_DSA,
  95         R600_PIPE_STATE_STENCIL_REF,
  96         R600_PIPE_STATE_PS_SHADER,
  97         R600_PIPE_STATE_VS_SHADER,
  98         R600_PIPE_STATE_CONSTANT,
  99         R600_PIPE_STATE_SAMPLER,
 100         R600_PIPE_STATE_RESOURCE,
 101         R600_PIPE_STATE_POLYGON_OFFSET,
 102         R600_PIPE_STATE_FETCH_SHADER,
 103         R600_PIPE_NSTATES
 104 };
 105
 106 struct r600_pipe_fences {
 107         struct r600_resource            *bo;
 108         unsigned                        *data;
 109         unsigned                        next_index;
 110         /* linked list of preallocated blocks */
 111         struct list_head                blocks;
 112         /* linked list of freed fences */
 113         struct list_head                pool;
 114         pipe_mutex                      mutex;
 115 };
 116
 117 struct r600_screen {
 118         struct pipe_screen              screen;
 119         struct radeon_winsys            *ws;
 120         unsigned                        family;
 121         enum chip_class                 chip_class;
 122         struct radeon_info              info;
 123         struct r600_tiling_info         tiling_info;
 124         struct util_slab_mempool        pool_buffers;
 125         struct r600_pipe_fences         fences;
 126
 127         unsigned                        num_contexts;
 128         unsigned                        use_surface;
 129
 130         /* for thread-safe write accessing to num_contexts */
 131         pipe_mutex                      mutex_num_contexts;
 132 };
 133
 134 struct r600_pipe_sampler_view {
 135         struct pipe_sampler_view        base;
 136         struct r600_pipe_resource_state         state;
 137 };
 138
 139 struct r600_pipe_rasterizer {
 140         struct r600_pipe_state          rstate;
 141         boolean                         flatshade;
 142         boolean                         two_side;
 143         unsigned                        sprite_coord_enable;
 144         unsigned                        clip_plane_enable;
 145         unsigned                        pa_sc_line_stipple;
 146         unsigned                        pa_cl_clip_cntl;
 147         float                           offset_units;
 148         float                           offset_scale;
 149 };
 150
 151 struct r600_pipe_blend {
 152         struct r600_pipe_state          rstate;
 153         unsigned                        cb_target_mask;
 154         unsigned                        cb_color_control;
 155 };
 156
 157 struct r600_pipe_dsa {
 158         struct r600_pipe_state          rstate;
 159         unsigned                        alpha_ref;
 160         unsigned                        db_render_override;
 161         unsigned                        db_render_control;
 162         ubyte                           valuemask[2];
 163         ubyte                           writemask[2];
 164 };
 165
 166 struct r600_vertex_element
 167 {
 168         unsigned                        count;
 169         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 170         struct u_vbuf_elements          *vmgr_elements;
 171         struct r600_resource            *fetch_shader;
 172         unsigned                        fs_size;
 173         struct r600_pipe_state          rstate;
 174         /* if offset is to big for fetch instructio we need to alterate
 175          * offset of vertex buffer, record here the offset need to add
 176          */
 177         unsigned                        vbuffer_need_offset;
 178         unsigned                        vbuffer_offset[PIPE_MAX_ATTRIBS];
 179 };
 180
 181 struct r600_pipe_shader {
 182         struct r600_shader              shader;
 183         struct r600_pipe_state          rstate;
 184         struct r600_resource            *bo;
 185         struct r600_resource            *bo_fetch;
 186         struct r600_vertex_element      vertex_elements;
 187         struct tgsi_token               *tokens;
 188         unsigned        sprite_coord_enable;
 189         unsigned        flatshade;
 190         unsigned        pa_cl_vs_out_cntl;
 191         struct pipe_stream_output_info  so;
 192 };
 193
 194 struct r600_pipe_sampler_state {
 195         struct r600_pipe_state          rstate;
 196         boolean seamless_cube_map;
 197 };
 198
 199 /* needed for blitter save */
 200 #define NUM_TEX_UNITS 16
 201
 202 struct r600_textures_info {
 203         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 204         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 205         unsigned                        n_views;
 206         unsigned                        n_samplers;
 207         bool                            samplers_dirty;
 208         bool                            is_array_sampler[NUM_TEX_UNITS];
 209 };
 210
 211 struct r600_fence {
 212         struct pipe_reference           reference;
 213         unsigned                        index; /* in the shared bo */
 214         struct r600_resource            *sleep_bo;
 215         struct list_head                head;
 216 };
 217
 218 #define FENCE_BLOCK_SIZE 16
 219
 220 struct r600_fence_block {
 221         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 222         struct list_head                head;
 223 };
 224
 225 #define R600_CONSTANT_ARRAY_SIZE 256
 226 #define R600_RESOURCE_ARRAY_SIZE 160
 227
 228 struct r600_stencil_ref
 229 {
 230         ubyte ref_value[2];
 231         ubyte valuemask[2];
 232         ubyte writemask[2];
 233 };
 234
 235 struct r600_context {
 236         struct pipe_context             context;
 237         struct blitter_context          *blitter;
 238         enum radeon_family              family;
 239         enum chip_class                 chip_class;
 240         unsigned                        r6xx_num_clause_temp_gprs;
 241         void                            *custom_dsa_flush;
 242         struct r600_screen              *screen;
 243         struct radeon_winsys            *ws;
 244         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 245         struct r600_vertex_element      *vertex_elements;
 246         struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
 247         struct pipe_framebuffer_state   framebuffer;
 248         unsigned                        cb_target_mask;
 249         unsigned                        cb_color_control;
 250         unsigned                        pa_sc_line_stipple;
 251         unsigned                        pa_cl_clip_cntl;
 252         /* for saving when using blitter */
 253         struct pipe_stencil_ref         stencil_ref;
 254         struct pipe_viewport_state      viewport;
 255         struct pipe_clip_state          clip;
 256         struct r600_pipe_shader         *ps_shader;
 257         struct r600_pipe_shader         *vs_shader;
 258         struct r600_pipe_state          vs_const_buffer;
 259         struct r600_pipe_resource_state         vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
 260         struct r600_pipe_state          ps_const_buffer;
 261         struct r600_pipe_resource_state         ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
 262         struct r600_pipe_rasterizer     *rasterizer;
 263         struct r600_pipe_state          vgt;
 264         struct r600_pipe_state          spi;
 265         struct pipe_query               *current_render_cond;
 266         unsigned                        current_render_cond_mode;
 267         struct pipe_query               *saved_render_cond;
 268         unsigned                        saved_render_cond_mode;
 269         /* shader information */
 270         boolean                         two_side;
 271         unsigned                        sprite_coord_enable;
 272         boolean                         export_16bpc;
 273         unsigned                        alpha_ref;
 274         boolean                         alpha_ref_dirty;
 275         unsigned                        nr_cbufs;
 276         struct r600_textures_info       vs_samplers;
 277         struct r600_textures_info       ps_samplers;
 278
 279         struct u_vbuf                   *vbuf_mgr;
 280         struct util_slab_mempool        pool_transfers;
 281         boolean                         have_depth_texture, have_depth_fb;
 282
 283         unsigned default_ps_gprs, default_vs_gprs;
 284
 285         /* States based on r600_state. */
 286         struct list_head                dirty_states;
 287         struct r600_command_buffer      atom_start_cs; /* invariant state mostly */
 288         struct r600_atom_surface_sync   atom_surface_sync;
 289         struct r600_atom                atom_r6xx_flush_and_inv;
 290
 291         /* Below are variables from the old r600_context.
 292          */
 293         struct radeon_winsys_cs *cs;
 294
 295         struct r600_range       *range;
 296         unsigned                nblocks;
 297         struct r600_block       **blocks;
 298         struct list_head        dirty;
 299         struct list_head        resource_dirty;
 300         struct list_head        enable_list;
 301         unsigned                pm4_dirty_cdwords;
 302         unsigned                ctx_pm4_ndwords;
 303
 304         /* The list of active queries. Only one query of each type can be active. */
 305         struct list_head        active_query_list;
 306         unsigned                num_cs_dw_queries_suspend;
 307         unsigned                num_cs_dw_streamout_end;
 308
 309         unsigned                backend_mask;
 310         unsigned                max_db; /* for OQ */
 311         unsigned                flags;
 312         boolean                 predicate_drawing;
 313         struct r600_range       ps_resources;
 314         struct r600_range       vs_resources;
 315         struct r600_range       fs_resources;
 316         int                     num_ps_resources, num_vs_resources, num_fs_resources;
 317
 318         unsigned                num_so_targets;
 319         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 320         boolean                 streamout_start;
 321         unsigned                streamout_append_bitmask;
 322 };
 323
 324 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 325 {
 326         atom->emit(rctx, atom);
 327         atom->dirty = false;
 328         if (atom->head.next && atom->head.prev)
 329                 LIST_DELINIT(&atom->head);
 330 }
 331
 332 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 333 {
 334         if (!state->dirty) {
 335                 if (state->flags & EMIT_EARLY) {
 336                         LIST_ADD(&state->head, &rctx->dirty_states);
 337                 } else {
 338                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 339                 }
 340                 state->dirty = true;
 341         }
 342 }
 343
 344 /* evergreen_state.c */
 345 void evergreen_init_state_functions(struct r600_context *rctx);
 346 void evergreen_init_atom_start_cs(struct r600_context *rctx);
 347 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 348 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 349 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 350 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 351 void evergreen_polygon_offset_update(struct r600_context *rctx);
 352 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
 353                                          struct r600_pipe_resource_state *rstate);
 354 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
 355                                         struct r600_pipe_resource_state *rstate,
 356                                         struct r600_resource *rbuffer,
 357                                         unsigned offset, unsigned stride,
 358                                         enum radeon_bo_usage usage);
 359 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 360                                       enum pipe_format format,
 361                                       enum pipe_texture_target target,
 362                                       unsigned sample_count,
 363                                       unsigned usage);
 364
 365 /* r600_blit.c */
 366 void r600_init_blit_functions(struct r600_context *rctx);
 367 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 368 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 369 void r600_flush_depth_textures(struct r600_context *rctx);
 370
 371 /* r600_buffer.c */
 372 bool r600_init_resource(struct r600_screen *rscreen,
 373                         struct r600_resource *res,
 374                         unsigned size, unsigned alignment,
 375                         unsigned bind, unsigned usage);
 376 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 377                                          const struct pipe_resource *templ);
 378 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
 379                                               void *ptr, unsigned bytes,
 380                                               unsigned bind);
 381 void r600_upload_index_buffer(struct r600_context *rctx,
 382                               struct pipe_index_buffer *ib, unsigned count);
 383
 384
 385 /* r600_pipe.c */
 386 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 387                 unsigned flags);
 388
 389 /* r600_query.c */
 390 void r600_init_query_functions(struct r600_context *rctx);
 391
 392 /* r600_resource.c */
 393 void r600_init_context_resource_functions(struct r600_context *r600);
 394
 395 /* r600_shader.c */
 396 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 397 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 398 int r600_find_vs_semantic_index(struct r600_shader *vs,
 399                                 struct r600_shader *ps, int id);
 400
 401 /* r600_state.c */
 402 void r600_update_sampler_states(struct r600_context *rctx);
 403 void r600_init_state_functions(struct r600_context *rctx);
 404 void r600_init_atom_start_cs(struct r600_context *rctx);
 405 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 406 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 407 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 408 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 409 void r600_polygon_offset_update(struct r600_context *rctx);
 410 void r600_pipe_init_buffer_resource(struct r600_context *rctx,
 411                                     struct r600_pipe_resource_state *rstate);
 412 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
 413                                    struct r600_resource *rbuffer,
 414                                    unsigned offset, unsigned stride,
 415                                    enum radeon_bo_usage usage);
 416 void r600_adjust_gprs(struct r600_context *rctx);
 417 boolean r600_is_format_supported(struct pipe_screen *screen,
 418                                  enum pipe_format format,
 419                                  enum pipe_texture_target target,
 420                                  unsigned sample_count,
 421                                  unsigned usage);
 422
 423 /* r600_texture.c */
 424 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 425 void r600_init_surface_functions(struct r600_context *r600);
 426 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 427                                   const unsigned char *swizzle_view,
 428                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 429 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 430                                         unsigned level, unsigned layer);
 431
 432 /* r600_translate.c */
 433 void r600_translate_index_buffer(struct r600_context *r600,
 434                                  struct pipe_index_buffer *ib,
 435                                  unsigned count);
 436
 437 /* r600_state_common.c */
 438 void r600_init_common_atoms(struct r600_context *rctx);
 439 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 440 void r600_texture_barrier(struct pipe_context *ctx);
 441 void r600_set_index_buffer(struct pipe_context *ctx,
 442                            const struct pipe_index_buffer *ib);
 443 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 444                              const struct pipe_vertex_buffer *buffers);
 445 void *r600_create_vertex_elements(struct pipe_context *ctx,
 446                                   unsigned count,
 447                                   const struct pipe_vertex_element *elements);
 448 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 449 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 450 void r600_set_blend_color(struct pipe_context *ctx,
 451                           const struct pipe_blend_color *state);
 452 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 453 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 454 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 455 void r600_sampler_view_destroy(struct pipe_context *ctx,
 456                                struct pipe_sampler_view *state);
 457 void r600_delete_state(struct pipe_context *ctx, void *state);
 458 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 459 void *r600_create_shader_state(struct pipe_context *ctx,
 460                                const struct pipe_shader_state *state);
 461 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 462 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 463 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 464 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 465 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 466                               struct pipe_resource *buffer);
 467 struct pipe_stream_output_target *
 468 r600_create_so_target(struct pipe_context *ctx,
 469                       struct pipe_resource *buffer,
 470                       unsigned buffer_offset,
 471                       unsigned buffer_size);
 472 void r600_so_target_destroy(struct pipe_context *ctx,
 473                             struct pipe_stream_output_target *target);
 474 void r600_set_so_targets(struct pipe_context *ctx,
 475                          unsigned num_targets,
 476                          struct pipe_stream_output_target **targets,
 477                          unsigned append_bitmask);
 478 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 479                                const struct pipe_stencil_ref *state);
 480 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 481 uint32_t r600_translate_stencil_op(int s_op);
 482 uint32_t r600_translate_fill(uint32_t func);
 483 unsigned r600_tex_wrap(unsigned wrap);
 484 unsigned r600_tex_filter(unsigned filter);
 485 unsigned r600_tex_mipfilter(unsigned filter);
 486 unsigned r600_tex_compare(unsigned compare);
 487
 488 /*
 489  * Helpers for building command buffers
 490  */
 491
 492 #define PKT3_SET_CONFIG_REG     0x68
 493 #define PKT3_SET_CONTEXT_REG    0x69
 494 #define PKT3_SET_CTL_CONST      0x6F
 495
 496 #define R600_CONFIG_REG_OFFSET  0x08000
 497 #define R600_CONTEXT_REG_OFFSET 0x28000
 498 #define R600_CTL_CONST_OFFSET   0x3CFF0
 499
 500 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 501 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 502 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
 503 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 504 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 505
 506 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
 507 {
 508         cb->buf[cb->atom.num_dw++] = value;
 509 }
 510
 511 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 512 {
 513         assert(reg < R600_CONTEXT_REG_OFFSET);
 514         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 515         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 516         cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 517 }
 518
 519 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 520 {
 521         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 522         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 523         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 524         cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 525 }
 526
 527 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 528 {
 529         assert(reg >= R600_CTL_CONST_OFFSET);
 530         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 531         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 532         cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 533 }
 534
 535 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 536 {
 537         r600_store_config_reg_seq(cb, reg, 1);
 538         r600_store_value(cb, value);
 539 }
 540
 541 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 542 {
 543         r600_store_context_reg_seq(cb, reg, 1);
 544         r600_store_value(cb, value);
 545 }
 546
 547 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 548 {
 549         r600_store_ctl_const_seq(cb, reg, 1);
 550         r600_store_value(cb, value);
 551 }
 552
 553 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
 554 void r600_release_command_buffer(struct r600_command_buffer *cb);
 555
 556 /*
 557  * common helpers
 558  */
 559 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 560 {
 561         return value * (1 << frac_bits);
 562 }
 563 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 564
 565 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 566 {
 567         if (filter <= 1)   return 0;
 568         if (filter <= 2)   return 1;
 569         if (filter <= 4)   return 2;
 570         if (filter <= 8)   return 3;
 571          /* else */        return 4;
 572 }
 573
 574 /* 12.4 fixed-point */
 575 static INLINE unsigned r600_pack_float_12p4(float x)
 576 {
 577         return x <= 0    ? 0 :
 578                x >= 4096 ? 0xffff : x * 16;
 579 }
 580
 581 #endif