src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "util/u_slab.h"
  30 #include "r600.h"
  31 #include "r600_llvm.h"
  32 #include "r600_public.h"
  33 #include "r600_shader.h"
  34 #include "r600_resource.h"
  35 #include "evergreen_compute.h"
  36
  37 #define R600_MAX_CONST_BUFFERS 2
  38 #define R600_MAX_CONST_BUFFER_SIZE 4096
  39
  40 #ifdef PIPE_ARCH_BIG_ENDIAN
  41 #define R600_BIG_ENDIAN 1
  42 #else
  43 #define R600_BIG_ENDIAN 0
  44 #endif
  45
  46 enum r600_atom_flags {
  47         /* When set, atoms are added at the beginning of the dirty list
  48          * instead of the end. */
  49         EMIT_EARLY = (1 << 0)
  50 };
  51
  52 /* This encapsulates a state or an operation which can emitted into the GPU
  53  * command stream. It's not limited to states only, it can be used for anything
  54  * that wants to write commands into the CS (e.g. cache flushes). */
  55 struct r600_atom {
  56         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  57
  58         unsigned                num_dw;
  59         enum r600_atom_flags    flags;
  60         bool                    dirty;
  61
  62         struct list_head        head;
  63 };
  64
  65 /* This is an atom containing GPU commands that never change.
  66  * This is supposed to be copied directly into the CS. */
  67 struct r600_command_buffer {
  68         struct r600_atom atom;
  69         uint32_t *buf;
  70         unsigned max_num_dw;
  71 };
  72
  73 struct r600_surface_sync_cmd {
  74         struct r600_atom atom;
  75         unsigned flush_flags; /* CP_COHER_CNTL */
  76 };
  77
  78 struct r600_db_misc_state {
  79         struct r600_atom atom;
  80         bool occlusion_query_enabled;
  81         bool flush_depthstencil_enabled;
  82 };
  83
  84 enum r600_pipe_state_id {
  85         R600_PIPE_STATE_BLEND = 0,
  86         R600_PIPE_STATE_BLEND_COLOR,
  87         R600_PIPE_STATE_CONFIG,
  88         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  89         R600_PIPE_STATE_CLIP,
  90         R600_PIPE_STATE_SCISSOR,
  91         R600_PIPE_STATE_VIEWPORT,
  92         R600_PIPE_STATE_RASTERIZER,
  93         R600_PIPE_STATE_VGT,
  94         R600_PIPE_STATE_FRAMEBUFFER,
  95         R600_PIPE_STATE_DSA,
  96         R600_PIPE_STATE_STENCIL_REF,
  97         R600_PIPE_STATE_PS_SHADER,
  98         R600_PIPE_STATE_VS_SHADER,
  99         R600_PIPE_STATE_CONSTANT,
 100         R600_PIPE_STATE_SAMPLER,
 101         R600_PIPE_STATE_RESOURCE,
 102         R600_PIPE_STATE_POLYGON_OFFSET,
 103         R600_PIPE_STATE_FETCH_SHADER,
 104         R600_PIPE_STATE_SPI,
 105         R600_PIPE_NSTATES
 106 };
 107
 108 struct compute_memory_pool;
 109 void compute_memory_pool_delete(struct compute_memory_pool* pool);
 110 struct compute_memory_pool* compute_memory_pool_new(
 111         int64_t initial_size_in_dw,
 112         struct r600_screen *rscreen);
 113
 114 struct r600_pipe_fences {
 115         struct r600_resource            *bo;
 116         unsigned                        *data;
 117         unsigned                        next_index;
 118         /* linked list of preallocated blocks */
 119         struct list_head                blocks;
 120         /* linked list of freed fences */
 121         struct list_head                pool;
 122         pipe_mutex                      mutex;
 123 };
 124
 125 struct r600_screen {
 126         struct pipe_screen              screen;
 127         struct radeon_winsys            *ws;
 128         unsigned                        family;
 129         enum chip_class                 chip_class;
 130         struct radeon_info              info;
 131         bool                            has_streamout;
 132         struct r600_tiling_info         tiling_info;
 133         struct r600_pipe_fences         fences;
 134
 135         bool                            use_surface_alloc;
 136         int                             glsl_feature_level;
 137
 138         /*for compute global memory binding, we allocate stuff here, instead of
 139          * buffers.
 140          * XXX: Not sure if this is the best place for global_pool.  Also,
 141          * it's not thread safe, so it won't work with multiple contexts. */
 142         struct compute_memory_pool *global_pool;
 143 };
 144
 145 struct r600_pipe_sampler_view {
 146         struct pipe_sampler_view        base;
 147         struct r600_pipe_resource_state         state;
 148 };
 149
 150 struct r600_pipe_rasterizer {
 151         struct r600_pipe_state          rstate;
 152         boolean                         flatshade;
 153         boolean                         two_side;
 154         unsigned                        sprite_coord_enable;
 155         unsigned                        clip_plane_enable;
 156         unsigned                        pa_sc_line_stipple;
 157         unsigned                        pa_cl_clip_cntl;
 158         float                           offset_units;
 159         float                           offset_scale;
 160         bool                            scissor_enable;
 161 };
 162
 163 struct r600_pipe_blend {
 164         struct r600_pipe_state          rstate;
 165         unsigned                        cb_target_mask;
 166         unsigned                        cb_color_control;
 167         bool                            dual_src_blend;
 168 };
 169
 170 struct r600_pipe_dsa {
 171         struct r600_pipe_state          rstate;
 172         unsigned                        alpha_ref;
 173         ubyte                           valuemask[2];
 174         ubyte                           writemask[2];
 175         bool                            is_flush;
 176         unsigned                        sx_alpha_test_control;
 177 };
 178
 179 struct r600_vertex_element
 180 {
 181         unsigned                        count;
 182         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 183         struct r600_resource            *fetch_shader;
 184         unsigned                        fs_size;
 185         struct r600_pipe_state          rstate;
 186 };
 187
 188 struct r600_pipe_shader;
 189
 190 struct r600_pipe_shader_selector {
 191         struct r600_pipe_shader *current;
 192
 193         struct tgsi_token       *tokens;
 194         struct pipe_stream_output_info  so;
 195
 196         unsigned        num_shaders;
 197
 198         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 199         unsigned        type;
 200
 201         unsigned        nr_ps_max_color_exports;
 202 };
 203
 204 struct r600_pipe_shader {
 205         struct r600_pipe_shader_selector *selector;
 206         struct r600_pipe_shader *next_variant;
 207         struct r600_shader              shader;
 208         struct r600_pipe_state          rstate;
 209         struct r600_resource            *bo;
 210         struct r600_resource            *bo_fetch;
 211         struct r600_vertex_element      vertex_elements;
 212         unsigned        sprite_coord_enable;
 213         unsigned        flatshade;
 214         unsigned        pa_cl_vs_out_cntl;
 215         unsigned        ps_cb_shader_mask;
 216         unsigned        key;
 217 };
 218
 219 struct r600_pipe_sampler_state {
 220         struct r600_pipe_state          rstate;
 221         boolean seamless_cube_map;
 222 };
 223
 224 /* needed for blitter save */
 225 #define NUM_TEX_UNITS 16
 226
 227 struct r600_textures_info {
 228         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 229         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 230         unsigned                        n_views;
 231         unsigned                        n_samplers;
 232         bool                            samplers_dirty;
 233         bool                            is_array_sampler[NUM_TEX_UNITS];
 234 };
 235
 236 struct r600_fence {
 237         struct pipe_reference           reference;
 238         unsigned                        index; /* in the shared bo */
 239         struct r600_resource            *sleep_bo;
 240         struct list_head                head;
 241 };
 242
 243 #define FENCE_BLOCK_SIZE 16
 244
 245 struct r600_fence_block {
 246         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 247         struct list_head                head;
 248 };
 249
 250 #define R600_CONSTANT_ARRAY_SIZE 256
 251 #define R600_RESOURCE_ARRAY_SIZE 160
 252
 253 struct r600_stencil_ref
 254 {
 255         ubyte ref_value[2];
 256         ubyte valuemask[2];
 257         ubyte writemask[2];
 258 };
 259
 260 struct r600_constbuf_state
 261 {
 262         struct r600_atom                atom;
 263         struct pipe_constant_buffer     cb[PIPE_MAX_CONSTANT_BUFFERS];
 264         uint32_t                        enabled_mask;
 265         uint32_t                        dirty_mask;
 266 };
 267
 268 struct r600_context {
 269         struct pipe_context             context;
 270         struct blitter_context          *blitter;
 271         enum radeon_family              family;
 272         enum chip_class                 chip_class;
 273         boolean                         has_vertex_cache;
 274         unsigned                        r6xx_num_clause_temp_gprs;
 275         void                            *custom_dsa_flush;
 276         struct r600_screen              *screen;
 277         struct radeon_winsys            *ws;
 278         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 279         struct r600_vertex_element      *vertex_elements;
 280         struct pipe_framebuffer_state   framebuffer;
 281         unsigned                        cb_target_mask;
 282         unsigned                        fb_cb_shader_mask;
 283         unsigned                        sx_alpha_test_control;
 284         unsigned                        cb_shader_mask;
 285         unsigned                        cb_color_control;
 286         unsigned                        pa_sc_line_stipple;
 287         unsigned                        pa_cl_clip_cntl;
 288         /* for saving when using blitter */
 289         struct pipe_stencil_ref         stencil_ref;
 290         struct pipe_viewport_state      viewport;
 291         struct pipe_clip_state          clip;
 292         struct r600_pipe_shader_selector        *ps_shader;
 293         struct r600_pipe_shader_selector        *vs_shader;
 294         struct r600_pipe_compute        *cs_shader;
 295         struct r600_pipe_rasterizer     *rasterizer;
 296         struct r600_pipe_state          vgt;
 297         struct r600_pipe_state          spi;
 298         struct pipe_query               *current_render_cond;
 299         unsigned                        current_render_cond_mode;
 300         struct pipe_query               *saved_render_cond;
 301         unsigned                        saved_render_cond_mode;
 302         /* shader information */
 303         boolean                         two_side;
 304         boolean                         spi_dirty;
 305         unsigned                        sprite_coord_enable;
 306         boolean                         flatshade;
 307         boolean                         export_16bpc;
 308         unsigned                        alpha_ref;
 309         boolean                         alpha_ref_dirty;
 310         unsigned                        nr_cbufs;
 311         struct r600_textures_info       vs_samplers;
 312         struct r600_textures_info       ps_samplers;
 313
 314         struct u_upload_mgr             *uploader;
 315         struct util_slab_mempool        pool_transfers;
 316         boolean                         have_depth_texture, have_depth_fb;
 317
 318         unsigned default_ps_gprs, default_vs_gprs;
 319
 320         /* States based on r600_atom. */
 321         struct list_head                dirty_states;
 322         struct r600_command_buffer      start_cs_cmd; /* invariant state mostly */
 323         struct r600_surface_sync_cmd    surface_sync_cmd;
 324         struct r600_atom                r6xx_flush_and_inv_cmd;
 325         struct r600_db_misc_state       db_misc_state;
 326         struct r600_atom                vertex_buffer_state;
 327         struct r600_constbuf_state      vs_constbuf_state;
 328         struct r600_constbuf_state      ps_constbuf_state;
 329
 330         struct radeon_winsys_cs *cs;
 331
 332         struct r600_range       *range;
 333         unsigned                nblocks;
 334         struct r600_block       **blocks;
 335         struct list_head        dirty;
 336         struct list_head        resource_dirty;
 337         struct list_head        enable_list;
 338         unsigned                pm4_dirty_cdwords;
 339         unsigned                ctx_pm4_ndwords;
 340
 341         /* The list of active queries. Only one query of each type can be active. */
 342         int                     num_occlusion_queries;
 343
 344         /* Manage queries in two separate groups:
 345          * The timer ones and the others (streamout, occlusion).
 346          *
 347          * We do this because we should only suspend non-timer queries for u_blitter,
 348          * and later if the non-timer queries are suspended, the context flush should
 349          * only suspend and resume the timer queries. */
 350         struct list_head        active_timer_queries;
 351         unsigned                num_cs_dw_timer_queries_suspend;
 352         struct list_head        active_nontimer_queries;
 353         unsigned                num_cs_dw_nontimer_queries_suspend;
 354
 355         unsigned                num_cs_dw_streamout_end;
 356
 357         unsigned                backend_mask;
 358         unsigned                max_db; /* for OQ */
 359         unsigned                flags;
 360         boolean                 predicate_drawing;
 361         struct r600_range       ps_resources;
 362         struct r600_range       vs_resources;
 363         int                     num_ps_resources, num_vs_resources;
 364
 365         unsigned                num_so_targets;
 366         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 367         boolean                 streamout_start;
 368         unsigned                streamout_append_bitmask;
 369
 370         /* There is no scissor enable bit on r6xx, so we must use a workaround.
 371          * These track the current scissor state. */
 372         bool                    scissor_enable;
 373         struct pipe_scissor_state scissor_state;
 374
 375         /* With rasterizer discard, there doesn't have to be a pixel shader.
 376          * In that case, we bind this one: */
 377         void                    *dummy_pixel_shader;
 378
 379         boolean                 dual_src_blend;
 380
 381         /* Vertex and index buffers. */
 382         bool                    vertex_buffers_dirty;
 383         struct pipe_index_buffer index_buffer;
 384         struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 385         unsigned                nr_vertex_buffers;
 386 };
 387
 388 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 389 {
 390         atom->emit(rctx, atom);
 391         atom->dirty = false;
 392         if (atom->head.next && atom->head.prev)
 393                 LIST_DELINIT(&atom->head);
 394 }
 395
 396 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 397 {
 398         if (!state->dirty) {
 399                 if (state->flags & EMIT_EARLY) {
 400                         LIST_ADD(&state->head, &rctx->dirty_states);
 401                 } else {
 402                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 403                 }
 404                 state->dirty = true;
 405         }
 406 }
 407
 408 /* evergreen_state.c */
 409 void evergreen_init_state_functions(struct r600_context *rctx);
 410 void evergreen_init_atom_start_cs(struct r600_context *rctx);
 411 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 412 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 413 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 414 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 415 void evergreen_polygon_offset_update(struct r600_context *rctx);
 416 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 417                                       enum pipe_format format,
 418                                       enum pipe_texture_target target,
 419                                       unsigned sample_count,
 420                                       unsigned usage);
 421
 422 /* r600_blit.c */
 423 void r600_init_blit_functions(struct r600_context *rctx);
 424 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 425 void r600_flush_depth_textures(struct r600_context *rctx);
 426
 427 /* r600_buffer.c */
 428 bool r600_init_resource(struct r600_screen *rscreen,
 429                         struct r600_resource *res,
 430                         unsigned size, unsigned alignment,
 431                         unsigned bind, unsigned usage);
 432 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 433                                          const struct pipe_resource *templ);
 434
 435 /* r600_pipe.c */
 436 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 437                 unsigned flags);
 438
 439 /* r600_query.c */
 440 void r600_init_query_functions(struct r600_context *rctx);
 441 void r600_suspend_nontimer_queries(struct r600_context *ctx);
 442 void r600_resume_nontimer_queries(struct r600_context *ctx);
 443 void r600_suspend_timer_queries(struct r600_context *ctx);
 444 void r600_resume_timer_queries(struct r600_context *ctx);
 445
 446 /* r600_resource.c */
 447 void r600_init_context_resource_functions(struct r600_context *r600);
 448
 449 /* r600_shader.c */
 450 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 451 #ifdef HAVE_OPENCL
 452 int r600_compute_shader_create(struct pipe_context * ctx,
 453         LLVMModuleRef mod,  struct r600_bytecode * bytecode);
 454 #endif
 455 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 456
 457 /* r600_state.c */
 458 void r600_set_scissor_state(struct r600_context *rctx,
 459                             const struct pipe_scissor_state *state);
 460 void r600_update_sampler_states(struct r600_context *rctx);
 461 void r600_init_state_functions(struct r600_context *rctx);
 462 void r600_init_atom_start_cs(struct r600_context *rctx);
 463 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 464 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 465 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 466 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 467 void r600_polygon_offset_update(struct r600_context *rctx);
 468 void r600_adjust_gprs(struct r600_context *rctx);
 469 boolean r600_is_format_supported(struct pipe_screen *screen,
 470                                  enum pipe_format format,
 471                                  enum pipe_texture_target target,
 472                                  unsigned sample_count,
 473                                  unsigned usage);
 474
 475 /* r600_texture.c */
 476 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 477 void r600_init_surface_functions(struct r600_context *r600);
 478 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 479                                   const unsigned char *swizzle_view,
 480                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 481 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 482                                         unsigned level, unsigned layer);
 483
 484 /* r600_translate.c */
 485 void r600_translate_index_buffer(struct r600_context *r600,
 486                                  struct pipe_index_buffer *ib,
 487                                  unsigned count);
 488
 489 /* r600_state_common.c */
 490 void r600_init_atom(struct r600_atom *atom,
 491                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
 492                     unsigned num_dw, enum r600_atom_flags flags);
 493 void r600_init_common_atoms(struct r600_context *rctx);
 494 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 495 void r600_texture_barrier(struct pipe_context *ctx);
 496 void r600_set_index_buffer(struct pipe_context *ctx,
 497                            const struct pipe_index_buffer *ib);
 498 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 499                              const struct pipe_vertex_buffer *buffers);
 500 void *r600_create_vertex_elements(struct pipe_context *ctx,
 501                                   unsigned count,
 502                                   const struct pipe_vertex_element *elements);
 503 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 504 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 505 void r600_set_blend_color(struct pipe_context *ctx,
 506                           const struct pipe_blend_color *state);
 507 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 508 void r600_set_max_scissor(struct r600_context *rctx);
 509 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 510 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 511 void r600_sampler_view_destroy(struct pipe_context *ctx,
 512                                struct pipe_sampler_view *state);
 513 void r600_delete_state(struct pipe_context *ctx, void *state);
 514 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 515 void *r600_create_shader_state_ps(struct pipe_context *ctx,
 516                    const struct pipe_shader_state *state);
 517 void *r600_create_shader_state_vs(struct pipe_context *ctx,
 518                    const struct pipe_shader_state *state);
 519 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 520 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 521 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 522 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 523 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
 524 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 525                               struct pipe_constant_buffer *cb);
 526 struct pipe_stream_output_target *
 527 r600_create_so_target(struct pipe_context *ctx,
 528                       struct pipe_resource *buffer,
 529                       unsigned buffer_offset,
 530                       unsigned buffer_size);
 531 void r600_so_target_destroy(struct pipe_context *ctx,
 532                             struct pipe_stream_output_target *target);
 533 void r600_set_so_targets(struct pipe_context *ctx,
 534                          unsigned num_targets,
 535                          struct pipe_stream_output_target **targets,
 536                          unsigned append_bitmask);
 537 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 538                                const struct pipe_stencil_ref *state);
 539 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 540 uint32_t r600_translate_stencil_op(int s_op);
 541 uint32_t r600_translate_fill(uint32_t func);
 542 unsigned r600_tex_wrap(unsigned wrap);
 543 unsigned r600_tex_filter(unsigned filter);
 544 unsigned r600_tex_mipfilter(unsigned filter);
 545 unsigned r600_tex_compare(unsigned compare);
 546
 547 /*
 548  * Helpers for building command buffers
 549  */
 550
 551 #define PKT3_SET_CONFIG_REG     0x68
 552 #define PKT3_SET_CONTEXT_REG    0x69
 553 #define PKT3_SET_CTL_CONST      0x6F
 554 #define PKT3_SET_LOOP_CONST                    0x6C
 555
 556 #define R600_CONFIG_REG_OFFSET  0x08000
 557 #define R600_CONTEXT_REG_OFFSET 0x28000
 558 #define R600_CTL_CONST_OFFSET   0x3CFF0
 559 #define R600_LOOP_CONST_OFFSET                 0X0003E200
 560 #define EG_LOOP_CONST_OFFSET               0x0003A200
 561
 562 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 563 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 564 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
 565 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 566 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 567
 568 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
 569 {
 570         cb->buf[cb->atom.num_dw++] = value;
 571 }
 572
 573 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 574 {
 575         assert(reg < R600_CONTEXT_REG_OFFSET);
 576         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 577         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 578         cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 579 }
 580
 581 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 582 {
 583         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 584         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 585         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 586         cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 587 }
 588
 589 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 590 {
 591         assert(reg >= R600_CTL_CONST_OFFSET);
 592         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 593         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 594         cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 595 }
 596
 597 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 598 {
 599         assert(reg >= R600_LOOP_CONST_OFFSET);
 600         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 601         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 602         cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
 603 }
 604
 605 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 606 {
 607         assert(reg >= EG_LOOP_CONST_OFFSET);
 608         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 609         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 610         cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
 611 }
 612
 613 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 614 {
 615         r600_store_config_reg_seq(cb, reg, 1);
 616         r600_store_value(cb, value);
 617 }
 618
 619 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 620 {
 621         r600_store_context_reg_seq(cb, reg, 1);
 622         r600_store_value(cb, value);
 623 }
 624
 625 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 626 {
 627         r600_store_ctl_const_seq(cb, reg, 1);
 628         r600_store_value(cb, value);
 629 }
 630
 631 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 632 {
 633         r600_store_loop_const_seq(cb, reg, 1);
 634         r600_store_value(cb, value);
 635 }
 636
 637 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 638 {
 639         eg_store_loop_const_seq(cb, reg, 1);
 640         r600_store_value(cb, value);
 641 }
 642
 643 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
 644 void r600_release_command_buffer(struct r600_command_buffer *cb);
 645
 646 /*
 647  * Helpers for emitting state into a command stream directly.
 648  */
 649
 650 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
 651                                              enum radeon_bo_usage usage)
 652 {
 653         assert(usage);
 654         return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
 655 }
 656
 657 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
 658 {
 659         cs->buf[cs->cdw++] = value;
 660 }
 661
 662 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 663 {
 664         assert(reg < R600_CONTEXT_REG_OFFSET);
 665         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 666         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 667         cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 668 }
 669
 670 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 671 {
 672         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 673         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 674         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 675         cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 676 }
 677
 678 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 679 {
 680         assert(reg >= R600_CTL_CONST_OFFSET);
 681         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 682         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 683         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 684 }
 685
 686 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 687 {
 688         r600_write_config_reg_seq(cs, reg, 1);
 689         r600_write_value(cs, value);
 690 }
 691
 692 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 693 {
 694         r600_write_context_reg_seq(cs, reg, 1);
 695         r600_write_value(cs, value);
 696 }
 697
 698 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 699 {
 700         r600_write_ctl_const_seq(cs, reg, 1);
 701         r600_write_value(cs, value);
 702 }
 703
 704 /*
 705  * common helpers
 706  */
 707 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 708 {
 709         return value * (1 << frac_bits);
 710 }
 711 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 712
 713 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 714 {
 715         if (filter <= 1)   return 0;
 716         if (filter <= 2)   return 1;
 717         if (filter <= 4)   return 2;
 718         if (filter <= 8)   return 3;
 719          /* else */        return 4;
 720 }
 721
 722 /* 12.4 fixed-point */
 723 static INLINE unsigned r600_pack_float_12p4(float x)
 724 {
 725         return x <= 0    ? 0 :
 726                x >= 4096 ? 0xffff : x * 16;
 727 }
 728
 729 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 730 {
 731         struct r600_screen *rscreen = (struct r600_screen*)screen;
 732         struct r600_resource *rresource = (struct r600_resource*)resource;
 733
 734         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 735 }
 736
 737 #endif