2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../../winsys/radeon/drm/radeon_winsys.h"
31 #include "pipe/p_state.h"
32 #include "pipe/p_screen.h"
33 #include "pipe/p_context.h"
34 #include "util/u_math.h"
35 #include "util/u_slab.h"
36 #include "util/u_vbuf.h"
38 #include "r600_public.h"
39 #include "r600_shader.h"
40 #include "r600_resource.h"
42 #define R600_MAX_CONST_BUFFERS 2
43 #define R600_MAX_CONST_BUFFER_SIZE 4096
45 #ifdef PIPE_ARCH_BIG_ENDIAN
46 #define R600_BIG_ENDIAN 1
48 #define R600_BIG_ENDIAN 0
51 enum r600_atom_flags {
52 /* When set, atoms are added at the beginning of the dirty list
53 * instead of the end. */
57 /* This encapsulates a state or an operation which can emitted into the GPU
58 * command stream. It's not limited to states only, it can be used for anything
59 * that wants to write commands into the CS (e.g. cache flushes). */
61 void (*emit)(struct r600_context *ctx, struct r600_atom *state);
64 enum r600_atom_flags flags;
67 struct list_head head;
70 struct r600_atom_surface_sync {
71 struct r600_atom atom;
72 unsigned flush_flags; /* CP_COHER_CNTL */
75 enum r600_pipe_state_id {
76 R600_PIPE_STATE_BLEND = 0,
77 R600_PIPE_STATE_BLEND_COLOR,
78 R600_PIPE_STATE_CONFIG,
79 R600_PIPE_STATE_SEAMLESS_CUBEMAP,
81 R600_PIPE_STATE_SCISSOR,
82 R600_PIPE_STATE_VIEWPORT,
83 R600_PIPE_STATE_RASTERIZER,
85 R600_PIPE_STATE_FRAMEBUFFER,
87 R600_PIPE_STATE_STENCIL_REF,
88 R600_PIPE_STATE_PS_SHADER,
89 R600_PIPE_STATE_VS_SHADER,
90 R600_PIPE_STATE_CONSTANT,
91 R600_PIPE_STATE_SAMPLER,
92 R600_PIPE_STATE_RESOURCE,
93 R600_PIPE_STATE_POLYGON_OFFSET,
94 R600_PIPE_STATE_FETCH_SHADER,
98 struct r600_pipe_fences {
99 struct r600_resource *bo;
102 /* linked list of preallocated blocks */
103 struct list_head blocks;
104 /* linked list of freed fences */
105 struct list_head pool;
110 struct pipe_screen screen;
111 struct radeon_winsys *ws;
113 enum chip_class chip_class;
114 struct radeon_info info;
115 struct r600_tiling_info tiling_info;
116 struct util_slab_mempool pool_buffers;
117 struct r600_pipe_fences fences;
119 unsigned num_contexts;
120 unsigned use_surface;
122 /* for thread-safe write accessing to num_contexts */
123 pipe_mutex mutex_num_contexts;
126 struct r600_pipe_sampler_view {
127 struct pipe_sampler_view base;
128 struct r600_pipe_resource_state state;
131 struct r600_pipe_rasterizer {
132 struct r600_pipe_state rstate;
135 unsigned sprite_coord_enable;
136 unsigned clip_plane_enable;
137 unsigned pa_sc_line_stipple;
138 unsigned pa_su_sc_mode_cntl;
139 unsigned pa_cl_clip_cntl;
144 struct r600_pipe_blend {
145 struct r600_pipe_state rstate;
146 unsigned cb_target_mask;
147 unsigned cb_color_control;
150 struct r600_pipe_dsa {
151 struct r600_pipe_state rstate;
153 unsigned db_render_override;
154 unsigned db_render_control;
159 struct r600_vertex_element
162 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
163 struct u_vbuf_elements *vmgr_elements;
164 struct r600_resource *fetch_shader;
166 struct r600_pipe_state rstate;
167 /* if offset is to big for fetch instructio we need to alterate
168 * offset of vertex buffer, record here the offset need to add
170 unsigned vbuffer_need_offset;
171 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS];
174 struct r600_pipe_shader {
175 struct r600_shader shader;
176 struct r600_pipe_state rstate;
177 struct r600_resource *bo;
178 struct r600_resource *bo_fetch;
179 struct r600_vertex_element vertex_elements;
180 struct tgsi_token *tokens;
181 unsigned sprite_coord_enable;
183 unsigned pa_cl_vs_out_cntl;
184 struct pipe_stream_output_info so;
187 struct r600_pipe_sampler_state {
188 struct r600_pipe_state rstate;
189 boolean seamless_cube_map;
192 /* needed for blitter save */
193 #define NUM_TEX_UNITS 16
195 struct r600_textures_info {
196 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
197 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS];
201 bool is_array_sampler[NUM_TEX_UNITS];
205 struct pipe_reference reference;
206 unsigned index; /* in the shared bo */
207 struct r600_resource *sleep_bo;
208 struct list_head head;
211 #define FENCE_BLOCK_SIZE 16
213 struct r600_fence_block {
214 struct r600_fence fences[FENCE_BLOCK_SIZE];
215 struct list_head head;
218 #define R600_CONSTANT_ARRAY_SIZE 256
219 #define R600_RESOURCE_ARRAY_SIZE 160
221 struct r600_stencil_ref
228 struct r600_context {
229 struct pipe_context context;
230 struct blitter_context *blitter;
231 enum radeon_family family;
232 enum chip_class chip_class;
233 unsigned r6xx_num_clause_temp_gprs;
234 void *custom_dsa_flush;
235 struct r600_screen *screen;
236 struct radeon_winsys *ws;
237 struct r600_pipe_state *states[R600_PIPE_NSTATES];
238 struct r600_vertex_element *vertex_elements;
239 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
240 struct pipe_framebuffer_state framebuffer;
241 unsigned cb_target_mask;
242 unsigned cb_color_control;
243 unsigned pa_sc_line_stipple;
244 unsigned pa_su_sc_mode_cntl;
245 unsigned pa_cl_clip_cntl;
246 /* for saving when using blitter */
247 struct pipe_stencil_ref stencil_ref;
248 struct pipe_viewport_state viewport;
249 struct pipe_clip_state clip;
250 struct r600_pipe_state config;
251 struct r600_pipe_shader *ps_shader;
252 struct r600_pipe_shader *vs_shader;
253 struct r600_pipe_state vs_const_buffer;
254 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
255 struct r600_pipe_state ps_const_buffer;
256 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
257 struct r600_pipe_rasterizer *rasterizer;
258 struct r600_pipe_state vgt;
259 struct r600_pipe_state spi;
260 struct pipe_query *current_render_cond;
261 unsigned current_render_cond_mode;
262 struct pipe_query *saved_render_cond;
263 unsigned saved_render_cond_mode;
264 /* shader information */
266 unsigned sprite_coord_enable;
267 boolean export_16bpc;
269 boolean alpha_ref_dirty;
271 struct r600_textures_info vs_samplers;
272 struct r600_textures_info ps_samplers;
274 struct u_vbuf *vbuf_mgr;
275 struct util_slab_mempool pool_transfers;
276 boolean have_depth_texture, have_depth_fb;
278 unsigned default_ps_gprs, default_vs_gprs;
280 /* States based on r600_state. */
281 struct list_head dirty_states;
282 struct r600_atom_surface_sync atom_surface_sync;
283 struct r600_atom atom_r6xx_flush_and_inv;
285 /* Below are variables from the old r600_context.
287 struct radeon_winsys_cs *cs;
289 struct r600_range *range;
291 struct r600_block **blocks;
292 struct list_head dirty;
293 struct list_head resource_dirty;
294 struct list_head enable_list;
295 unsigned pm4_dirty_cdwords;
296 unsigned ctx_pm4_ndwords;
297 unsigned init_dwords;
299 /* The list of active queries. Only one query of each type can be active. */
300 struct list_head active_query_list;
301 unsigned num_cs_dw_queries_suspend;
302 unsigned num_cs_dw_streamout_end;
304 unsigned backend_mask;
305 unsigned max_db; /* for OQ */
307 boolean predicate_drawing;
308 struct r600_range ps_resources;
309 struct r600_range vs_resources;
310 struct r600_range fs_resources;
311 int num_ps_resources, num_vs_resources, num_fs_resources;
313 unsigned num_so_targets;
314 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
315 boolean streamout_start;
316 unsigned streamout_append_bitmask;
317 unsigned *vs_so_stride_in_dw;
320 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
322 atom->emit(rctx, atom);
324 if (atom->head.next && atom->head.prev)
325 LIST_DELINIT(&atom->head);
328 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
331 if (state->flags & EMIT_EARLY) {
332 LIST_ADD(&state->head, &rctx->dirty_states);
334 LIST_ADDTAIL(&state->head, &rctx->dirty_states);
340 /* evergreen_state.c */
341 void evergreen_init_state_functions(struct r600_context *rctx);
342 void evergreen_init_config(struct r600_context *rctx);
343 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
344 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
345 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
346 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
347 void evergreen_polygon_offset_update(struct r600_context *rctx);
348 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
349 struct r600_pipe_resource_state *rstate);
350 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
351 struct r600_pipe_resource_state *rstate,
352 struct r600_resource *rbuffer,
353 unsigned offset, unsigned stride,
354 enum radeon_bo_usage usage);
355 boolean evergreen_is_format_supported(struct pipe_screen *screen,
356 enum pipe_format format,
357 enum pipe_texture_target target,
358 unsigned sample_count,
362 void r600_init_blit_functions(struct r600_context *rctx);
363 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
364 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
365 void r600_flush_depth_textures(struct r600_context *rctx);
368 bool r600_init_resource(struct r600_screen *rscreen,
369 struct r600_resource *res,
370 unsigned size, unsigned alignment,
371 unsigned bind, unsigned usage);
372 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
373 const struct pipe_resource *templ);
374 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
375 void *ptr, unsigned bytes,
377 void r600_upload_index_buffer(struct r600_context *rctx,
378 struct pipe_index_buffer *ib, unsigned count);
382 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
386 void r600_init_query_functions(struct r600_context *rctx);
388 /* r600_resource.c */
389 void r600_init_context_resource_functions(struct r600_context *r600);
392 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
393 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
394 int r600_find_vs_semantic_index(struct r600_shader *vs,
395 struct r600_shader *ps, int id);
398 void r600_update_sampler_states(struct r600_context *rctx);
399 void r600_init_state_functions(struct r600_context *rctx);
400 void r600_init_config(struct r600_context *rctx);
401 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
402 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
403 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
404 void *r600_create_db_flush_dsa(struct r600_context *rctx);
405 void r600_polygon_offset_update(struct r600_context *rctx);
406 void r600_pipe_init_buffer_resource(struct r600_context *rctx,
407 struct r600_pipe_resource_state *rstate);
408 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
409 struct r600_resource *rbuffer,
410 unsigned offset, unsigned stride,
411 enum radeon_bo_usage usage);
412 void r600_adjust_gprs(struct r600_context *rctx);
413 boolean r600_is_format_supported(struct pipe_screen *screen,
414 enum pipe_format format,
415 enum pipe_texture_target target,
416 unsigned sample_count,
420 void r600_init_screen_texture_functions(struct pipe_screen *screen);
421 void r600_init_surface_functions(struct r600_context *r600);
422 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
423 const unsigned char *swizzle_view,
424 uint32_t *word4_p, uint32_t *yuv_format_p);
425 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
426 unsigned level, unsigned layer);
428 /* r600_translate.c */
429 void r600_translate_index_buffer(struct r600_context *r600,
430 struct pipe_index_buffer *ib,
433 /* r600_state_common.c */
434 void r600_init_common_atoms(struct r600_context *rctx);
435 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
436 void r600_texture_barrier(struct pipe_context *ctx);
437 void r600_set_index_buffer(struct pipe_context *ctx,
438 const struct pipe_index_buffer *ib);
439 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
440 const struct pipe_vertex_buffer *buffers);
441 void *r600_create_vertex_elements(struct pipe_context *ctx,
443 const struct pipe_vertex_element *elements);
444 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
445 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
446 void r600_set_blend_color(struct pipe_context *ctx,
447 const struct pipe_blend_color *state);
448 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
449 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
450 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
451 void r600_sampler_view_destroy(struct pipe_context *ctx,
452 struct pipe_sampler_view *state);
453 void r600_delete_state(struct pipe_context *ctx, void *state);
454 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
455 void *r600_create_shader_state(struct pipe_context *ctx,
456 const struct pipe_shader_state *state);
457 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
458 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
459 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
460 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
461 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
462 struct pipe_resource *buffer);
463 struct pipe_stream_output_target *
464 r600_create_so_target(struct pipe_context *ctx,
465 struct pipe_resource *buffer,
466 unsigned buffer_offset,
467 unsigned buffer_size);
468 void r600_so_target_destroy(struct pipe_context *ctx,
469 struct pipe_stream_output_target *target);
470 void r600_set_so_targets(struct pipe_context *ctx,
471 unsigned num_targets,
472 struct pipe_stream_output_target **targets,
473 unsigned append_bitmask);
474 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
475 const struct pipe_stencil_ref *state);
476 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
477 uint32_t r600_translate_stencil_op(int s_op);
478 uint32_t r600_translate_fill(uint32_t func);
479 unsigned r600_tex_wrap(unsigned wrap);
480 unsigned r600_tex_filter(unsigned filter);
481 unsigned r600_tex_mipfilter(unsigned filter);
482 unsigned r600_tex_compare(unsigned compare);
487 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
489 return value * (1 << frac_bits);
491 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
493 static inline unsigned r600_tex_aniso_filter(unsigned filter)
495 if (filter <= 1) return 0;
496 if (filter <= 2) return 1;
497 if (filter <= 4) return 2;
498 if (filter <= 8) return 3;
502 /* 12.4 fixed-point */
503 static INLINE unsigned r600_pack_float_12p4(float x)
506 x >= 4096 ? 0xffff : x * 16;