2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include <pipe/p_defines.h>
26 #include <pipe/p_state.h>
27 #include <pipe/p_context.h>
28 #include <tgsi/tgsi_scan.h>
29 #include <tgsi/tgsi_parse.h>
30 #include <tgsi/tgsi_util.h>
31 #include <util/u_blitter.h>
32 #include <util/u_double_list.h>
33 #include "util/u_format.h"
34 #include <util/u_format_s3tc.h>
35 #include <util/u_transfer.h>
36 #include <util/u_surface.h>
37 #include <util/u_pack_color.h>
38 #include <util/u_memory.h>
39 #include <util/u_inlines.h>
40 #include "util/u_upload_mgr.h"
41 #include "os/os_time.h"
42 #include <pipebuffer/pb_buffer.h>
45 #include "r600_resource.h"
46 #include "r600_shader.h"
47 #include "r600_pipe.h"
48 #include "r600_state_inlines.h"
53 static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx)
55 struct r600_fence *fence = NULL;
57 if (!ctx->fences.bo) {
58 /* Create the shared buffer object */
59 ctx->fences.bo = r600_bo(ctx->radeon, 4096, 0, 0, 0);
60 if (!ctx->fences.bo) {
61 R600_ERR("r600: failed to create bo for fence objects\n");
64 ctx->fences.data = r600_bo_map(ctx->radeon, ctx->fences.bo, PB_USAGE_UNSYNCHRONIZED, NULL);
67 if (!LIST_IS_EMPTY(&ctx->fences.pool)) {
68 struct r600_fence *entry;
70 /* Try to find a freed fence that has been signalled */
71 LIST_FOR_EACH_ENTRY(entry, &ctx->fences.pool, head) {
72 if (ctx->fences.data[entry->index] != 0) {
73 LIST_DELINIT(&entry->head);
81 /* Allocate a new fence */
82 struct r600_fence_block *block;
85 if ((ctx->fences.next_index + 1) >= 1024) {
86 R600_ERR("r600: too many concurrent fences\n");
90 index = ctx->fences.next_index++;
92 if (!(index % FENCE_BLOCK_SIZE)) {
93 /* Allocate a new block */
94 block = CALLOC_STRUCT(r600_fence_block);
98 LIST_ADD(&block->head, &ctx->fences.blocks);
100 block = LIST_ENTRY(struct r600_fence_block, ctx->fences.blocks.next, head);
103 fence = &block->fences[index % FENCE_BLOCK_SIZE];
105 fence->index = index;
108 pipe_reference_init(&fence->reference, 1);
110 ctx->fences.data[fence->index] = 0;
111 r600_context_emit_fence(&ctx->ctx, ctx->fences.bo, fence->index, 1);
115 static void r600_flush(struct pipe_context *ctx,
116 struct pipe_fence_handle **fence)
118 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
119 struct r600_fence **rfence = (struct r600_fence**)fence;
127 *rfence = r600_create_fence(rctx);
130 sprintf(dname, "gallium-%08d.bof", dc);
132 r600_context_dump_bof(&rctx->ctx, dname);
133 R600_ERR("dumped %s\n", dname);
137 r600_context_flush(&rctx->ctx);
140 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
142 pipe_mutex_lock(rscreen->mutex_num_contexts);
144 rscreen->num_contexts++;
146 if (rscreen->num_contexts > 1)
147 util_slab_set_thread_safety(&rscreen->pool_buffers,
148 UTIL_SLAB_MULTITHREADED);
150 rscreen->num_contexts--;
152 if (rscreen->num_contexts <= 1)
153 util_slab_set_thread_safety(&rscreen->pool_buffers,
154 UTIL_SLAB_SINGLETHREADED);
156 pipe_mutex_unlock(rscreen->mutex_num_contexts);
159 static void r600_destroy_context(struct pipe_context *context)
161 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
163 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
164 util_unreference_framebuffer_state(&rctx->framebuffer);
166 r600_context_fini(&rctx->ctx);
168 util_blitter_destroy(rctx->blitter);
170 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
171 free(rctx->states[i]);
174 u_vbuf_destroy(rctx->vbuf_mgr);
175 util_slab_destroy(&rctx->pool_transfers);
177 if (rctx->fences.bo) {
178 struct r600_fence_block *entry, *tmp;
180 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rctx->fences.blocks, head) {
181 LIST_DEL(&entry->head);
185 r600_bo_unmap(rctx->radeon, rctx->fences.bo);
186 r600_bo_reference(rctx->radeon, &rctx->fences.bo, NULL);
189 r600_update_num_contexts(rctx->screen, -1);
194 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
196 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
197 struct r600_screen* rscreen = (struct r600_screen *)screen;
198 enum chip_class class;
203 r600_update_num_contexts(rscreen, 1);
205 rctx->context.winsys = rscreen->screen.winsys;
206 rctx->context.screen = screen;
207 rctx->context.priv = priv;
208 rctx->context.destroy = r600_destroy_context;
209 rctx->context.flush = r600_flush;
211 /* Easy accessing of screen/winsys. */
212 rctx->screen = rscreen;
213 rctx->radeon = rscreen->radeon;
214 rctx->family = r600_get_family(rctx->radeon);
216 rctx->fences.bo = NULL;
217 rctx->fences.data = NULL;
218 rctx->fences.next_index = 0;
219 LIST_INITHEAD(&rctx->fences.pool);
220 LIST_INITHEAD(&rctx->fences.blocks);
222 r600_init_blit_functions(rctx);
223 r600_init_query_functions(rctx);
224 r600_init_context_resource_functions(rctx);
225 r600_init_surface_functions(rctx);
226 rctx->context.draw_vbo = r600_draw_vbo;
228 switch (r600_get_family(rctx->radeon)) {
241 r600_init_state_functions(rctx);
242 if (r600_context_init(&rctx->ctx, rctx->radeon)) {
243 r600_destroy_context(&rctx->context);
246 r600_init_config(rctx);
260 evergreen_init_state_functions(rctx);
261 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
262 r600_destroy_context(&rctx->context);
265 evergreen_init_config(rctx);
268 R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
269 r600_destroy_context(&rctx->context);
273 util_slab_create(&rctx->pool_transfers,
274 sizeof(struct pipe_transfer), 64,
275 UTIL_SLAB_SINGLETHREADED);
277 rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256,
278 PIPE_BIND_VERTEX_BUFFER |
279 PIPE_BIND_INDEX_BUFFER |
280 PIPE_BIND_CONSTANT_BUFFER,
281 U_VERTEX_FETCH_DWORD_ALIGNED);
282 if (!rctx->vbuf_mgr) {
283 r600_destroy_context(&rctx->context);
287 rctx->blitter = util_blitter_create(&rctx->context);
288 if (rctx->blitter == NULL) {
289 r600_destroy_context(&rctx->context);
293 class = r600_get_family_class(rctx->radeon);
294 if (class == R600 || class == R700)
295 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
297 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
299 return &rctx->context;
305 static const char* r600_get_vendor(struct pipe_screen* pscreen)
310 static const char *r600_get_family_name(enum radeon_family family)
313 case CHIP_R600: return "AMD R600";
314 case CHIP_RV610: return "AMD RV610";
315 case CHIP_RV630: return "AMD RV630";
316 case CHIP_RV670: return "AMD RV670";
317 case CHIP_RV620: return "AMD RV620";
318 case CHIP_RV635: return "AMD RV635";
319 case CHIP_RS780: return "AMD RS780";
320 case CHIP_RS880: return "AMD RS880";
321 case CHIP_RV770: return "AMD RV770";
322 case CHIP_RV730: return "AMD RV730";
323 case CHIP_RV710: return "AMD RV710";
324 case CHIP_RV740: return "AMD RV740";
325 case CHIP_CEDAR: return "AMD CEDAR";
326 case CHIP_REDWOOD: return "AMD REDWOOD";
327 case CHIP_JUNIPER: return "AMD JUNIPER";
328 case CHIP_CYPRESS: return "AMD CYPRESS";
329 case CHIP_HEMLOCK: return "AMD HEMLOCK";
330 case CHIP_PALM: return "AMD PALM";
331 case CHIP_SUMO: return "AMD SUMO";
332 case CHIP_SUMO2: return "AMD SUMO2";
333 case CHIP_BARTS: return "AMD BARTS";
334 case CHIP_TURKS: return "AMD TURKS";
335 case CHIP_CAICOS: return "AMD CAICOS";
336 case CHIP_CAYMAN: return "AMD CAYMAN";
337 default: return "AMD unknown";
341 static const char* r600_get_name(struct pipe_screen* pscreen)
343 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
344 enum radeon_family family = r600_get_family(rscreen->radeon);
346 return r600_get_family_name(family);
349 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
351 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
352 enum radeon_family family = r600_get_family(rscreen->radeon);
355 /* Supported features (boolean caps). */
356 case PIPE_CAP_NPOT_TEXTURES:
357 case PIPE_CAP_TWO_SIDED_STENCIL:
359 case PIPE_CAP_DUAL_SOURCE_BLEND:
360 case PIPE_CAP_ANISOTROPIC_FILTER:
361 case PIPE_CAP_POINT_SPRITE:
362 case PIPE_CAP_OCCLUSION_QUERY:
363 case PIPE_CAP_TEXTURE_SHADOW_MAP:
364 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
365 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
366 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
367 case PIPE_CAP_TEXTURE_SWIZZLE:
368 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
369 case PIPE_CAP_DEPTH_CLAMP:
370 case PIPE_CAP_SHADER_STENCIL_EXPORT:
371 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
372 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
373 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
374 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
376 case PIPE_CAP_SEAMLESS_CUBE_MAP:
377 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
380 /* Supported except the original R600. */
381 case PIPE_CAP_INDEP_BLEND_ENABLE:
382 case PIPE_CAP_INDEP_BLEND_FUNC:
383 /* R600 doesn't support per-MRT blends */
384 return family == CHIP_R600 ? 0 : 1;
386 /* Supported on Evergreen. */
387 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
388 return family >= CHIP_CEDAR ? 1 : 0;
390 /* Unsupported features. */
391 case PIPE_CAP_STREAM_OUTPUT:
392 case PIPE_CAP_PRIMITIVE_RESTART:
393 case PIPE_CAP_TGSI_INSTANCEID:
394 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
395 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
398 case PIPE_CAP_ARRAY_TEXTURES:
399 /* fix once the CS checker upstream is fixed */
400 return debug_get_bool_option("R600_ARRAY_TEXTURE", FALSE);
403 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
404 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
405 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
406 if (family >= CHIP_CEDAR)
410 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
411 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
413 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
416 /* Render targets. */
417 case PIPE_CAP_MAX_RENDER_TARGETS:
418 /* FIXME some r6xx are buggy and can only do 4 */
421 /* Timer queries, present when the clock frequency is non zero. */
422 case PIPE_CAP_TIMER_QUERY:
423 return r600_get_clock_crystal_freq(rscreen->radeon) != 0;
426 R600_ERR("r600: unknown param %d\n", param);
431 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
433 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
434 enum radeon_family family = r600_get_family(rscreen->radeon);
437 case PIPE_CAP_MAX_LINE_WIDTH:
438 case PIPE_CAP_MAX_LINE_WIDTH_AA:
439 case PIPE_CAP_MAX_POINT_WIDTH:
440 case PIPE_CAP_MAX_POINT_WIDTH_AA:
441 if (family >= CHIP_CEDAR)
445 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
447 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
450 R600_ERR("r600: unsupported paramf %d\n", param);
455 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
459 case PIPE_SHADER_FRAGMENT:
460 case PIPE_SHADER_VERTEX:
462 case PIPE_SHADER_GEOMETRY:
463 /* TODO: support and enable geometry programs */
466 /* TODO: support tessellation on Evergreen */
470 /* TODO: all these should be fixed, since r600 surely supports much more! */
472 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
473 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
474 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
475 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
477 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
478 return 8; /* FIXME */
479 case PIPE_SHADER_CAP_MAX_INPUTS:
480 if(shader == PIPE_SHADER_FRAGMENT)
484 case PIPE_SHADER_CAP_MAX_TEMPS:
485 return 256; /* Max native temporaries. */
486 case PIPE_SHADER_CAP_MAX_ADDRS:
487 /* FIXME Isn't this equal to TEMPS? */
488 return 1; /* Max native address registers */
489 case PIPE_SHADER_CAP_MAX_CONSTS:
490 return R600_MAX_CONST_BUFFER_SIZE;
491 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
492 return R600_MAX_CONST_BUFFERS;
493 case PIPE_SHADER_CAP_MAX_PREDS:
494 return 0; /* FIXME */
495 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
497 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
498 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
499 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
500 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
502 case PIPE_SHADER_CAP_SUBROUTINES:
509 static boolean r600_is_format_supported(struct pipe_screen* screen,
510 enum pipe_format format,
511 enum pipe_texture_target target,
512 unsigned sample_count,
516 if (target >= PIPE_MAX_TEXTURE_TYPES) {
517 R600_ERR("r600: unsupported texture type %d\n", target);
521 if (!util_format_is_supported(format, usage))
525 if (sample_count > 1)
528 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
529 r600_is_sampler_format_supported(screen, format)) {
530 retval |= PIPE_BIND_SAMPLER_VIEW;
533 if ((usage & (PIPE_BIND_RENDER_TARGET |
534 PIPE_BIND_DISPLAY_TARGET |
536 PIPE_BIND_SHARED)) &&
537 r600_is_colorbuffer_format_supported(format)) {
539 (PIPE_BIND_RENDER_TARGET |
540 PIPE_BIND_DISPLAY_TARGET |
545 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
546 r600_is_zs_format_supported(format)) {
547 retval |= PIPE_BIND_DEPTH_STENCIL;
550 if (usage & PIPE_BIND_VERTEX_BUFFER) {
551 struct r600_screen *rscreen = (struct r600_screen *)screen;
552 enum radeon_family family = r600_get_family(rscreen->radeon);
554 if (r600_is_vertex_format_supported(format, family)) {
555 retval |= PIPE_BIND_VERTEX_BUFFER;
559 if (usage & PIPE_BIND_TRANSFER_READ)
560 retval |= PIPE_BIND_TRANSFER_READ;
561 if (usage & PIPE_BIND_TRANSFER_WRITE)
562 retval |= PIPE_BIND_TRANSFER_WRITE;
564 return retval == usage;
567 static void r600_destroy_screen(struct pipe_screen* pscreen)
569 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
574 radeon_decref(rscreen->radeon);
576 util_slab_destroy(&rscreen->pool_buffers);
577 pipe_mutex_destroy(rscreen->mutex_num_contexts);
581 static void r600_fence_reference(struct pipe_screen *pscreen,
582 struct pipe_fence_handle **ptr,
583 struct pipe_fence_handle *fence)
585 struct r600_fence **oldf = (struct r600_fence**)ptr;
586 struct r600_fence *newf = (struct r600_fence*)fence;
588 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
589 struct r600_pipe_context *ctx = (*oldf)->ctx;
590 LIST_ADDTAIL(&(*oldf)->head, &ctx->fences.pool);
596 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
597 struct pipe_fence_handle *fence)
599 struct r600_fence *rfence = (struct r600_fence*)fence;
600 struct r600_pipe_context *ctx = rfence->ctx;
602 return ctx->fences.data[rfence->index];
605 static boolean r600_fence_finish(struct pipe_screen *pscreen,
606 struct pipe_fence_handle *fence,
609 struct r600_fence *rfence = (struct r600_fence*)fence;
610 struct r600_pipe_context *ctx = rfence->ctx;
611 int64_t start_time = 0;
614 if (timeout != PIPE_TIMEOUT_INFINITE) {
615 start_time = os_time_get();
617 /* Convert to microseconds. */
621 while (ctx->fences.data[rfence->index] == 0) {
629 if (timeout != PIPE_TIMEOUT_INFINITE &&
630 os_time_get() - start_time >= timeout) {
638 struct pipe_screen *r600_screen_create(struct radeon *radeon)
640 struct r600_screen *rscreen;
642 rscreen = CALLOC_STRUCT(r600_screen);
643 if (rscreen == NULL) {
647 rscreen->radeon = radeon;
648 rscreen->screen.winsys = (struct pipe_winsys*)radeon;
649 rscreen->screen.destroy = r600_destroy_screen;
650 rscreen->screen.get_name = r600_get_name;
651 rscreen->screen.get_vendor = r600_get_vendor;
652 rscreen->screen.get_param = r600_get_param;
653 rscreen->screen.get_shader_param = r600_get_shader_param;
654 rscreen->screen.get_paramf = r600_get_paramf;
655 rscreen->screen.is_format_supported = r600_is_format_supported;
656 rscreen->screen.context_create = r600_create_context;
657 rscreen->screen.fence_reference = r600_fence_reference;
658 rscreen->screen.fence_signalled = r600_fence_signalled;
659 rscreen->screen.fence_finish = r600_fence_finish;
660 r600_init_screen_resource_functions(&rscreen->screen);
662 rscreen->tiling_info = r600_get_tiling_info(radeon);
663 util_format_s3tc_init();
665 util_slab_create(&rscreen->pool_buffers,
666 sizeof(struct r600_resource_buffer), 64,
667 UTIL_SLAB_SINGLETHREADED);
669 pipe_mutex_init(rscreen->mutex_num_contexts);
671 return &rscreen->screen;