Tizen 2.0 Release
[profile/ivi/osmesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * on the rights to use, copy, modify, merge, publish, distribute, sub
8  * license, and/or sell copies of the Software, and to permit persons to whom
9  * the Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 #include <stdio.h>
24 #include <errno.h>
25 #include <pipe/p_defines.h>
26 #include <pipe/p_state.h>
27 #include <pipe/p_context.h>
28 #include <tgsi/tgsi_scan.h>
29 #include <tgsi/tgsi_parse.h>
30 #include <tgsi/tgsi_util.h>
31 #include <util/u_blitter.h>
32 #include <util/u_double_list.h>
33 #include "util/u_format.h"
34 #include <util/u_format_s3tc.h>
35 #include <util/u_transfer.h>
36 #include <util/u_surface.h>
37 #include <util/u_pack_color.h>
38 #include <util/u_memory.h>
39 #include <util/u_inlines.h>
40 #include "util/u_upload_mgr.h"
41 #include "os/os_time.h"
42 #include <pipebuffer/pb_buffer.h>
43 #include "r600.h"
44 #include "r600d.h"
45 #include "r600_resource.h"
46 #include "r600_shader.h"
47 #include "r600_pipe.h"
48 #include "r600_state_inlines.h"
49
50 /*
51  * pipe_context
52  */
53 static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx)
54 {
55         struct r600_fence *fence = NULL;
56
57         if (!ctx->fences.bo) {
58                 /* Create the shared buffer object */
59                 ctx->fences.bo = r600_bo(ctx->radeon, 4096, 0, 0, 0);
60                 if (!ctx->fences.bo) {
61                         R600_ERR("r600: failed to create bo for fence objects\n");
62                         return NULL;
63                 }
64                 ctx->fences.data = r600_bo_map(ctx->radeon, ctx->fences.bo, PB_USAGE_UNSYNCHRONIZED, NULL);
65         }
66
67         if (!LIST_IS_EMPTY(&ctx->fences.pool)) {
68                 struct r600_fence *entry;
69
70                 /* Try to find a freed fence that has been signalled */
71                 LIST_FOR_EACH_ENTRY(entry, &ctx->fences.pool, head) {
72                         if (ctx->fences.data[entry->index] != 0) {
73                                 LIST_DELINIT(&entry->head);
74                                 fence = entry;
75                                 break;
76                         }
77                 }
78         }
79
80         if (!fence) {
81                 /* Allocate a new fence */
82                 struct r600_fence_block *block;
83                 unsigned index;
84
85                 if ((ctx->fences.next_index + 1) >= 1024) {
86                         R600_ERR("r600: too many concurrent fences\n");
87                         return NULL;
88                 }
89
90                 index = ctx->fences.next_index++;
91
92                 if (!(index % FENCE_BLOCK_SIZE)) {
93                         /* Allocate a new block */
94                         block = CALLOC_STRUCT(r600_fence_block);
95                         if (block == NULL)
96                                 return NULL;
97
98                         LIST_ADD(&block->head, &ctx->fences.blocks);
99                 } else {
100                         block = LIST_ENTRY(struct r600_fence_block, ctx->fences.blocks.next, head);
101                 }
102
103                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
104                 fence->ctx = ctx;
105                 fence->index = index;
106         }
107
108         pipe_reference_init(&fence->reference, 1);
109
110         ctx->fences.data[fence->index] = 0;
111         r600_context_emit_fence(&ctx->ctx, ctx->fences.bo, fence->index, 1);
112         return fence;
113 }
114
115 static void r600_flush(struct pipe_context *ctx,
116                         struct pipe_fence_handle **fence)
117 {
118         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
119         struct r600_fence **rfence = (struct r600_fence**)fence;
120
121 #if 0
122         static int dc = 0;
123         char dname[256];
124 #endif
125
126         if (rfence)
127                 *rfence = r600_create_fence(rctx);
128
129 #if 0
130         sprintf(dname, "gallium-%08d.bof", dc);
131         if (dc < 20) {
132                 r600_context_dump_bof(&rctx->ctx, dname);
133                 R600_ERR("dumped %s\n", dname);
134         }
135         dc++;
136 #endif
137         r600_context_flush(&rctx->ctx);
138 }
139
140 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
141 {
142         pipe_mutex_lock(rscreen->mutex_num_contexts);
143         if (diff > 0) {
144                 rscreen->num_contexts++;
145
146                 if (rscreen->num_contexts > 1)
147                         util_slab_set_thread_safety(&rscreen->pool_buffers,
148                                                     UTIL_SLAB_MULTITHREADED);
149         } else {
150                 rscreen->num_contexts--;
151
152                 if (rscreen->num_contexts <= 1)
153                         util_slab_set_thread_safety(&rscreen->pool_buffers,
154                                                     UTIL_SLAB_SINGLETHREADED);
155         }
156         pipe_mutex_unlock(rscreen->mutex_num_contexts);
157 }
158
159 static void r600_destroy_context(struct pipe_context *context)
160 {
161         struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
162
163         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
164         util_unreference_framebuffer_state(&rctx->framebuffer);
165
166         r600_context_fini(&rctx->ctx);
167
168         util_blitter_destroy(rctx->blitter);
169
170         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
171                 free(rctx->states[i]);
172         }
173
174         u_vbuf_destroy(rctx->vbuf_mgr);
175         util_slab_destroy(&rctx->pool_transfers);
176
177         if (rctx->fences.bo) {
178                 struct r600_fence_block *entry, *tmp;
179
180                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rctx->fences.blocks, head) {
181                         LIST_DEL(&entry->head);
182                         FREE(entry);
183                 }
184
185                 r600_bo_unmap(rctx->radeon, rctx->fences.bo);
186                 r600_bo_reference(rctx->radeon, &rctx->fences.bo, NULL);
187         }
188
189         r600_update_num_contexts(rctx->screen, -1);
190
191         FREE(rctx);
192 }
193
194 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
195 {
196         struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
197         struct r600_screen* rscreen = (struct r600_screen *)screen;
198         enum chip_class class;
199
200         if (rctx == NULL)
201                 return NULL;
202
203         r600_update_num_contexts(rscreen, 1);
204
205         rctx->context.winsys = rscreen->screen.winsys;
206         rctx->context.screen = screen;
207         rctx->context.priv = priv;
208         rctx->context.destroy = r600_destroy_context;
209         rctx->context.flush = r600_flush;
210
211         /* Easy accessing of screen/winsys. */
212         rctx->screen = rscreen;
213         rctx->radeon = rscreen->radeon;
214         rctx->family = r600_get_family(rctx->radeon);
215
216         rctx->fences.bo = NULL;
217         rctx->fences.data = NULL;
218         rctx->fences.next_index = 0;
219         LIST_INITHEAD(&rctx->fences.pool);
220         LIST_INITHEAD(&rctx->fences.blocks);
221
222         r600_init_blit_functions(rctx);
223         r600_init_query_functions(rctx);
224         r600_init_context_resource_functions(rctx);
225         r600_init_surface_functions(rctx);
226         rctx->context.draw_vbo = r600_draw_vbo;
227
228         switch (r600_get_family(rctx->radeon)) {
229         case CHIP_R600:
230         case CHIP_RV610:
231         case CHIP_RV630:
232         case CHIP_RV670:
233         case CHIP_RV620:
234         case CHIP_RV635:
235         case CHIP_RS780:
236         case CHIP_RS880:
237         case CHIP_RV770:
238         case CHIP_RV730:
239         case CHIP_RV710:
240         case CHIP_RV740:
241                 r600_init_state_functions(rctx);
242                 if (r600_context_init(&rctx->ctx, rctx->radeon)) {
243                         r600_destroy_context(&rctx->context);
244                         return NULL;
245                 }
246                 r600_init_config(rctx);
247                 break;
248         case CHIP_CEDAR:
249         case CHIP_REDWOOD:
250         case CHIP_JUNIPER:
251         case CHIP_CYPRESS:
252         case CHIP_HEMLOCK:
253         case CHIP_PALM:
254         case CHIP_SUMO:
255         case CHIP_SUMO2:
256         case CHIP_BARTS:
257         case CHIP_TURKS:
258         case CHIP_CAICOS:
259         case CHIP_CAYMAN:
260                 evergreen_init_state_functions(rctx);
261                 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
262                         r600_destroy_context(&rctx->context);
263                         return NULL;
264                 }
265                 evergreen_init_config(rctx);
266                 break;
267         default:
268                 R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
269                 r600_destroy_context(&rctx->context);
270                 return NULL;
271         }
272
273         util_slab_create(&rctx->pool_transfers,
274                          sizeof(struct pipe_transfer), 64,
275                          UTIL_SLAB_SINGLETHREADED);
276
277         rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256,
278                                            PIPE_BIND_VERTEX_BUFFER |
279                                            PIPE_BIND_INDEX_BUFFER |
280                                            PIPE_BIND_CONSTANT_BUFFER,
281                                            U_VERTEX_FETCH_DWORD_ALIGNED);
282         if (!rctx->vbuf_mgr) {
283                 r600_destroy_context(&rctx->context);
284                 return NULL;
285         }
286
287         rctx->blitter = util_blitter_create(&rctx->context);
288         if (rctx->blitter == NULL) {
289                 r600_destroy_context(&rctx->context);
290                 return NULL;
291         }
292
293         class = r600_get_family_class(rctx->radeon);
294         if (class == R600 || class == R700)
295                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
296         else
297                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
298
299         return &rctx->context;
300 }
301
302 /*
303  * pipe_screen
304  */
305 static const char* r600_get_vendor(struct pipe_screen* pscreen)
306 {
307         return "X.Org";
308 }
309
310 static const char *r600_get_family_name(enum radeon_family family)
311 {
312         switch(family) {
313         case CHIP_R600: return "AMD R600";
314         case CHIP_RV610: return "AMD RV610";
315         case CHIP_RV630: return "AMD RV630";
316         case CHIP_RV670: return "AMD RV670";
317         case CHIP_RV620: return "AMD RV620";
318         case CHIP_RV635: return "AMD RV635";
319         case CHIP_RS780: return "AMD RS780";
320         case CHIP_RS880: return "AMD RS880";
321         case CHIP_RV770: return "AMD RV770";
322         case CHIP_RV730: return "AMD RV730";
323         case CHIP_RV710: return "AMD RV710";
324         case CHIP_RV740: return "AMD RV740";
325         case CHIP_CEDAR: return "AMD CEDAR";
326         case CHIP_REDWOOD: return "AMD REDWOOD";
327         case CHIP_JUNIPER: return "AMD JUNIPER";
328         case CHIP_CYPRESS: return "AMD CYPRESS";
329         case CHIP_HEMLOCK: return "AMD HEMLOCK";
330         case CHIP_PALM: return "AMD PALM";
331         case CHIP_SUMO: return "AMD SUMO";
332         case CHIP_SUMO2: return "AMD SUMO2";
333         case CHIP_BARTS: return "AMD BARTS";
334         case CHIP_TURKS: return "AMD TURKS";
335         case CHIP_CAICOS: return "AMD CAICOS";
336         case CHIP_CAYMAN: return "AMD CAYMAN";
337         default: return "AMD unknown";
338         }
339 }
340
341 static const char* r600_get_name(struct pipe_screen* pscreen)
342 {
343         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
344         enum radeon_family family = r600_get_family(rscreen->radeon);
345
346         return r600_get_family_name(family);
347 }
348
349 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
350 {
351         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
352         enum radeon_family family = r600_get_family(rscreen->radeon);
353
354         switch (param) {
355         /* Supported features (boolean caps). */
356         case PIPE_CAP_NPOT_TEXTURES:
357         case PIPE_CAP_TWO_SIDED_STENCIL:
358         case PIPE_CAP_GLSL:
359         case PIPE_CAP_DUAL_SOURCE_BLEND:
360         case PIPE_CAP_ANISOTROPIC_FILTER:
361         case PIPE_CAP_POINT_SPRITE:
362         case PIPE_CAP_OCCLUSION_QUERY:
363         case PIPE_CAP_TEXTURE_SHADOW_MAP:
364         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
365         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
366         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
367         case PIPE_CAP_TEXTURE_SWIZZLE:
368         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
369         case PIPE_CAP_DEPTH_CLAMP:
370         case PIPE_CAP_SHADER_STENCIL_EXPORT:
371         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
372         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
373         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
374         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
375         case PIPE_CAP_SM3:
376         case PIPE_CAP_SEAMLESS_CUBE_MAP:
377         case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
378                 return 1;
379
380         /* Supported except the original R600. */
381         case PIPE_CAP_INDEP_BLEND_ENABLE:
382         case PIPE_CAP_INDEP_BLEND_FUNC:
383                 /* R600 doesn't support per-MRT blends */
384                 return family == CHIP_R600 ? 0 : 1;
385
386         /* Supported on Evergreen. */
387         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
388                 return family >= CHIP_CEDAR ? 1 : 0;
389
390         /* Unsupported features. */
391         case PIPE_CAP_STREAM_OUTPUT:
392         case PIPE_CAP_PRIMITIVE_RESTART:
393         case PIPE_CAP_TGSI_INSTANCEID:
394         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
395         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
396                 return 0;
397
398         case PIPE_CAP_ARRAY_TEXTURES:
399                 /* fix once the CS checker upstream is fixed */
400                 return debug_get_bool_option("R600_ARRAY_TEXTURE", FALSE);
401
402         /* Texturing. */
403         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
404         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
405         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
406                 if (family >= CHIP_CEDAR)
407                         return 15;
408                 else
409                         return 14;
410         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
411         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
412                 return 16;
413         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
414                 return 32;
415
416         /* Render targets. */
417         case PIPE_CAP_MAX_RENDER_TARGETS:
418                 /* FIXME some r6xx are buggy and can only do 4 */
419                 return 8;
420
421         /* Timer queries, present when the clock frequency is non zero. */
422         case PIPE_CAP_TIMER_QUERY:
423                 return r600_get_clock_crystal_freq(rscreen->radeon) != 0;
424
425         default:
426                 R600_ERR("r600: unknown param %d\n", param);
427                 return 0;
428         }
429 }
430
431 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
432 {
433         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
434         enum radeon_family family = r600_get_family(rscreen->radeon);
435
436         switch (param) {
437         case PIPE_CAP_MAX_LINE_WIDTH:
438         case PIPE_CAP_MAX_LINE_WIDTH_AA:
439         case PIPE_CAP_MAX_POINT_WIDTH:
440         case PIPE_CAP_MAX_POINT_WIDTH_AA:
441                 if (family >= CHIP_CEDAR)
442                         return 16384.0f;
443                 else
444                         return 8192.0f;
445         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
446                 return 16.0f;
447         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
448                 return 16.0f;
449         default:
450                 R600_ERR("r600: unsupported paramf %d\n", param);
451                 return 0.0f;
452         }
453 }
454
455 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
456 {
457         switch(shader)
458         {
459         case PIPE_SHADER_FRAGMENT:
460         case PIPE_SHADER_VERTEX:
461                 break;
462         case PIPE_SHADER_GEOMETRY:
463                 /* TODO: support and enable geometry programs */
464                 return 0;
465         default:
466                 /* TODO: support tessellation on Evergreen */
467                 return 0;
468         }
469
470         /* TODO: all these should be fixed, since r600 surely supports much more! */
471         switch (param) {
472         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
473         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
474         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
475         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
476                 return 16384;
477         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
478                 return 8; /* FIXME */
479         case PIPE_SHADER_CAP_MAX_INPUTS:
480                 if(shader == PIPE_SHADER_FRAGMENT)
481                         return 34;
482                 else
483                         return 32;
484         case PIPE_SHADER_CAP_MAX_TEMPS:
485                 return 256; /* Max native temporaries. */
486         case PIPE_SHADER_CAP_MAX_ADDRS:
487                 /* FIXME Isn't this equal to TEMPS? */
488                 return 1; /* Max native address registers */
489         case PIPE_SHADER_CAP_MAX_CONSTS:
490                 return R600_MAX_CONST_BUFFER_SIZE;
491         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
492                 return R600_MAX_CONST_BUFFERS;
493         case PIPE_SHADER_CAP_MAX_PREDS:
494                 return 0; /* FIXME */
495         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
496                 return 1;
497         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
498         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
499         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
500         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
501                 return 1;
502         case PIPE_SHADER_CAP_SUBROUTINES:
503                 return 0;
504         default:
505                 return 0;
506         }
507 }
508
509 static boolean r600_is_format_supported(struct pipe_screen* screen,
510                                         enum pipe_format format,
511                                         enum pipe_texture_target target,
512                                         unsigned sample_count,
513                                         unsigned usage)
514 {
515         unsigned retval = 0;
516         if (target >= PIPE_MAX_TEXTURE_TYPES) {
517                 R600_ERR("r600: unsupported texture type %d\n", target);
518                 return FALSE;
519         }
520
521         if (!util_format_is_supported(format, usage))
522                 return FALSE;
523
524         /* Multisample */
525         if (sample_count > 1)
526                 return FALSE;
527
528         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
529             r600_is_sampler_format_supported(screen, format)) {
530                 retval |= PIPE_BIND_SAMPLER_VIEW;
531         }
532
533         if ((usage & (PIPE_BIND_RENDER_TARGET |
534                         PIPE_BIND_DISPLAY_TARGET |
535                         PIPE_BIND_SCANOUT |
536                         PIPE_BIND_SHARED)) &&
537                         r600_is_colorbuffer_format_supported(format)) {
538                 retval |= usage &
539                         (PIPE_BIND_RENDER_TARGET |
540                          PIPE_BIND_DISPLAY_TARGET |
541                          PIPE_BIND_SCANOUT |
542                          PIPE_BIND_SHARED);
543         }
544
545         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
546             r600_is_zs_format_supported(format)) {
547                 retval |= PIPE_BIND_DEPTH_STENCIL;
548         }
549
550         if (usage & PIPE_BIND_VERTEX_BUFFER) {
551                 struct r600_screen *rscreen = (struct r600_screen *)screen;
552                 enum radeon_family family = r600_get_family(rscreen->radeon);
553
554                 if (r600_is_vertex_format_supported(format, family)) {
555                         retval |= PIPE_BIND_VERTEX_BUFFER;
556                 }
557         }
558
559         if (usage & PIPE_BIND_TRANSFER_READ)
560                 retval |= PIPE_BIND_TRANSFER_READ;
561         if (usage & PIPE_BIND_TRANSFER_WRITE)
562                 retval |= PIPE_BIND_TRANSFER_WRITE;
563
564         return retval == usage;
565 }
566
567 static void r600_destroy_screen(struct pipe_screen* pscreen)
568 {
569         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
570
571         if (rscreen == NULL)
572                 return;
573
574         radeon_decref(rscreen->radeon);
575
576         util_slab_destroy(&rscreen->pool_buffers);
577         pipe_mutex_destroy(rscreen->mutex_num_contexts);
578         FREE(rscreen);
579 }
580
581 static void r600_fence_reference(struct pipe_screen *pscreen,
582                                  struct pipe_fence_handle **ptr,
583                                  struct pipe_fence_handle *fence)
584 {
585         struct r600_fence **oldf = (struct r600_fence**)ptr;
586         struct r600_fence *newf = (struct r600_fence*)fence;
587
588         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
589                 struct r600_pipe_context *ctx = (*oldf)->ctx;
590                 LIST_ADDTAIL(&(*oldf)->head, &ctx->fences.pool);
591         }
592
593         *ptr = fence;
594 }
595
596 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
597                                     struct pipe_fence_handle *fence)
598 {
599         struct r600_fence *rfence = (struct r600_fence*)fence;
600         struct r600_pipe_context *ctx = rfence->ctx;
601
602         return ctx->fences.data[rfence->index];
603 }
604
605 static boolean r600_fence_finish(struct pipe_screen *pscreen,
606                                  struct pipe_fence_handle *fence,
607                                  uint64_t timeout)
608 {
609         struct r600_fence *rfence = (struct r600_fence*)fence;
610         struct r600_pipe_context *ctx = rfence->ctx;
611         int64_t start_time = 0;
612         unsigned spins = 0;
613
614         if (timeout != PIPE_TIMEOUT_INFINITE) {
615                 start_time = os_time_get();
616
617                 /* Convert to microseconds. */
618                 timeout /= 1000;
619         }
620
621         while (ctx->fences.data[rfence->index] == 0) {
622                 if (++spins % 256)
623                         continue;
624 #ifdef PIPE_OS_UNIX
625                 sched_yield();
626 #else
627                 os_time_sleep(10);
628 #endif
629                 if (timeout != PIPE_TIMEOUT_INFINITE &&
630                     os_time_get() - start_time >= timeout) {
631                         return FALSE;
632                 }
633         }
634
635         return TRUE;
636 }
637
638 struct pipe_screen *r600_screen_create(struct radeon *radeon)
639 {
640         struct r600_screen *rscreen;
641
642         rscreen = CALLOC_STRUCT(r600_screen);
643         if (rscreen == NULL) {
644                 return NULL;
645         }
646
647         rscreen->radeon = radeon;
648         rscreen->screen.winsys = (struct pipe_winsys*)radeon;
649         rscreen->screen.destroy = r600_destroy_screen;
650         rscreen->screen.get_name = r600_get_name;
651         rscreen->screen.get_vendor = r600_get_vendor;
652         rscreen->screen.get_param = r600_get_param;
653         rscreen->screen.get_shader_param = r600_get_shader_param;
654         rscreen->screen.get_paramf = r600_get_paramf;
655         rscreen->screen.is_format_supported = r600_is_format_supported;
656         rscreen->screen.context_create = r600_create_context;
657         rscreen->screen.fence_reference = r600_fence_reference;
658         rscreen->screen.fence_signalled = r600_fence_signalled;
659         rscreen->screen.fence_finish = r600_fence_finish;
660         r600_init_screen_resource_functions(&rscreen->screen);
661
662         rscreen->tiling_info = r600_get_tiling_info(radeon);
663         util_format_s3tc_init();
664
665         util_slab_create(&rscreen->pool_buffers,
666                          sizeof(struct r600_resource_buffer), 64,
667                          UTIL_SLAB_SINGLETHREADED);
668
669         pipe_mutex_init(rscreen->mutex_num_contexts);
670
671         return &rscreen->screen;
672 }