2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_pipe.h"
24 #include "r600_public.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_blitter.h"
29 #include "util/u_format_s3tc.h"
30 #include "util/u_simple_shaders.h"
31 #include "util/u_upload_mgr.h"
32 #include "vl/vl_decoder.h"
33 #include "vl/vl_video_buffer.h"
34 #include "os/os_time.h"
39 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
41 struct r600_screen *rscreen = rctx->screen;
42 struct r600_fence *fence = NULL;
44 pipe_mutex_lock(rscreen->fences.mutex);
46 if (!rscreen->fences.bo) {
47 /* Create the shared buffer object */
48 rscreen->fences.bo = (struct r600_resource*)
49 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
50 PIPE_USAGE_STAGING, 4096);
51 if (!rscreen->fences.bo) {
52 R600_ERR("r600: failed to create bo for fence objects\n");
55 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
57 PIPE_TRANSFER_READ_WRITE);
60 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
61 struct r600_fence *entry;
63 /* Try to find a freed fence that has been signalled */
64 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
65 if (rscreen->fences.data[entry->index] != 0) {
66 LIST_DELINIT(&entry->head);
74 /* Allocate a new fence */
75 struct r600_fence_block *block;
78 if ((rscreen->fences.next_index + 1) >= 1024) {
79 R600_ERR("r600: too many concurrent fences\n");
83 index = rscreen->fences.next_index++;
85 if (!(index % FENCE_BLOCK_SIZE)) {
86 /* Allocate a new block */
87 block = CALLOC_STRUCT(r600_fence_block);
91 LIST_ADD(&block->head, &rscreen->fences.blocks);
93 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
96 fence = &block->fences[index % FENCE_BLOCK_SIZE];
100 pipe_reference_init(&fence->reference, 1);
102 rscreen->fences.data[fence->index] = 0;
103 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
105 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
106 fence->sleep_bo = (struct r600_resource*)
107 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
108 PIPE_USAGE_STAGING, 1);
109 /* Add the fence as a dummy relocation. */
110 r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
113 pipe_mutex_unlock(rscreen->fences.mutex);
118 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
121 struct r600_context *rctx = (struct r600_context *)ctx;
122 struct r600_fence **rfence = (struct r600_fence**)fence;
123 struct pipe_query *render_cond = NULL;
124 unsigned render_cond_mode = 0;
127 *rfence = r600_create_fence(rctx);
129 /* Disable render condition. */
130 if (rctx->current_render_cond) {
131 render_cond = rctx->current_render_cond;
132 render_cond_mode = rctx->current_render_cond_mode;
133 ctx->render_condition(ctx, NULL, 0);
136 r600_context_flush(rctx, flags);
138 /* Re-enable render condition. */
140 ctx->render_condition(ctx, render_cond, render_cond_mode);
144 static void r600_flush_from_st(struct pipe_context *ctx,
145 struct pipe_fence_handle **fence)
147 r600_flush(ctx, fence, 0);
150 static void r600_flush_from_winsys(void *ctx, unsigned flags)
152 r600_flush((struct pipe_context*)ctx, NULL, flags);
155 static void r600_destroy_context(struct pipe_context *context)
157 struct r600_context *rctx = (struct r600_context *)context;
159 if (rctx->dummy_pixel_shader) {
160 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
162 if (rctx->custom_dsa_flush) {
163 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
165 util_unreference_framebuffer_state(&rctx->framebuffer);
167 r600_context_fini(rctx);
170 util_blitter_destroy(rctx->blitter);
172 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
173 free(rctx->states[i]);
176 if (rctx->uploader) {
177 u_upload_destroy(rctx->uploader);
179 util_slab_destroy(&rctx->pool_transfers);
181 r600_release_command_buffer(&rctx->start_cs_cmd);
184 rctx->ws->cs_destroy(rctx->cs);
191 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
193 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
194 struct r600_screen* rscreen = (struct r600_screen *)screen;
199 util_slab_create(&rctx->pool_transfers,
200 sizeof(struct pipe_transfer), 64,
201 UTIL_SLAB_SINGLETHREADED);
203 rctx->context.screen = screen;
204 rctx->context.priv = priv;
205 rctx->context.destroy = r600_destroy_context;
206 rctx->context.flush = r600_flush_from_st;
208 /* Easy accessing of screen/winsys. */
209 rctx->screen = rscreen;
210 rctx->ws = rscreen->ws;
211 rctx->family = rscreen->family;
212 rctx->chip_class = rscreen->chip_class;
214 LIST_INITHEAD(&rctx->dirty_states);
215 LIST_INITHEAD(&rctx->active_timer_queries);
216 LIST_INITHEAD(&rctx->active_nontimer_queries);
217 LIST_INITHEAD(&rctx->dirty);
218 LIST_INITHEAD(&rctx->enable_list);
220 rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range));
224 r600_init_blit_functions(rctx);
225 r600_init_query_functions(rctx);
226 r600_init_context_resource_functions(rctx);
227 r600_init_surface_functions(rctx);
228 rctx->context.draw_vbo = r600_draw_vbo;
230 rctx->context.create_video_decoder = vl_create_decoder;
231 rctx->context.create_video_buffer = vl_video_buffer_create;
233 r600_init_common_atoms(rctx);
235 switch (rctx->chip_class) {
238 r600_init_state_functions(rctx);
239 r600_init_atom_start_cs(rctx);
240 if (r600_context_init(rctx))
242 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
243 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 ||
244 rctx->family == CHIP_RV620 ||
245 rctx->family == CHIP_RS780 ||
246 rctx->family == CHIP_RS880 ||
247 rctx->family == CHIP_RV710);
251 evergreen_init_state_functions(rctx);
252 evergreen_init_atom_start_cs(rctx);
253 evergreen_init_atom_start_compute_cs(rctx);
254 if (evergreen_context_init(rctx))
256 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
257 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
258 rctx->family == CHIP_PALM ||
259 rctx->family == CHIP_SUMO ||
260 rctx->family == CHIP_SUMO2 ||
261 rctx->family == CHIP_CAICOS ||
262 rctx->family == CHIP_CAYMAN ||
263 rctx->family == CHIP_ARUBA);
266 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
270 rctx->cs = rctx->ws->cs_create(rctx->ws);
271 rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
272 r600_emit_atom(rctx, &rctx->start_cs_cmd.atom);
274 rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
275 PIPE_BIND_INDEX_BUFFER |
276 PIPE_BIND_CONSTANT_BUFFER);
280 rctx->blitter = util_blitter_create(&rctx->context);
281 if (rctx->blitter == NULL)
284 r600_get_backend_mask(rctx); /* this emits commands and must be last */
286 if (rctx->chip_class == R600)
287 r600_set_max_scissor(rctx);
289 rctx->dummy_pixel_shader =
290 util_make_fragment_cloneinput_shader(&rctx->context, 0,
291 TGSI_SEMANTIC_GENERIC,
292 TGSI_INTERPOLATE_CONSTANT);
293 rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
295 return &rctx->context;
298 r600_destroy_context(&rctx->context);
305 static const char* r600_get_vendor(struct pipe_screen* pscreen)
310 static const char *r600_get_family_name(enum radeon_family family)
313 case CHIP_R600: return "AMD R600";
314 case CHIP_RV610: return "AMD RV610";
315 case CHIP_RV630: return "AMD RV630";
316 case CHIP_RV670: return "AMD RV670";
317 case CHIP_RV620: return "AMD RV620";
318 case CHIP_RV635: return "AMD RV635";
319 case CHIP_RS780: return "AMD RS780";
320 case CHIP_RS880: return "AMD RS880";
321 case CHIP_RV770: return "AMD RV770";
322 case CHIP_RV730: return "AMD RV730";
323 case CHIP_RV710: return "AMD RV710";
324 case CHIP_RV740: return "AMD RV740";
325 case CHIP_CEDAR: return "AMD CEDAR";
326 case CHIP_REDWOOD: return "AMD REDWOOD";
327 case CHIP_JUNIPER: return "AMD JUNIPER";
328 case CHIP_CYPRESS: return "AMD CYPRESS";
329 case CHIP_HEMLOCK: return "AMD HEMLOCK";
330 case CHIP_PALM: return "AMD PALM";
331 case CHIP_SUMO: return "AMD SUMO";
332 case CHIP_SUMO2: return "AMD SUMO2";
333 case CHIP_BARTS: return "AMD BARTS";
334 case CHIP_TURKS: return "AMD TURKS";
335 case CHIP_CAICOS: return "AMD CAICOS";
336 case CHIP_CAYMAN: return "AMD CAYMAN";
337 case CHIP_ARUBA: return "AMD ARUBA";
338 default: return "AMD unknown";
342 static const char* r600_get_name(struct pipe_screen* pscreen)
344 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
346 return r600_get_family_name(rscreen->family);
349 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
351 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
352 enum radeon_family family = rscreen->family;
355 /* Supported features (boolean caps). */
356 case PIPE_CAP_NPOT_TEXTURES:
357 case PIPE_CAP_TWO_SIDED_STENCIL:
358 case PIPE_CAP_ANISOTROPIC_FILTER:
359 case PIPE_CAP_POINT_SPRITE:
360 case PIPE_CAP_OCCLUSION_QUERY:
361 case PIPE_CAP_TEXTURE_SHADOW_MAP:
362 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
363 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
364 case PIPE_CAP_TEXTURE_SWIZZLE:
365 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
366 case PIPE_CAP_DEPTH_CLIP_DISABLE:
367 case PIPE_CAP_SHADER_STENCIL_EXPORT:
368 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
369 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
370 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
371 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
373 case PIPE_CAP_SEAMLESS_CUBE_MAP:
374 case PIPE_CAP_PRIMITIVE_RESTART:
375 case PIPE_CAP_CONDITIONAL_RENDER:
376 case PIPE_CAP_TEXTURE_BARRIER:
377 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
378 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
379 case PIPE_CAP_TGSI_INSTANCEID:
380 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
381 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
382 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
383 case PIPE_CAP_USER_INDEX_BUFFERS:
384 case PIPE_CAP_USER_CONSTANT_BUFFERS:
385 case PIPE_CAP_COMPUTE:
386 case PIPE_CAP_START_INSTANCE:
389 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
392 case PIPE_CAP_GLSL_FEATURE_LEVEL:
395 /* Supported except the original R600. */
396 case PIPE_CAP_INDEP_BLEND_ENABLE:
397 case PIPE_CAP_INDEP_BLEND_FUNC:
398 /* R600 doesn't support per-MRT blends */
399 return family == CHIP_R600 ? 0 : 1;
401 /* Supported on Evergreen. */
402 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
403 return family >= CHIP_CEDAR ? 1 : 0;
405 /* Unsupported features. */
406 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
407 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
408 case PIPE_CAP_SCALED_RESOLVE:
409 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
410 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
411 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
412 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
413 case PIPE_CAP_USER_VERTEX_BUFFERS:
414 case PIPE_CAP_QUERY_TIMESTAMP:
418 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
419 return rscreen->has_streamout ? 4 : 0;
420 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
421 return rscreen->has_streamout ? 1 : 0;
422 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
423 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
427 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
428 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
429 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
430 if (family >= CHIP_CEDAR)
434 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
435 return rscreen->info.drm_minor >= 9 ?
436 (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
437 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
440 /* Render targets. */
441 case PIPE_CAP_MAX_RENDER_TARGETS:
442 /* XXX some r6xx are buggy and can only do 4 */
445 /* Timer queries, present when the clock frequency is non zero. */
446 case PIPE_CAP_TIMER_QUERY:
447 return rscreen->info.r600_clock_crystal_freq != 0;
449 case PIPE_CAP_MIN_TEXEL_OFFSET:
452 case PIPE_CAP_MAX_TEXEL_OFFSET:
455 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
456 return family < CHIP_CEDAR ? 1 : 0;
461 static float r600_get_paramf(struct pipe_screen* pscreen,
462 enum pipe_capf param)
464 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
465 enum radeon_family family = rscreen->family;
468 case PIPE_CAPF_MAX_LINE_WIDTH:
469 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
470 case PIPE_CAPF_MAX_POINT_WIDTH:
471 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
472 if (family >= CHIP_CEDAR)
476 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
478 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
480 case PIPE_CAPF_GUARD_BAND_LEFT:
481 case PIPE_CAPF_GUARD_BAND_TOP:
482 case PIPE_CAPF_GUARD_BAND_RIGHT:
483 case PIPE_CAPF_GUARD_BAND_BOTTOM:
489 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
493 case PIPE_SHADER_FRAGMENT:
494 case PIPE_SHADER_VERTEX:
495 case PIPE_SHADER_COMPUTE:
497 case PIPE_SHADER_GEOMETRY:
498 /* XXX: support and enable geometry programs */
501 /* XXX: support tessellation on Evergreen */
505 /* XXX: all these should be fixed, since r600 surely supports much more! */
507 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
508 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
509 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
510 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
512 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
514 case PIPE_SHADER_CAP_MAX_INPUTS:
515 if(shader == PIPE_SHADER_FRAGMENT)
519 case PIPE_SHADER_CAP_MAX_TEMPS:
520 return 256; /* Max native temporaries. */
521 case PIPE_SHADER_CAP_MAX_ADDRS:
522 /* XXX Isn't this equal to TEMPS? */
523 return 1; /* Max native address registers */
524 case PIPE_SHADER_CAP_MAX_CONSTS:
525 return R600_MAX_CONST_BUFFER_SIZE;
526 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
527 return R600_MAX_CONST_BUFFERS-1;
528 case PIPE_SHADER_CAP_MAX_PREDS:
529 return 0; /* nothing uses this */
530 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
532 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
533 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
534 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
535 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
537 case PIPE_SHADER_CAP_SUBROUTINES:
539 case PIPE_SHADER_CAP_INTEGERS:
541 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
543 case PIPE_SHADER_CAP_PREFERRED_IR:
544 if (shader == PIPE_SHADER_COMPUTE) {
545 return PIPE_SHADER_IR_LLVM;
547 return PIPE_SHADER_IR_TGSI;
553 static int r600_get_video_param(struct pipe_screen *screen,
554 enum pipe_video_profile profile,
555 enum pipe_video_cap param)
558 case PIPE_VIDEO_CAP_SUPPORTED:
559 return vl_profile_supported(screen, profile);
560 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
562 case PIPE_VIDEO_CAP_MAX_WIDTH:
563 case PIPE_VIDEO_CAP_MAX_HEIGHT:
564 return vl_video_buffer_max_size(screen);
565 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
566 return PIPE_FORMAT_NV12;
567 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
569 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
571 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
578 static int r600_get_compute_param(struct pipe_screen *screen,
579 enum pipe_compute_cap param,
582 //TODO: select these params by asic
584 case PIPE_COMPUTE_CAP_IR_TARGET:
586 strcpy(ret, "r600--");
588 return 7 * sizeof(char);
590 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
592 uint64_t * grid_dimension = ret;
593 grid_dimension[0] = 3;
595 return 1 * sizeof(uint64_t);
597 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
599 uint64_t * grid_size = ret;
600 grid_size[0] = 65535;
601 grid_size[1] = 65535;
604 return 3 * sizeof(uint64_t) ;
606 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
608 uint64_t * block_size = ret;
613 return 3 * sizeof(uint64_t);
615 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
617 uint64_t * max_threads_per_block = ret;
618 *max_threads_per_block = 256;
620 return sizeof(uint64_t);
622 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
624 uint64_t * max_global_size = ret;
625 /* XXX: This is 64kb for now until we get the
626 * compute memory pool working correctly.
628 *max_global_size = 1024 * 16 * 4;
630 return sizeof(uint64_t);
632 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
634 uint64_t * max_input_size = ret;
635 *max_input_size = 1024;
637 return sizeof(uint64_t);
639 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
641 uint64_t * max_local_size = ret;
642 /* XXX: This is what the proprietary driver reports, we
643 * may want to use a different value. */
644 *max_local_size = 32768;
646 return sizeof(uint64_t);
649 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
654 static void r600_destroy_screen(struct pipe_screen* pscreen)
656 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
661 if (rscreen->global_pool) {
662 compute_memory_pool_delete(rscreen->global_pool);
665 if (rscreen->fences.bo) {
666 struct r600_fence_block *entry, *tmp;
668 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
669 LIST_DEL(&entry->head);
673 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
674 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
676 pipe_mutex_destroy(rscreen->fences.mutex);
678 rscreen->ws->destroy(rscreen->ws);
682 static void r600_fence_reference(struct pipe_screen *pscreen,
683 struct pipe_fence_handle **ptr,
684 struct pipe_fence_handle *fence)
686 struct r600_fence **oldf = (struct r600_fence**)ptr;
687 struct r600_fence *newf = (struct r600_fence*)fence;
689 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
690 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
691 pipe_mutex_lock(rscreen->fences.mutex);
692 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
693 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
694 pipe_mutex_unlock(rscreen->fences.mutex);
700 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
701 struct pipe_fence_handle *fence)
703 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
704 struct r600_fence *rfence = (struct r600_fence*)fence;
706 return rscreen->fences.data[rfence->index];
709 static boolean r600_fence_finish(struct pipe_screen *pscreen,
710 struct pipe_fence_handle *fence,
713 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
714 struct r600_fence *rfence = (struct r600_fence*)fence;
715 int64_t start_time = 0;
718 if (timeout != PIPE_TIMEOUT_INFINITE) {
719 start_time = os_time_get();
721 /* Convert to microseconds. */
725 while (rscreen->fences.data[rfence->index] == 0) {
726 /* Special-case infinite timeout - wait for the dummy BO to become idle */
727 if (timeout == PIPE_TIMEOUT_INFINITE) {
728 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
732 /* The dummy BO will be busy until the CS including the fence has completed, or
733 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
734 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
744 if (timeout != PIPE_TIMEOUT_INFINITE &&
745 os_time_get() - start_time >= timeout) {
750 return rscreen->fences.data[rfence->index] != 0;
753 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
755 switch ((tiling_config & 0xe) >> 1) {
757 rscreen->tiling_info.num_channels = 1;
760 rscreen->tiling_info.num_channels = 2;
763 rscreen->tiling_info.num_channels = 4;
766 rscreen->tiling_info.num_channels = 8;
772 switch ((tiling_config & 0x30) >> 4) {
774 rscreen->tiling_info.num_banks = 4;
777 rscreen->tiling_info.num_banks = 8;
783 switch ((tiling_config & 0xc0) >> 6) {
785 rscreen->tiling_info.group_bytes = 256;
788 rscreen->tiling_info.group_bytes = 512;
796 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
798 switch (tiling_config & 0xf) {
800 rscreen->tiling_info.num_channels = 1;
803 rscreen->tiling_info.num_channels = 2;
806 rscreen->tiling_info.num_channels = 4;
809 rscreen->tiling_info.num_channels = 8;
815 switch ((tiling_config & 0xf0) >> 4) {
817 rscreen->tiling_info.num_banks = 4;
820 rscreen->tiling_info.num_banks = 8;
823 rscreen->tiling_info.num_banks = 16;
829 switch ((tiling_config & 0xf00) >> 8) {
831 rscreen->tiling_info.group_bytes = 256;
834 rscreen->tiling_info.group_bytes = 512;
842 static int r600_init_tiling(struct r600_screen *rscreen)
844 uint32_t tiling_config = rscreen->info.r600_tiling_config;
846 /* set default group bytes, overridden by tiling info ioctl */
847 if (rscreen->chip_class <= R700) {
848 rscreen->tiling_info.group_bytes = 256;
850 rscreen->tiling_info.group_bytes = 512;
856 if (rscreen->chip_class <= R700) {
857 return r600_interpret_tiling(rscreen, tiling_config);
859 return evergreen_interpret_tiling(rscreen, tiling_config);
863 static unsigned radeon_family_from_device(unsigned device)
866 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
867 #include "pci_ids/r600_pci_ids.h"
874 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
876 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
878 if (rscreen == NULL) {
883 ws->query_info(ws, &rscreen->info);
885 rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
886 if (rscreen->family == CHIP_UNKNOWN) {
887 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
893 if (rscreen->family >= CHIP_CAYMAN) {
894 rscreen->chip_class = CAYMAN;
895 } else if (rscreen->family >= CHIP_CEDAR) {
896 rscreen->chip_class = EVERGREEN;
897 } else if (rscreen->family >= CHIP_RV770) {
898 rscreen->chip_class = R700;
900 rscreen->chip_class = R600;
903 /* Figure out streamout kernel support. */
904 switch (rscreen->chip_class) {
907 rscreen->has_streamout = rscreen->info.drm_minor >= 13;
910 rscreen->has_streamout = rscreen->info.drm_minor >= 17;
914 rscreen->has_streamout = debug_get_bool_option("R600_STREAMOUT", FALSE);
917 if (r600_init_tiling(rscreen)) {
922 rscreen->screen.destroy = r600_destroy_screen;
923 rscreen->screen.get_name = r600_get_name;
924 rscreen->screen.get_vendor = r600_get_vendor;
925 rscreen->screen.get_param = r600_get_param;
926 rscreen->screen.get_shader_param = r600_get_shader_param;
927 rscreen->screen.get_paramf = r600_get_paramf;
928 rscreen->screen.get_video_param = r600_get_video_param;
929 rscreen->screen.get_compute_param = r600_get_compute_param;
931 if (rscreen->chip_class >= EVERGREEN) {
932 rscreen->screen.is_format_supported = evergreen_is_format_supported;
934 rscreen->screen.is_format_supported = r600_is_format_supported;
936 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
937 rscreen->screen.context_create = r600_create_context;
938 rscreen->screen.fence_reference = r600_fence_reference;
939 rscreen->screen.fence_signalled = r600_fence_signalled;
940 rscreen->screen.fence_finish = r600_fence_finish;
941 r600_init_screen_resource_functions(&rscreen->screen);
943 util_format_s3tc_init();
945 rscreen->fences.bo = NULL;
946 rscreen->fences.data = NULL;
947 rscreen->fences.next_index = 0;
948 LIST_INITHEAD(&rscreen->fences.pool);
949 LIST_INITHEAD(&rscreen->fences.blocks);
950 pipe_mutex_init(rscreen->fences.mutex);
952 rscreen->use_surface_alloc = debug_get_bool_option("R600_SURF", TRUE);
954 rscreen->global_pool = compute_memory_pool_new(rscreen);
956 return &rscreen->screen;