src/gallium/drivers/r600/r600_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #include "r600_hw_context_priv.h"
  27 #include "r600d.h"
  28 #include "util/u_memory.h"
  29 #include <errno.h>
  30
  31 /* Get backends mask */
  32 void r600_get_backend_mask(struct r600_context *ctx)
  33 {
  34         struct radeon_winsys_cs *cs = ctx->cs;
  35         struct r600_resource *buffer;
  36         uint32_t *results;
  37         unsigned num_backends = ctx->screen->info.r600_num_backends;
  38         unsigned i, mask = 0;
  39         uint64_t va;
  40
  41         /* if backend_map query is supported by the kernel */
  42         if (ctx->screen->info.r600_backend_map_valid) {
  43                 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
  44                 unsigned backend_map = ctx->screen->info.r600_backend_map;
  45                 unsigned item_width, item_mask;
  46
  47                 if (ctx->chip_class >= EVERGREEN) {
  48                         item_width = 4;
  49                         item_mask = 0x7;
  50                 } else {
  51                         item_width = 2;
  52                         item_mask = 0x3;
  53                 }
  54
  55                 while(num_tile_pipes--) {
  56                         i = backend_map & item_mask;
  57                         mask |= (1<<i);
  58                         backend_map >>= item_width;
  59                 }
  60                 if (mask != 0) {
  61                         ctx->backend_mask = mask;
  62                         return;
  63                 }
  64         }
  65
  66         /* otherwise backup path for older kernels */
  67
  68         /* create buffer for event data */
  69         buffer = (struct r600_resource*)
  70                 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
  71                                    PIPE_USAGE_STAGING, ctx->max_db*16);
  72         if (!buffer)
  73                 goto err;
  74
  75         va = r600_resource_va(&ctx->screen->screen, (void*)buffer);
  76
  77         /* initialize buffer with zeroes */
  78         results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE);
  79         if (results) {
  80                 memset(results, 0, ctx->max_db * 4 * 4);
  81                 ctx->ws->buffer_unmap(buffer->cs_buf);
  82
  83                 /* emit EVENT_WRITE for ZPASS_DONE */
  84                 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
  85                 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
  86                 cs->buf[cs->cdw++] = va;
  87                 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
  88
  89                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
  90                 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
  91
  92                 /* analyze results */
  93                 results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_READ);
  94                 if (results) {
  95                         for(i = 0; i < ctx->max_db; i++) {
  96                                 /* at least highest bit will be set if backend is used */
  97                                 if (results[i*4 + 1])
  98                                         mask |= (1<<i);
  99                         }
 100                         ctx->ws->buffer_unmap(buffer->cs_buf);
 101                 }
 102         }
 103
 104         pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
 105
 106         if (mask != 0) {
 107                 ctx->backend_mask = mask;
 108                 return;
 109         }
 110
 111 err:
 112         /* fallback to old method - set num_backends lower bits to 1 */
 113         ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
 114         return;
 115 }
 116
 117 void r600_context_ps_partial_flush(struct r600_context *ctx)
 118 {
 119         struct radeon_winsys_cs *cs = ctx->cs;
 120
 121         if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
 122                 return;
 123
 124         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
 125         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
 126
 127         ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
 128 }
 129
 130 static void r600_init_block(struct r600_context *ctx,
 131                             struct r600_block *block,
 132                             const struct r600_reg *reg, int index, int nreg,
 133                             unsigned opcode, unsigned offset_base)
 134 {
 135         int i = index;
 136         int j, n = nreg;
 137
 138         /* initialize block */
 139         block->flags = 0;
 140         block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
 141         block->start_offset = reg[i].offset;
 142         block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
 143         block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
 144         block->reg = &block->pm4[block->pm4_ndwords];
 145         block->pm4_ndwords += n;
 146         block->nreg = n;
 147         block->nreg_dirty = n;
 148         LIST_INITHEAD(&block->list);
 149         LIST_INITHEAD(&block->enable_list);
 150
 151         for (j = 0; j < n; j++) {
 152                 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
 153                         block->flags |= REG_FLAG_DIRTY_ALWAYS;
 154                 }
 155                 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
 156                         if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
 157                                 block->status |= R600_BLOCK_STATUS_ENABLED;
 158                                 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
 159                                 LIST_ADDTAIL(&block->list,&ctx->dirty);
 160                         }
 161                 }
 162                 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
 163                         block->flags |= REG_FLAG_FLUSH_CHANGE;
 164                 }
 165
 166                 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
 167                         block->nbo++;
 168                         assert(block->nbo < R600_BLOCK_MAX_BO);
 169                         block->pm4_bo_index[j] = block->nbo;
 170                         block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
 171                         block->pm4[block->pm4_ndwords++] = 0x00000000;
 172                         block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
 173                 }
 174                 if ((ctx->family > CHIP_R600) &&
 175                     (ctx->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
 176                         block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
 177                         block->pm4[block->pm4_ndwords++] = reg[i+j].sbu_flags;
 178                 }
 179         }
 180         /* check that we stay in limit */
 181         assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
 182 }
 183
 184 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
 185                            unsigned opcode, unsigned offset_base)
 186 {
 187         struct r600_block *block;
 188         struct r600_range *range;
 189         int offset;
 190
 191         for (unsigned i = 0, n = 0; i < nreg; i += n) {
 192                 /* ignore new block balise */
 193                 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
 194                         n = 1;
 195                         continue;
 196                 }
 197
 198                 /* ignore regs not on R600 on R600 */
 199                 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->family == CHIP_R600) {
 200                         n = 1;
 201                         continue;
 202                 }
 203
 204                 /* register that need relocation are in their own group */
 205                 /* find number of consecutive registers */
 206                 n = 0;
 207                 offset = reg[i].offset;
 208                 while (reg[i + n].offset == offset) {
 209                         n++;
 210                         offset += 4;
 211                         if ((n + i) >= nreg)
 212                                 break;
 213                         if (n >= (R600_BLOCK_MAX_REG - 2))
 214                                 break;
 215                 }
 216
 217                 /* allocate new block */
 218                 block = calloc(1, sizeof(struct r600_block));
 219                 if (block == NULL) {
 220                         return -ENOMEM;
 221                 }
 222                 ctx->nblocks++;
 223                 for (int j = 0; j < n; j++) {
 224                         range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
 225                         /* create block table if it doesn't exist */
 226                         if (!range->blocks)
 227                                 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
 228                         if (!range->blocks)
 229                                 return -1;
 230
 231                         range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
 232                 }
 233
 234                 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
 235
 236         }
 237         return 0;
 238 }
 239
 240 /* R600/R700 configuration */
 241 static const struct r600_reg r600_config_reg_list[] = {
 242         {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
 243         {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
 244         {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
 245 };
 246
 247 static const struct r600_reg r600_ctl_const_list[] = {
 248         {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
 249 };
 250
 251 static const struct r600_reg r600_context_reg_list[] = {
 252         {R_028A4C_PA_SC_MODE_CNTL, 0, 0},
 253         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 254         {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0)},
 255         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 256         {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
 257         {R_028060_CB_COLOR0_SIZE, 0, 0},
 258         {R_028080_CB_COLOR0_VIEW, 0, 0},
 259         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 260         {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0},
 261         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 262         {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0},
 263         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 264         {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1)},
 265         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 266         {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
 267         {R_028064_CB_COLOR1_SIZE, 0, 0},
 268         {R_028084_CB_COLOR1_VIEW, 0, 0},
 269         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 270         {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0},
 271         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 272         {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0},
 273         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 274         {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2)},
 275         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 276         {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
 277         {R_028068_CB_COLOR2_SIZE, 0, 0},
 278         {R_028088_CB_COLOR2_VIEW, 0, 0},
 279         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 280         {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0},
 281         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 282         {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0},
 283         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 284         {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3)},
 285         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 286         {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
 287         {R_02806C_CB_COLOR3_SIZE, 0, 0},
 288         {R_02808C_CB_COLOR3_VIEW, 0, 0},
 289         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 290         {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0},
 291         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 292         {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0},
 293         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 294         {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4)},
 295         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 296         {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
 297         {R_028070_CB_COLOR4_SIZE, 0, 0},
 298         {R_028090_CB_COLOR4_VIEW, 0, 0},
 299         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 300         {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0},
 301         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 302         {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0},
 303         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 304         {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5)},
 305         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 306         {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
 307         {R_028074_CB_COLOR5_SIZE, 0, 0},
 308         {R_028094_CB_COLOR5_VIEW, 0, 0},
 309         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 310         {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0},
 311         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 312         {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0},
 313         {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6)},
 314         {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
 315         {R_028078_CB_COLOR6_SIZE, 0, 0},
 316         {R_028098_CB_COLOR6_VIEW, 0, 0},
 317         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 318         {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0},
 319         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 320         {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0},
 321         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 322         {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7)},
 323         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 324         {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
 325         {R_02807C_CB_COLOR7_SIZE, 0, 0},
 326         {R_02809C_CB_COLOR7_VIEW, 0, 0},
 327         {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0},
 328         {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0},
 329         {R_028120_CB_CLEAR_RED, 0, 0},
 330         {R_028124_CB_CLEAR_GREEN, 0, 0},
 331         {R_028128_CB_CLEAR_BLUE, 0, 0},
 332         {R_02812C_CB_CLEAR_ALPHA, 0, 0},
 333         {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
 334         {R_028414_CB_BLEND_RED, 0, 0},
 335         {R_028418_CB_BLEND_GREEN, 0, 0},
 336         {R_02841C_CB_BLEND_BLUE, 0, 0},
 337         {R_028420_CB_BLEND_ALPHA, 0, 0},
 338         {R_028424_CB_FOG_RED, 0, 0},
 339         {R_028428_CB_FOG_GREEN, 0, 0},
 340         {R_02842C_CB_FOG_BLUE, 0, 0},
 341         {R_028430_DB_STENCILREFMASK, 0, 0},
 342         {R_028434_DB_STENCILREFMASK_BF, 0, 0},
 343         {R_028438_SX_ALPHA_REF, 0, 0},
 344         {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0},
 345         {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0},
 346         {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0},
 347         {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0},
 348         {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0},
 349         {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0},
 350         {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0},
 351         {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0},
 352         {R_0287A0_CB_SHADER_CONTROL, 0, 0},
 353         {R_028800_DB_DEPTH_CONTROL, 0, 0},
 354         {R_028804_CB_BLEND_CONTROL, 0, 0},
 355         {R_02880C_DB_SHADER_CONTROL, 0, 0},
 356         {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH},
 357         {R_028000_DB_DEPTH_SIZE, 0, 0},
 358         {R_028004_DB_DEPTH_VIEW, 0, 0},
 359         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 360         {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0},
 361         {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
 362         {R_028D24_DB_HTILE_SURFACE, 0, 0},
 363         {R_028D34_DB_PREFETCH_LIMIT, 0, 0},
 364         {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
 365         {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
 366         {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
 367         {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
 368         {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
 369         {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
 370         {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
 371         {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
 372         {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
 373         {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
 374         {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
 375         {R_028810_PA_CL_CLIP_CNTL, 0, 0},
 376         {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
 377         {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
 378         {R_028A00_PA_SU_POINT_SIZE, 0, 0},
 379         {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
 380         {R_028A08_PA_SU_LINE_CNTL, 0, 0},
 381         {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
 382         {R_028C08_PA_SU_VTX_CNTL, 0, 0},
 383         {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
 384         {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
 385         {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
 386         {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
 387         {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
 388         {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
 389         {R_028E20_PA_CL_UCP0_X, 0, 0},
 390         {R_028E24_PA_CL_UCP0_Y, 0, 0},
 391         {R_028E28_PA_CL_UCP0_Z, 0, 0},
 392         {R_028E2C_PA_CL_UCP0_W, 0, 0},
 393         {R_028E30_PA_CL_UCP1_X, 0, 0},
 394         {R_028E34_PA_CL_UCP1_Y, 0, 0},
 395         {R_028E38_PA_CL_UCP1_Z, 0, 0},
 396         {R_028E3C_PA_CL_UCP1_W, 0, 0},
 397         {R_028E40_PA_CL_UCP2_X, 0, 0},
 398         {R_028E44_PA_CL_UCP2_Y, 0, 0},
 399         {R_028E48_PA_CL_UCP2_Z, 0, 0},
 400         {R_028E4C_PA_CL_UCP2_W, 0, 0},
 401         {R_028E50_PA_CL_UCP3_X, 0, 0},
 402         {R_028E54_PA_CL_UCP3_Y, 0, 0},
 403         {R_028E58_PA_CL_UCP3_Z, 0, 0},
 404         {R_028E5C_PA_CL_UCP3_W, 0, 0},
 405         {R_028E60_PA_CL_UCP4_X, 0, 0},
 406         {R_028E64_PA_CL_UCP4_Y, 0, 0},
 407         {R_028E68_PA_CL_UCP4_Z, 0, 0},
 408         {R_028E6C_PA_CL_UCP4_W, 0, 0},
 409         {R_028E70_PA_CL_UCP5_X, 0, 0},
 410         {R_028E74_PA_CL_UCP5_Y, 0, 0},
 411         {R_028E78_PA_CL_UCP5_Z, 0, 0},
 412         {R_028E7C_PA_CL_UCP5_W, 0, 0},
 413         {R_028350_SX_MISC, 0, 0},
 414         {R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
 415         {R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
 416         {R_028388_SQ_VTX_SEMANTIC_2, 0, 0},
 417         {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0},
 418         {R_028390_SQ_VTX_SEMANTIC_4, 0, 0},
 419         {R_028394_SQ_VTX_SEMANTIC_5, 0, 0},
 420         {R_028398_SQ_VTX_SEMANTIC_6, 0, 0},
 421         {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0},
 422         {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0},
 423         {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0},
 424         {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0},
 425         {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0},
 426         {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0},
 427         {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0},
 428         {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0},
 429         {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0},
 430         {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0},
 431         {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0},
 432         {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0},
 433         {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0},
 434         {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0},
 435         {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0},
 436         {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0},
 437         {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0},
 438         {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0},
 439         {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0},
 440         {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0},
 441         {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0},
 442         {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0},
 443         {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0},
 444         {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0},
 445         {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0},
 446         {R_028614_SPI_VS_OUT_ID_0, 0, 0},
 447         {R_028618_SPI_VS_OUT_ID_1, 0, 0},
 448         {R_02861C_SPI_VS_OUT_ID_2, 0, 0},
 449         {R_028620_SPI_VS_OUT_ID_3, 0, 0},
 450         {R_028624_SPI_VS_OUT_ID_4, 0, 0},
 451         {R_028628_SPI_VS_OUT_ID_5, 0, 0},
 452         {R_02862C_SPI_VS_OUT_ID_6, 0, 0},
 453         {R_028630_SPI_VS_OUT_ID_7, 0, 0},
 454         {R_028634_SPI_VS_OUT_ID_8, 0, 0},
 455         {R_028638_SPI_VS_OUT_ID_9, 0, 0},
 456         {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
 457         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 458         {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
 459         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 460         {R_028868_SQ_PGM_RESOURCES_VS, 0, 0},
 461         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 462         {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
 463         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 464         {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0},
 465         {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0},
 466         {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
 467         {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
 468         {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
 469         {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
 470         {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
 471         {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
 472         {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
 473         {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
 474         {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
 475         {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
 476         {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
 477         {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
 478         {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
 479         {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
 480         {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
 481         {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
 482         {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
 483         {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
 484         {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
 485         {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
 486         {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
 487         {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
 488         {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
 489         {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
 490         {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
 491         {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
 492         {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
 493         {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
 494         {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
 495         {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
 496         {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
 497         {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
 498         {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
 499         {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
 500         {R_0286D8_SPI_INPUT_Z, 0, 0},
 501         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 502         {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
 503         {GROUP_FORCE_NEW_BLOCK, 0, 0},
 504         {R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
 505         {R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
 506         {R_028408_VGT_INDX_OFFSET, 0, 0},
 507         {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
 508         {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
 509 };
 510
 511 /* SHADER SAMPLER R600/R700/EG/CM */
 512 int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset)
 513 {
 514         struct r600_reg r600_shader_sampler[] = {
 515                 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0},
 516                 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0},
 517                 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0},
 518         };
 519         unsigned nreg = Elements(r600_shader_sampler);
 520
 521         for (int i = 0; i < nreg; i++) {
 522                 r600_shader_sampler[i].offset += offset;
 523         }
 524         return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
 525 }
 526
 527 /* SHADER SAMPLER BORDER R600/R700 */
 528 static int r600_state_sampler_border_init(struct r600_context *ctx, uint32_t offset)
 529 {
 530         struct r600_reg r600_shader_sampler_border[] = {
 531                 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0},
 532                 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0},
 533                 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
 534                 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0},
 535         };
 536         unsigned nreg = Elements(r600_shader_sampler_border);
 537
 538         for (int i = 0; i < nreg; i++) {
 539                 r600_shader_sampler_border[i].offset += offset;
 540         }
 541         return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
 542 }
 543
 544 static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset)
 545 {
 546         unsigned nreg = 32;
 547         struct r600_reg r600_loop_consts[32];
 548         int i;
 549
 550         for (i = 0; i < nreg; i++) {
 551                 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
 552                 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
 553                 r600_loop_consts[i].sbu_flags = 0;
 554         }
 555         return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
 556 }
 557
 558 /* initialize */
 559 void r600_context_fini(struct r600_context *ctx)
 560 {
 561         struct r600_block *block;
 562         struct r600_range *range;
 563
 564         if (ctx->range) {
 565                 for (int i = 0; i < NUM_RANGES; i++) {
 566                         if (!ctx->range[i].blocks)
 567                                 continue;
 568                         for (int j = 0; j < (1 << HASH_SHIFT); j++) {
 569                                 block = ctx->range[i].blocks[j];
 570                                 if (block) {
 571                                         for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
 572                                                 range = &ctx->range[CTX_RANGE_ID(offset)];
 573                                                 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
 574                                         }
 575                                         for (int k = 1; k <= block->nbo; k++) {
 576                                                 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
 577                                         }
 578                                         free(block);
 579                                 }
 580                         }
 581                         free(ctx->range[i].blocks);
 582                 }
 583         }
 584         free(ctx->blocks);
 585 }
 586
 587 int r600_setup_block_table(struct r600_context *ctx)
 588 {
 589         /* setup block table */
 590         int c = 0;
 591         ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
 592         if (!ctx->blocks)
 593                 return -ENOMEM;
 594         for (int i = 0; i < NUM_RANGES; i++) {
 595                 if (!ctx->range[i].blocks)
 596                         continue;
 597                 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
 598                         if (!ctx->range[i].blocks[j])
 599                                 continue;
 600
 601                         add = 1;
 602                         for (int k = 0; k < c; k++) {
 603                                 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
 604                                         add = 0;
 605                                         break;
 606                                 }
 607                         }
 608                         if (add) {
 609                                 assert(c < ctx->nblocks);
 610                                 ctx->blocks[c++] = ctx->range[i].blocks[j];
 611                                 j += (ctx->range[i].blocks[j]->nreg) - 1;
 612                         }
 613                 }
 614         }
 615         return 0;
 616 }
 617
 618 int r600_context_init(struct r600_context *ctx)
 619 {
 620         int r;
 621
 622         /* add blocks */
 623         r = r600_context_add_block(ctx, r600_config_reg_list,
 624                                    Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
 625         if (r)
 626                 goto out_err;
 627         r = r600_context_add_block(ctx, r600_context_reg_list,
 628                                    Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
 629         if (r)
 630                 goto out_err;
 631         r = r600_context_add_block(ctx, r600_ctl_const_list,
 632                                    Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
 633         if (r)
 634                 goto out_err;
 635
 636         /* PS SAMPLER BORDER */
 637         for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
 638                 r = r600_state_sampler_border_init(ctx, offset);
 639                 if (r)
 640                         goto out_err;
 641         }
 642
 643         /* VS SAMPLER BORDER */
 644         for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
 645                 r = r600_state_sampler_border_init(ctx, offset);
 646                 if (r)
 647                         goto out_err;
 648         }
 649         /* PS SAMPLER */
 650         for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
 651                 r = r600_state_sampler_init(ctx, offset);
 652                 if (r)
 653                         goto out_err;
 654         }
 655         /* VS SAMPLER */
 656         for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
 657                 r = r600_state_sampler_init(ctx, offset);
 658                 if (r)
 659                         goto out_err;
 660         }
 661
 662         /* PS loop const */
 663         r600_loop_const_init(ctx, 0);
 664         /* VS loop const */
 665         r600_loop_const_init(ctx, 32);
 666
 667         r = r600_setup_block_table(ctx);
 668         if (r)
 669                 goto out_err;
 670
 671         ctx->max_db = 4;
 672         return 0;
 673 out_err:
 674         r600_context_fini(ctx);
 675         return r;
 676 }
 677
 678 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
 679                         boolean count_draw_in)
 680 {
 681         struct r600_atom *state;
 682
 683         /* The number of dwords we already used in the CS so far. */
 684         num_dw += ctx->cs->cdw;
 685
 686         if (count_draw_in) {
 687                 /* The number of dwords all the dirty states would take. */
 688                 LIST_FOR_EACH_ENTRY(state, &ctx->dirty_states, head) {
 689                         num_dw += state->num_dw;
 690                 }
 691
 692                 num_dw += ctx->pm4_dirty_cdwords;
 693
 694                 /* The upper-bound of how much a draw command would take. */
 695                 num_dw += R600_MAX_DRAW_CS_DWORDS;
 696         }
 697
 698         /* Count in queries_suspend. */
 699         num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
 700         num_dw += ctx->num_cs_dw_timer_queries_suspend;
 701
 702         /* Count in streamout_end at the end of CS. */
 703         num_dw += ctx->num_cs_dw_streamout_end;
 704
 705         /* Count in render_condition(NULL) at the end of CS. */
 706         if (ctx->predicate_drawing) {
 707                 num_dw += 3;
 708         }
 709
 710         /* Count in framebuffer cache flushes at the end of CS. */
 711         num_dw += 7; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */
 712
 713         /* Save 16 dwords for the fence mechanism. */
 714         num_dw += 16;
 715
 716         /* Flush if there's not enough space. */
 717         if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
 718                 r600_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC);
 719         }
 720 }
 721
 722 void r600_context_dirty_block(struct r600_context *ctx,
 723                               struct r600_block *block,
 724                               int dirty, int index)
 725 {
 726         if ((index + 1) > block->nreg_dirty)
 727                 block->nreg_dirty = index + 1;
 728
 729         if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
 730                 block->status |= R600_BLOCK_STATUS_DIRTY;
 731                 ctx->pm4_dirty_cdwords += block->pm4_ndwords;
 732                 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
 733                         block->status |= R600_BLOCK_STATUS_ENABLED;
 734                         LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
 735                 }
 736                 LIST_ADDTAIL(&block->list,&ctx->dirty);
 737
 738                 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
 739                         r600_context_ps_partial_flush(ctx);
 740                 }
 741         }
 742 }
 743
 744 /**
 745  * If reg needs a reloc, this function will add it to its block's reloc list.
 746  * @return true if reg needs a reloc, false otherwise
 747  */
 748 static bool r600_reg_set_block_reloc(struct r600_pipe_reg *reg)
 749 {
 750         unsigned reloc_id;
 751
 752         if (!reg->block->pm4_bo_index[reg->id]) {
 753                 return false;
 754         }
 755         /* find relocation */
 756         reloc_id = reg->block->pm4_bo_index[reg->id];
 757         pipe_resource_reference(
 758                 (struct pipe_resource**)&reg->block->reloc[reloc_id].bo,
 759                 &reg->bo->b.b);
 760         reg->block->reloc[reloc_id].bo_usage = reg->bo_usage;
 761         return true;
 762 }
 763
 764 /**
 765  * This function will emit all the registers in state directly to the command
 766  * stream allowing you to bypass the r600_context dirty list.
 767  *
 768  * This is used for dispatching compute shaders to avoid mixing compute and
 769  * 3D states in the context's dirty list.
 770  *
 771  * @param pkt_flags Should be either 0 or RADEON_CP_PACKET3_COMPUTE_MODE.  This
 772  * value will be passed on to r600_context_block_emit_dirty an or'd against
 773  * the PKT3 headers.
 774  */
 775 void r600_context_pipe_state_emit(struct r600_context *ctx,
 776                           struct r600_pipe_state *state,
 777                           unsigned pkt_flags)
 778 {
 779         unsigned i;
 780
 781         /* Mark all blocks as dirty:
 782          * Since two registers can be in the same block, we need to make sure
 783          * we mark all the blocks dirty before we emit any of them.  If we were
 784          * to mark blocks dirty and emit them in the same loop, like this:
 785          *
 786          * foreach (reg in state->regs) {
 787          *     mark_dirty(reg->block)
 788          *     emit_block(reg->block)
 789          * }
 790          *
 791          * Then if we have two registers in this state that are in the same
 792          * block, we would end up emitting that block twice.
 793          */
 794         for (i = 0; i < state->nregs; i++) {
 795                 struct r600_pipe_reg *reg = &state->regs[i];
 796                 /* Mark all the registers in the block as dirty */
 797                 reg->block->nreg_dirty = reg->block->nreg;
 798                 reg->block->status |= R600_BLOCK_STATUS_DIRTY;
 799                 /* Update the reloc for this register if necessary. */
 800                 r600_reg_set_block_reloc(reg);
 801         }
 802
 803         /* Emit the registers writes */
 804         for (i = 0; i < state->nregs; i++) {
 805                 struct r600_pipe_reg *reg = &state->regs[i];
 806                 if (reg->block->status & R600_BLOCK_STATUS_DIRTY) {
 807                         r600_context_block_emit_dirty(ctx, reg->block, pkt_flags);
 808                 }
 809         }
 810 }
 811
 812 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
 813 {
 814         struct r600_block *block;
 815         int dirty;
 816         for (int i = 0; i < state->nregs; i++) {
 817                 unsigned id;
 818                 struct r600_pipe_reg *reg = &state->regs[i];
 819
 820                 block = reg->block;
 821                 id = reg->id;
 822
 823                 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
 824
 825                 if (reg->value != block->reg[id]) {
 826                         block->reg[id] = reg->value;
 827                         dirty |= R600_BLOCK_STATUS_DIRTY;
 828                 }
 829                 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
 830                         dirty |= R600_BLOCK_STATUS_DIRTY;
 831                 if (r600_reg_set_block_reloc(reg)) {
 832                         /* always force dirty for relocs for now */
 833                         dirty |= R600_BLOCK_STATUS_DIRTY;
 834                 }
 835
 836                 if (dirty)
 837                         r600_context_dirty_block(ctx, block, dirty, id);
 838         }
 839 }
 840
 841 void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
 842 {
 843         struct r600_range *range;
 844         struct r600_block *block;
 845         int i;
 846         int dirty;
 847
 848         range = &ctx->range[CTX_RANGE_ID(offset)];
 849         block = range->blocks[CTX_BLOCK_ID(offset)];
 850         if (state == NULL) {
 851                 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
 852                 LIST_DELINIT(&block->list);
 853                 LIST_DELINIT(&block->enable_list);
 854                 return;
 855         }
 856         dirty = block->status & R600_BLOCK_STATUS_DIRTY;
 857
 858         for (i = 0; i < 3; i++) {
 859                 if (block->reg[i] != state->regs[i].value) {
 860                         block->reg[i] = state->regs[i].value;
 861                         dirty |= R600_BLOCK_STATUS_DIRTY;
 862                 }
 863         }
 864
 865         if (dirty)
 866                 r600_context_dirty_block(ctx, block, dirty, 2);
 867 }
 868
 869 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
 870 {
 871         struct r600_range *range;
 872         struct r600_block *block;
 873         int i;
 874         int dirty;
 875
 876         range = &ctx->range[CTX_RANGE_ID(offset)];
 877         block = range->blocks[CTX_BLOCK_ID(offset)];
 878         if (state == NULL) {
 879                 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
 880                 LIST_DELINIT(&block->list);
 881                 LIST_DELINIT(&block->enable_list);
 882                 return;
 883         }
 884         if (state->nregs <= 3) {
 885                 return;
 886         }
 887         dirty = block->status & R600_BLOCK_STATUS_DIRTY;
 888         for (i = 0; i < 4; i++) {
 889                 if (block->reg[i] != state->regs[i + 3].value) {
 890                         block->reg[i] = state->regs[i + 3].value;
 891                         dirty |= R600_BLOCK_STATUS_DIRTY;
 892                 }
 893         }
 894
 895         /* We have to flush the shaders before we change the border color
 896          * registers, or previous draw commands that haven't completed yet
 897          * will end up using the new border color. */
 898         if (dirty & R600_BLOCK_STATUS_DIRTY)
 899                 r600_context_ps_partial_flush(ctx);
 900         if (dirty)
 901                 r600_context_dirty_block(ctx, block, dirty, 3);
 902 }
 903
 904 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
 905 {
 906         unsigned offset;
 907
 908         offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*id;
 909         r600_context_pipe_state_set_sampler(ctx, state, offset);
 910         offset = R_00A400_TD_PS_SAMPLER0_BORDER_RED + 16*id;
 911         r600_context_pipe_state_set_sampler_border(ctx, state, offset);
 912 }
 913
 914 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
 915 {
 916         unsigned offset;
 917
 918         offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*(id + 18);
 919         r600_context_pipe_state_set_sampler(ctx, state, offset);
 920         offset = R_00A600_TD_VS_SAMPLER0_BORDER_RED + 16*id;
 921         r600_context_pipe_state_set_sampler_border(ctx, state, offset);
 922 }
 923
 924 /**
 925  * @param pkt_flags should be set to RADEON_CP_PACKET3_COMPUTE_MODE if this
 926  * block will be used for compute shaders.
 927  */
 928 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block,
 929         unsigned pkt_flags)
 930 {
 931         struct radeon_winsys_cs *cs = ctx->cs;
 932         int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
 933         int cp_dwords = block->pm4_ndwords, start_dword = 0;
 934         int new_dwords = 0;
 935         int nbo = block->nbo;
 936
 937         if (block->nreg_dirty == 0 && optional) {
 938                 goto out;
 939         }
 940
 941         if (nbo) {
 942                 for (int j = 0; j < block->nreg; j++) {
 943                         if (block->pm4_bo_index[j]) {
 944                                 /* find relocation */
 945                                 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
 946                                 if (reloc->bo) {
 947                                         block->pm4[reloc->bo_pm4_index] =
 948                                                         r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
 949                                 } else {
 950                                         block->pm4[reloc->bo_pm4_index] = 0;
 951                                 }
 952                                 nbo--;
 953                                 if (nbo == 0)
 954                                         break;
 955
 956                         }
 957                 }
 958         }
 959
 960         optional &= (block->nreg_dirty != block->nreg);
 961         if (optional) {
 962                 new_dwords = block->nreg_dirty;
 963                 start_dword = cs->cdw;
 964                 cp_dwords = new_dwords + 2;
 965         }
 966         memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
 967
 968         /* We are applying the pkt_flags after copying the register block to
 969          * the the command stream, because it is possible this block will be
 970          * emitted with a different pkt_flags, and we don't want to store the
 971          * pkt_flags in the block.
 972          */
 973         cs->buf[cs->cdw] |= pkt_flags;
 974         cs->cdw += cp_dwords;
 975
 976         if (optional) {
 977                 uint32_t newword;
 978
 979                 newword = cs->buf[start_dword];
 980                 newword &= PKT_COUNT_C;
 981                 newword |= PKT_COUNT_S(new_dwords);
 982                 cs->buf[start_dword] = newword;
 983         }
 984 out:
 985         block->status ^= R600_BLOCK_STATUS_DIRTY;
 986         block->nreg_dirty = 0;
 987         LIST_DELINIT(&block->list);
 988 }
 989
 990 void r600_inval_shader_cache(struct r600_context *ctx)
 991 {
 992         ctx->surface_sync_cmd.flush_flags |= S_0085F0_SH_ACTION_ENA(1);
 993         r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
 994 }
 995
 996 void r600_inval_texture_cache(struct r600_context *ctx)
 997 {
 998         ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
 999         r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
1000 }
1001
1002 void r600_inval_vertex_cache(struct r600_context *ctx)
1003 {
1004         if (ctx->has_vertex_cache) {
1005                 ctx->surface_sync_cmd.flush_flags |= S_0085F0_VC_ACTION_ENA(1);
1006         } else {
1007                 /* Some GPUs don't have the vertex cache and must use the texture cache instead. */
1008                 ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
1009         }
1010         r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
1011 }
1012
1013 void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now)
1014 {
1015         if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1016                 return;
1017
1018         ctx->surface_sync_cmd.flush_flags |=
1019                 r600_get_cb_flush_flags(ctx) |
1020                 (ctx->framebuffer.zsbuf ? S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1) : 0);
1021
1022         if (flush_now) {
1023                 r600_emit_atom(ctx, &ctx->surface_sync_cmd.atom);
1024         } else {
1025                 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
1026         }
1027
1028         /* Also add a complete cache flush to work around broken flushing on R6xx. */
1029         if (ctx->chip_class == R600) {
1030                 if (flush_now) {
1031                         r600_emit_atom(ctx, &ctx->r6xx_flush_and_inv_cmd);
1032                 } else {
1033                         r600_atom_dirty(ctx, &ctx->r6xx_flush_and_inv_cmd);
1034                 }
1035         }
1036
1037         ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1038 }
1039
1040 void r600_context_flush(struct r600_context *ctx, unsigned flags)
1041 {
1042         struct radeon_winsys_cs *cs = ctx->cs;
1043         struct r600_block *enable_block = NULL;
1044         bool timer_queries_suspended = false;
1045         bool nontimer_queries_suspended = false;
1046         bool streamout_suspended = false;
1047
1048         if (cs->cdw == ctx->start_cs_cmd.atom.num_dw)
1049                 return;
1050
1051         /* suspend queries */
1052         if (ctx->num_cs_dw_timer_queries_suspend) {
1053                 r600_suspend_timer_queries(ctx);
1054                 timer_queries_suspended = true;
1055         }
1056         if (ctx->num_cs_dw_nontimer_queries_suspend) {
1057                 r600_suspend_nontimer_queries(ctx);
1058                 nontimer_queries_suspended = true;
1059         }
1060
1061         if (ctx->num_cs_dw_streamout_end) {
1062                 r600_context_streamout_end(ctx);
1063                 streamout_suspended = true;
1064         }
1065
1066         r600_flush_framebuffer(ctx, true);
1067
1068         /* partial flush is needed to avoid lockups on some chips with user fences */
1069         r600_context_ps_partial_flush(ctx);
1070
1071         /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
1072         if (ctx->chip_class <= R700) {
1073                 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
1074         }
1075
1076         /* force to keep tiling flags */
1077         flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
1078
1079         /* Flush the CS. */
1080         ctx->ws->cs_flush(ctx->cs, flags);
1081
1082         ctx->pm4_dirty_cdwords = 0;
1083         ctx->flags = 0;
1084
1085         /* Begin a new CS. */
1086         r600_emit_atom(ctx, &ctx->start_cs_cmd.atom);
1087
1088         /* Invalidate caches. */
1089         r600_inval_texture_cache(ctx);
1090         r600_flush_framebuffer(ctx, false);
1091
1092         /* Re-emit states. */
1093         r600_atom_dirty(ctx, &ctx->cb_misc_state.atom);
1094         r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
1095
1096         ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
1097         r600_vertex_buffers_dirty(ctx);
1098
1099         ctx->vs_constbuf_state.dirty_mask = ctx->vs_constbuf_state.enabled_mask;
1100         ctx->ps_constbuf_state.dirty_mask = ctx->ps_constbuf_state.enabled_mask;
1101         r600_constant_buffers_dirty(ctx, &ctx->vs_constbuf_state);
1102         r600_constant_buffers_dirty(ctx, &ctx->ps_constbuf_state);
1103
1104         ctx->vs_samplers.views.dirty_mask = ctx->vs_samplers.views.enabled_mask;
1105         ctx->ps_samplers.views.dirty_mask = ctx->ps_samplers.views.enabled_mask;
1106         r600_sampler_views_dirty(ctx, &ctx->vs_samplers.views);
1107         r600_sampler_views_dirty(ctx, &ctx->ps_samplers.views);
1108
1109         if (streamout_suspended) {
1110                 ctx->streamout_start = TRUE;
1111                 ctx->streamout_append_bitmask = ~0;
1112         }
1113
1114         /* resume queries */
1115         if (timer_queries_suspended) {
1116                 r600_resume_timer_queries(ctx);
1117         }
1118         if (nontimer_queries_suspended) {
1119                 r600_resume_nontimer_queries(ctx);
1120         }
1121
1122         /* set all valid group as dirty so they get reemited on
1123          * next draw command
1124          */
1125         LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
1126                 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
1127                         LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
1128                         enable_block->status |= R600_BLOCK_STATUS_DIRTY;
1129                 }
1130                 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
1131                 enable_block->nreg_dirty = enable_block->nreg;
1132         }
1133 }
1134
1135 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
1136 {
1137         struct radeon_winsys_cs *cs = ctx->cs;
1138         uint64_t va;
1139
1140         r600_need_cs_space(ctx, 10, FALSE);
1141
1142         va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
1143         va = va + (offset << 2);
1144
1145         r600_context_ps_partial_flush(ctx);
1146         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1147         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1148         cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;       /* ADDRESS_LO */
1149         /* DATA_SEL | INT_EN | ADDRESS_HI */
1150         cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
1151         cs->buf[cs->cdw++] = value;                   /* DATA_LO */
1152         cs->buf[cs->cdw++] = 0;                       /* DATA_HI */
1153         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1154         cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE);
1155 }
1156
1157 static void r600_flush_vgt_streamout(struct r600_context *ctx)
1158 {
1159         struct radeon_winsys_cs *cs = ctx->cs;
1160
1161         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
1162         cs->buf[cs->cdw++] = (R_008490_CP_STRMOUT_CNTL - R600_CONFIG_REG_OFFSET) >> 2;
1163         cs->buf[cs->cdw++] = 0;
1164
1165         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1166         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
1167
1168         cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
1169         cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
1170         cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2;  /* register */
1171         cs->buf[cs->cdw++] = 0;
1172         cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
1173         cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
1174         cs->buf[cs->cdw++] = 4; /* poll interval */
1175 }
1176
1177 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
1178 {
1179         struct radeon_winsys_cs *cs = ctx->cs;
1180
1181         if (buffer_enable_bit) {
1182                 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1183                 cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2;
1184                 cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(1);
1185
1186                 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1187                 cs->buf[cs->cdw++] = (R_028B20_VGT_STRMOUT_BUFFER_EN - R600_CONTEXT_REG_OFFSET) >> 2;
1188                 cs->buf[cs->cdw++] = buffer_enable_bit;
1189         } else {
1190                 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1191                 cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2;
1192                 cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(0);
1193         }
1194 }
1195
1196 void r600_context_streamout_begin(struct r600_context *ctx)
1197 {
1198         struct radeon_winsys_cs *cs = ctx->cs;
1199         struct r600_so_target **t = ctx->so_targets;
1200         unsigned *stride_in_dw = ctx->vs_shader->so.stride;
1201         unsigned buffer_en, i, update_flags = 0;
1202         uint64_t va;
1203
1204         buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
1205                     (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
1206                     (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
1207                     (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
1208
1209         ctx->num_cs_dw_streamout_end =
1210                 12 + /* flush_vgt_streamout */
1211                 util_bitcount(buffer_en) * 8 + /* STRMOUT_BUFFER_UPDATE */
1212                 3 /* set_streamout_enable(0) */;
1213
1214         r600_need_cs_space(ctx,
1215                            12 + /* flush_vgt_streamout */
1216                            6 + /* set_streamout_enable */
1217                            util_bitcount(buffer_en) * 7 + /* SET_CONTEXT_REG */
1218                            (ctx->chip_class == R700 ? util_bitcount(buffer_en) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
1219                            util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
1220                            util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
1221                            (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
1222                            ctx->num_cs_dw_streamout_end, TRUE);
1223
1224         if (ctx->chip_class >= EVERGREEN) {
1225                 evergreen_flush_vgt_streamout(ctx);
1226                 evergreen_set_streamout_enable(ctx, buffer_en);
1227         } else {
1228                 r600_flush_vgt_streamout(ctx);
1229                 r600_set_streamout_enable(ctx, buffer_en);
1230         }
1231
1232         for (i = 0; i < ctx->num_so_targets; i++) {
1233                 if (t[i]) {
1234                         t[i]->stride_in_dw = stride_in_dw[i];
1235                         t[i]->so_index = i;
1236                         va = r600_resource_va(&ctx->screen->screen,
1237                                               (void*)t[i]->b.buffer);
1238
1239                         update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
1240
1241                         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0);
1242                         cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 +
1243                                                         16*i - R600_CONTEXT_REG_OFFSET) >> 2;
1244                         cs->buf[cs->cdw++] = (t[i]->b.buffer_offset +
1245                                                         t[i]->b.buffer_size) >> 2; /* BUFFER_SIZE (in DW) */
1246                         cs->buf[cs->cdw++] = stride_in_dw[i];              /* VTX_STRIDE (in DW) */
1247                         cs->buf[cs->cdw++] = va >> 8;                      /* BUFFER_BASE */
1248
1249                         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1250                         cs->buf[cs->cdw++] =
1251                                 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
1252                                                       RADEON_USAGE_WRITE);
1253
1254                         /* R7xx requires this packet after updating BUFFER_BASE.
1255                          * Without this, R7xx locks up. */
1256                         if (ctx->chip_class == R700) {
1257                                 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
1258                                 cs->buf[cs->cdw++] = i;
1259                                 cs->buf[cs->cdw++] = va >> 8;
1260
1261                                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1262                                 cs->buf[cs->cdw++] =
1263                                         r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
1264                                                               RADEON_USAGE_WRITE);
1265                         }
1266
1267                         if (ctx->streamout_append_bitmask & (1 << i)) {
1268                                 va = r600_resource_va(&ctx->screen->screen,
1269                                                       (void*)t[i]->filled_size);
1270                                 /* Append. */
1271                                 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1272                                 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1273                                                                STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
1274                                 cs->buf[cs->cdw++] = 0; /* unused */
1275                                 cs->buf[cs->cdw++] = 0; /* unused */
1276                                 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1277                                 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1278
1279                                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1280                                 cs->buf[cs->cdw++] =
1281                                         r600_context_bo_reloc(ctx,  t[i]->filled_size,
1282                                                               RADEON_USAGE_READ);
1283                         } else {
1284                                 /* Start from the beginning. */
1285                                 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1286                                 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1287                                                                STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
1288                                 cs->buf[cs->cdw++] = 0; /* unused */
1289                                 cs->buf[cs->cdw++] = 0; /* unused */
1290                                 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
1291                                 cs->buf[cs->cdw++] = 0; /* unused */
1292                         }
1293                 }
1294         }
1295
1296         if (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770) {
1297                 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
1298                 cs->buf[cs->cdw++] = update_flags;
1299         }
1300 }
1301
1302 void r600_context_streamout_end(struct r600_context *ctx)
1303 {
1304         struct radeon_winsys_cs *cs = ctx->cs;
1305         struct r600_so_target **t = ctx->so_targets;
1306         unsigned i, flush_flags = 0;
1307         uint64_t va;
1308
1309         if (ctx->chip_class >= EVERGREEN) {
1310                 evergreen_flush_vgt_streamout(ctx);
1311         } else {
1312                 r600_flush_vgt_streamout(ctx);
1313         }
1314
1315         for (i = 0; i < ctx->num_so_targets; i++) {
1316                 if (t[i]) {
1317                         va = r600_resource_va(&ctx->screen->screen,
1318                                               (void*)t[i]->filled_size);
1319                         cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1320                         cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1321                                                        STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
1322                                                        STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
1323                         cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;     /* dst address lo */
1324                         cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
1325                         cs->buf[cs->cdw++] = 0; /* unused */
1326                         cs->buf[cs->cdw++] = 0; /* unused */
1327
1328                         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1329                         cs->buf[cs->cdw++] =
1330                                 r600_context_bo_reloc(ctx,  t[i]->filled_size,
1331                                                       RADEON_USAGE_WRITE);
1332
1333                         flush_flags |= S_0085F0_SO0_DEST_BASE_ENA(1) << i;
1334                 }
1335         }
1336
1337         if (ctx->chip_class >= EVERGREEN) {
1338                 evergreen_set_streamout_enable(ctx, 0);
1339         } else {
1340                 r600_set_streamout_enable(ctx, 0);
1341         }
1342
1343         /* This is needed to fix cache flushes on r600. */
1344         if (ctx->chip_class == R600) {
1345                 if (ctx->family == CHIP_RV670 ||
1346                     ctx->family == CHIP_RS780 ||
1347                     ctx->family == CHIP_RS880) {
1348                         flush_flags |= S_0085F0_DEST_BASE_0_ENA(1);
1349                 }
1350
1351                 r600_atom_dirty(ctx, &ctx->r6xx_flush_and_inv_cmd);
1352         }
1353
1354         /* Flush streamout caches. */
1355         ctx->surface_sync_cmd.flush_flags |=
1356                 S_0085F0_SMX_ACTION_ENA(1) | flush_flags;
1357         r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
1358
1359         ctx->num_cs_dw_streamout_end = 0;
1360
1361 #if 0
1362         for (i = 0; i < ctx->num_so_targets; i++) {
1363                 if (!t[i])
1364                         continue;
1365
1366                 uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->buf, ctx->cs, RADEON_USAGE_READ);
1367                 printf("FILLED_SIZE%i: %u\n", i, *ptr);
1368                 ctx->ws->buffer_unmap(t[i]->filled_size->buf);
1369         }
1370 #endif
1371 }
1372
1373 void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t)
1374 {
1375         struct radeon_winsys_cs *cs = ctx->cs;
1376         uint64_t va = r600_resource_va(&ctx->screen->screen,
1377                                        (void*)t->filled_size);
1378
1379         r600_need_cs_space(ctx, 14 + 21, TRUE);
1380
1381         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1382         cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - R600_CONTEXT_REG_OFFSET) >> 2;
1383         cs->buf[cs->cdw++] = 0;
1384
1385         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1386         cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - R600_CONTEXT_REG_OFFSET) >> 2;
1387         cs->buf[cs->cdw++] = t->stride_in_dw;
1388
1389         cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1390         cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1391         cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;     /* src address lo */
1392         cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1393         cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1394         cs->buf[cs->cdw++] = 0; /* unused */
1395
1396         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1397         cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ);
1398 }