2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
32 #include <util/u_double_list.h>
33 #include <util/u_inlines.h>
34 #include <pipe/p_compiler.h>
36 #define RADEON_CTX_MAX_PM4 (64 * 1024 / 4)
38 #define R600_ERR(fmt, args...) \
39 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
85 struct r600_tiling_info {
86 unsigned num_channels;
91 enum radeon_family r600_get_family(struct radeon *rw);
92 enum chip_class r600_get_family_class(struct radeon *radeon);
93 struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon);
94 unsigned r600_get_clock_crystal_freq(struct radeon *radeon);
95 unsigned r600_get_minor_version(struct radeon *radeon);
96 unsigned r600_get_num_backends(struct radeon *radeon);
97 unsigned r600_get_num_tile_pipes(struct radeon *radeon);
98 unsigned r600_get_backend_map(struct radeon *radeon);
102 struct r600_bo *r600_bo(struct radeon *radeon,
103 unsigned size, unsigned alignment,
104 unsigned binding, unsigned usage);
105 struct r600_bo *r600_bo_handle(struct radeon *radeon,
106 unsigned handle, unsigned *array_mode);
107 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx);
108 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
109 boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo,
110 unsigned stride, struct winsys_handle *whandle);
111 static INLINE unsigned r600_bo_offset(struct r600_bo *bo)
115 void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo);
117 /* this relies on the pipe_reference being the first member of r600_bo */
118 static INLINE void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, struct r600_bo *src)
120 struct r600_bo *old = *dst;
122 if (pipe_reference((struct pipe_reference *)(*dst), (struct pipe_reference *)src)) {
123 r600_bo_destroy(radeon, old);
129 /* R600/R700 STATES */
130 #define R600_GROUP_MAX 16
131 #define R600_BLOCK_MAX_BO 32
132 #define R600_BLOCK_MAX_REG 128
134 /* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
135 /* there is a block entry for each register so 512 blocks */
136 /* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
137 /* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
138 #define RANGE_OFFSET_START 0x8000
140 #define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
142 #define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
143 #define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
145 struct r600_pipe_reg {
148 struct r600_block *block;
153 struct r600_pipe_state {
156 struct r600_pipe_reg regs[R600_BLOCK_MAX_REG];
159 struct r600_pipe_resource_state {
162 struct r600_bo *bo[2];
165 #define R600_BLOCK_STATUS_ENABLED (1 << 0)
166 #define R600_BLOCK_STATUS_DIRTY (1 << 1)
167 #define R600_BLOCK_STATUS_RESOURCE_DIRTY (1 << 2)
169 #define R600_BLOCK_STATUS_RESOURCE_VERTEX (1 << 3)
171 struct r600_block_reloc {
173 unsigned flush_flags;
175 unsigned bo_pm4_index;
179 struct list_head list;
180 struct list_head enable_list;
183 unsigned start_offset;
184 unsigned pm4_ndwords;
185 unsigned pm4_flush_ndwords;
190 u32 pm4[R600_BLOCK_MAX_REG];
191 unsigned pm4_bo_index[R600_BLOCK_MAX_REG];
192 struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
196 struct r600_block **blocks;
205 uint32_t read_domain;
206 uint32_t write_domain;
216 /* The kind of query */
218 /* Offset of the first result for current query */
219 unsigned results_start;
220 /* Offset of the next free result after current query data */
221 unsigned results_end;
222 /* Size of the result */
223 unsigned result_size;
224 /* Count of new queries started in one stream without flushing */
225 unsigned queries_emitted;
228 /* The buffer where query results are stored. It's used as a ring,
229 * data blocks for current query are stored sequentially from
230 * results_start to results_end, with wrapping on the buffer end */
231 struct r600_bo *buffer;
232 unsigned buffer_size;
233 /* linked list of queries */
234 struct list_head list;
237 #define R600_QUERY_STATE_STARTED (1 << 0)
238 #define R600_QUERY_STATE_ENDED (1 << 1)
239 #define R600_QUERY_STATE_SUSPENDED (1 << 2)
240 #define R600_QUERY_STATE_FLUSHED (1 << 3)
242 #define R600_CONTEXT_DRAW_PENDING (1 << 0)
243 #define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1)
244 #define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2)
246 struct r600_context {
247 struct radeon *radeon;
248 struct r600_range *range;
250 struct r600_block **blocks;
251 struct list_head dirty;
252 struct list_head resource_dirty;
253 struct list_head enable_list;
254 unsigned pm4_ndwords;
255 unsigned pm4_cdwords;
256 unsigned pm4_dirty_cdwords;
257 unsigned ctx_pm4_ndwords;
258 unsigned init_dwords;
261 struct r600_reloc *reloc;
262 struct radeon_bo **bo;
264 struct list_head query_list;
265 unsigned num_query_running;
266 unsigned backend_mask;
267 struct list_head fenced_bo;
268 unsigned max_db; /* for OQ */
269 unsigned num_dest_buffers;
271 boolean predicate_drawing;
272 struct r600_range ps_resources;
273 struct r600_range vs_resources;
274 struct r600_range fs_resources;
275 int num_ps_resources, num_vs_resources, num_fs_resources;
276 boolean have_depth_texture, have_depth_fb;
281 u32 vgt_num_instances;
283 u32 vgt_draw_initiator;
284 u32 indices_bo_offset;
285 struct r600_bo *indices;
288 void r600_get_backend_mask(struct r600_context *ctx);
289 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
290 void r600_context_fini(struct r600_context *ctx);
291 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
292 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
293 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
294 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
295 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
296 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
297 void r600_context_flush(struct r600_context *ctx);
298 void r600_context_dump_bof(struct r600_context *ctx, const char *file);
299 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
301 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
302 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
303 boolean r600_context_query_result(struct r600_context *ctx,
304 struct r600_query *query,
305 boolean wait, void *vresult);
306 void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
307 void r600_query_end(struct r600_context *ctx, struct r600_query *query);
308 void r600_context_queries_suspend(struct r600_context *ctx);
309 void r600_context_queries_resume(struct r600_context *ctx, boolean flushed);
310 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
312 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence,
313 unsigned offset, unsigned value);
314 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags);
315 void r600_context_flush_dest_caches(struct r600_context *ctx);
317 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
318 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
319 void evergreen_context_flush_dest_caches(struct r600_context *ctx);
320 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
321 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
322 void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
323 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
324 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
326 struct radeon *radeon_decref(struct radeon *radeon);
328 void _r600_pipe_state_add_reg(struct r600_context *ctx,
329 struct r600_pipe_state *state,
330 u32 offset, u32 value, u32 mask,
331 u32 range_id, u32 block_id,
334 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
335 u32 offset, u32 value, u32 mask,
337 #define r600_pipe_state_add_reg(state, offset, value, mask, bo) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo)
339 static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
342 state->regs[state->nregs].value = value;
346 static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
347 u32 value, struct r600_bo *bo)
349 state->regs[state->nregs].value = value;
350 state->regs[state->nregs].bo = bo;