src/gallium/drivers/r600/evergreen_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /* TODO:
  25  *      - fix mask for depth control & cull for query
  26  */
  27 #include <stdio.h>
  28 #include <errno.h>
  29 #include "pipe/p_defines.h"
  30 #include "pipe/p_state.h"
  31 #include "pipe/p_context.h"
  32 #include "tgsi/tgsi_scan.h"
  33 #include "tgsi/tgsi_parse.h"
  34 #include "tgsi/tgsi_util.h"
  35 #include "util/u_blitter.h"
  36 #include "util/u_double_list.h"
  37 #include "util/u_transfer.h"
  38 #include "util/u_surface.h"
  39 #include "util/u_pack_color.h"
  40 #include "util/u_memory.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_framebuffer.h"
  43 #include "pipebuffer/pb_buffer.h"
  44 #include "r600.h"
  45 #include "evergreend.h"
  46 #include "r600_resource.h"
  47 #include "r600_shader.h"
  48 #include "r600_pipe.h"
  49 #include "r600_formats.h"
  50
  51 static uint32_t eg_num_banks(uint32_t nbanks)
  52 {
  53         switch (nbanks) {
  54         case 2:
  55                 return 0;
  56         case 4:
  57                 return 1;
  58         case 8:
  59         default:
  60                 return 2;
  61         case 16:
  62                 return 3;
  63         }
  64 }
  65
  66
  67 static unsigned eg_tile_split(unsigned tile_split)
  68 {
  69         switch (tile_split) {
  70         case 64:        tile_split = 0; break;
  71         case 128:       tile_split = 1; break;
  72         case 256:       tile_split = 2; break;
  73         case 512:       tile_split = 3; break;
  74         default:
  75         case 1024:      tile_split = 4; break;
  76         case 2048:      tile_split = 5; break;
  77         case 4096:      tile_split = 6; break;
  78         }
  79         return tile_split;
  80 }
  81
  82 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
  83 {
  84         switch (macro_tile_aspect) {
  85         default:
  86         case 1: macro_tile_aspect = 0;  break;
  87         case 2: macro_tile_aspect = 1;  break;
  88         case 4: macro_tile_aspect = 2;  break;
  89         case 8: macro_tile_aspect = 3;  break;
  90         }
  91         return macro_tile_aspect;
  92 }
  93
  94 static unsigned eg_bank_wh(unsigned bankwh)
  95 {
  96         switch (bankwh) {
  97         default:
  98         case 1: bankwh = 0;     break;
  99         case 2: bankwh = 1;     break;
 100         case 4: bankwh = 2;     break;
 101         case 8: bankwh = 3;     break;
 102         }
 103         return bankwh;
 104 }
 105
 106 static uint32_t r600_translate_blend_function(int blend_func)
 107 {
 108         switch (blend_func) {
 109         case PIPE_BLEND_ADD:
 110                 return V_028780_COMB_DST_PLUS_SRC;
 111         case PIPE_BLEND_SUBTRACT:
 112                 return V_028780_COMB_SRC_MINUS_DST;
 113         case PIPE_BLEND_REVERSE_SUBTRACT:
 114                 return V_028780_COMB_DST_MINUS_SRC;
 115         case PIPE_BLEND_MIN:
 116                 return V_028780_COMB_MIN_DST_SRC;
 117         case PIPE_BLEND_MAX:
 118                 return V_028780_COMB_MAX_DST_SRC;
 119         default:
 120                 R600_ERR("Unknown blend function %d\n", blend_func);
 121                 assert(0);
 122                 break;
 123         }
 124         return 0;
 125 }
 126
 127 static uint32_t r600_translate_blend_factor(int blend_fact)
 128 {
 129         switch (blend_fact) {
 130         case PIPE_BLENDFACTOR_ONE:
 131                 return V_028780_BLEND_ONE;
 132         case PIPE_BLENDFACTOR_SRC_COLOR:
 133                 return V_028780_BLEND_SRC_COLOR;
 134         case PIPE_BLENDFACTOR_SRC_ALPHA:
 135                 return V_028780_BLEND_SRC_ALPHA;
 136         case PIPE_BLENDFACTOR_DST_ALPHA:
 137                 return V_028780_BLEND_DST_ALPHA;
 138         case PIPE_BLENDFACTOR_DST_COLOR:
 139                 return V_028780_BLEND_DST_COLOR;
 140         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
 141                 return V_028780_BLEND_SRC_ALPHA_SATURATE;
 142         case PIPE_BLENDFACTOR_CONST_COLOR:
 143                 return V_028780_BLEND_CONST_COLOR;
 144         case PIPE_BLENDFACTOR_CONST_ALPHA:
 145                 return V_028780_BLEND_CONST_ALPHA;
 146         case PIPE_BLENDFACTOR_ZERO:
 147                 return V_028780_BLEND_ZERO;
 148         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
 149                 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
 150         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
 151                 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
 152         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
 153                 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
 154         case PIPE_BLENDFACTOR_INV_DST_COLOR:
 155                 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
 156         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
 157                 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
 158         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
 159                 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
 160         case PIPE_BLENDFACTOR_SRC1_COLOR:
 161                 return V_028780_BLEND_SRC1_COLOR;
 162         case PIPE_BLENDFACTOR_SRC1_ALPHA:
 163                 return V_028780_BLEND_SRC1_ALPHA;
 164         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
 165                 return V_028780_BLEND_INV_SRC1_COLOR;
 166         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
 167                 return V_028780_BLEND_INV_SRC1_ALPHA;
 168         default:
 169                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
 170                 assert(0);
 171                 break;
 172         }
 173         return 0;
 174 }
 175
 176 static unsigned r600_tex_dim(unsigned dim)
 177 {
 178         switch (dim) {
 179         default:
 180         case PIPE_TEXTURE_1D:
 181                 return V_030000_SQ_TEX_DIM_1D;
 182         case PIPE_TEXTURE_1D_ARRAY:
 183                 return V_030000_SQ_TEX_DIM_1D_ARRAY;
 184         case PIPE_TEXTURE_2D:
 185         case PIPE_TEXTURE_RECT:
 186                 return V_030000_SQ_TEX_DIM_2D;
 187         case PIPE_TEXTURE_2D_ARRAY:
 188                 return V_030000_SQ_TEX_DIM_2D_ARRAY;
 189         case PIPE_TEXTURE_3D:
 190                 return V_030000_SQ_TEX_DIM_3D;
 191         case PIPE_TEXTURE_CUBE:
 192                 return V_030000_SQ_TEX_DIM_CUBEMAP;
 193         }
 194 }
 195
 196 static uint32_t r600_translate_dbformat(enum pipe_format format)
 197 {
 198         switch (format) {
 199         case PIPE_FORMAT_Z16_UNORM:
 200                 return V_028040_Z_16;
 201         case PIPE_FORMAT_Z24X8_UNORM:
 202         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 203                 return V_028040_Z_24;
 204         case PIPE_FORMAT_Z32_FLOAT:
 205         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 206                 return V_028040_Z_32_FLOAT;
 207         default:
 208                 return ~0U;
 209         }
 210 }
 211
 212 static uint32_t r600_translate_colorswap(enum pipe_format format)
 213 {
 214         switch (format) {
 215         /* 8-bit buffers. */
 216         case PIPE_FORMAT_L4A4_UNORM:
 217         case PIPE_FORMAT_A4R4_UNORM:
 218                 return V_028C70_SWAP_ALT;
 219
 220         case PIPE_FORMAT_A8_UNORM:
 221         case PIPE_FORMAT_A8_UINT:
 222         case PIPE_FORMAT_A8_SINT:
 223         case PIPE_FORMAT_R4A4_UNORM:
 224                 return V_028C70_SWAP_ALT_REV;
 225         case PIPE_FORMAT_I8_UNORM:
 226         case PIPE_FORMAT_L8_UNORM:
 227         case PIPE_FORMAT_I8_UINT:
 228         case PIPE_FORMAT_I8_SINT:
 229         case PIPE_FORMAT_L8_UINT:
 230         case PIPE_FORMAT_L8_SINT:
 231         case PIPE_FORMAT_L8_SRGB:
 232         case PIPE_FORMAT_R8_UNORM:
 233         case PIPE_FORMAT_R8_SNORM:
 234         case PIPE_FORMAT_R8_UINT:
 235         case PIPE_FORMAT_R8_SINT:
 236                 return V_028C70_SWAP_STD;
 237
 238         /* 16-bit buffers. */
 239         case PIPE_FORMAT_B5G6R5_UNORM:
 240                 return V_028C70_SWAP_STD_REV;
 241
 242         case PIPE_FORMAT_B5G5R5A1_UNORM:
 243         case PIPE_FORMAT_B5G5R5X1_UNORM:
 244                 return V_028C70_SWAP_ALT;
 245
 246         case PIPE_FORMAT_B4G4R4A4_UNORM:
 247         case PIPE_FORMAT_B4G4R4X4_UNORM:
 248                 return V_028C70_SWAP_ALT;
 249
 250         case PIPE_FORMAT_Z16_UNORM:
 251                 return V_028C70_SWAP_STD;
 252
 253         case PIPE_FORMAT_L8A8_UNORM:
 254         case PIPE_FORMAT_L8A8_UINT:
 255         case PIPE_FORMAT_L8A8_SINT:
 256         case PIPE_FORMAT_L8A8_SRGB:
 257                 return V_028C70_SWAP_ALT;
 258         case PIPE_FORMAT_R8G8_UNORM:
 259         case PIPE_FORMAT_R8G8_UINT:
 260         case PIPE_FORMAT_R8G8_SINT:
 261                 return V_028C70_SWAP_STD;
 262
 263         case PIPE_FORMAT_R16_UNORM:
 264         case PIPE_FORMAT_R16_UINT:
 265         case PIPE_FORMAT_R16_SINT:
 266         case PIPE_FORMAT_R16_FLOAT:
 267                 return V_028C70_SWAP_STD;
 268
 269         /* 32-bit buffers. */
 270         case PIPE_FORMAT_A8B8G8R8_SRGB:
 271                 return V_028C70_SWAP_STD_REV;
 272         case PIPE_FORMAT_B8G8R8A8_SRGB:
 273                 return V_028C70_SWAP_ALT;
 274
 275         case PIPE_FORMAT_B8G8R8A8_UNORM:
 276         case PIPE_FORMAT_B8G8R8X8_UNORM:
 277                 return V_028C70_SWAP_ALT;
 278
 279         case PIPE_FORMAT_A8R8G8B8_UNORM:
 280         case PIPE_FORMAT_X8R8G8B8_UNORM:
 281                 return V_028C70_SWAP_ALT_REV;
 282         case PIPE_FORMAT_R8G8B8A8_SNORM:
 283         case PIPE_FORMAT_R8G8B8A8_UNORM:
 284         case PIPE_FORMAT_R8G8B8A8_SSCALED:
 285         case PIPE_FORMAT_R8G8B8A8_USCALED:
 286         case PIPE_FORMAT_R8G8B8A8_SINT:
 287         case PIPE_FORMAT_R8G8B8A8_UINT:
 288         case PIPE_FORMAT_R8G8B8X8_UNORM:
 289                 return V_028C70_SWAP_STD;
 290
 291         case PIPE_FORMAT_A8B8G8R8_UNORM:
 292         case PIPE_FORMAT_X8B8G8R8_UNORM:
 293         /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
 294                 return V_028C70_SWAP_STD_REV;
 295
 296         case PIPE_FORMAT_Z24X8_UNORM:
 297         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 298                 return V_028C70_SWAP_STD;
 299
 300         case PIPE_FORMAT_X8Z24_UNORM:
 301         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 302                 return V_028C70_SWAP_STD;
 303
 304         case PIPE_FORMAT_R10G10B10A2_UNORM:
 305         case PIPE_FORMAT_R10G10B10X2_SNORM:
 306         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 307                 return V_028C70_SWAP_STD;
 308
 309         case PIPE_FORMAT_B10G10R10A2_UNORM:
 310         case PIPE_FORMAT_B10G10R10A2_UINT:
 311                 return V_028C70_SWAP_ALT;
 312
 313         case PIPE_FORMAT_R11G11B10_FLOAT:
 314         case PIPE_FORMAT_R32_FLOAT:
 315         case PIPE_FORMAT_R32_UINT:
 316         case PIPE_FORMAT_R32_SINT:
 317         case PIPE_FORMAT_Z32_FLOAT:
 318         case PIPE_FORMAT_R16G16_FLOAT:
 319         case PIPE_FORMAT_R16G16_UNORM:
 320         case PIPE_FORMAT_R16G16_UINT:
 321         case PIPE_FORMAT_R16G16_SINT:
 322                 return V_028C70_SWAP_STD;
 323
 324         /* 64-bit buffers. */
 325         case PIPE_FORMAT_R32G32_FLOAT:
 326         case PIPE_FORMAT_R32G32_UINT:
 327         case PIPE_FORMAT_R32G32_SINT:
 328         case PIPE_FORMAT_R16G16B16A16_UNORM:
 329         case PIPE_FORMAT_R16G16B16A16_SNORM:
 330         case PIPE_FORMAT_R16G16B16A16_USCALED:
 331         case PIPE_FORMAT_R16G16B16A16_SSCALED:
 332         case PIPE_FORMAT_R16G16B16A16_UINT:
 333         case PIPE_FORMAT_R16G16B16A16_SINT:
 334         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 335         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 336
 337         /* 128-bit buffers. */
 338         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 339         case PIPE_FORMAT_R32G32B32A32_SNORM:
 340         case PIPE_FORMAT_R32G32B32A32_UNORM:
 341         case PIPE_FORMAT_R32G32B32A32_SSCALED:
 342         case PIPE_FORMAT_R32G32B32A32_USCALED:
 343         case PIPE_FORMAT_R32G32B32A32_SINT:
 344         case PIPE_FORMAT_R32G32B32A32_UINT:
 345                 return V_028C70_SWAP_STD;
 346         default:
 347                 R600_ERR("unsupported colorswap format %d\n", format);
 348                 return ~0U;
 349         }
 350         return ~0U;
 351 }
 352
 353 static uint32_t r600_translate_colorformat(enum pipe_format format)
 354 {
 355         switch (format) {
 356         /* 8-bit buffers. */
 357         case PIPE_FORMAT_A8_UNORM:
 358         case PIPE_FORMAT_A8_UINT:
 359         case PIPE_FORMAT_A8_SINT:
 360         case PIPE_FORMAT_I8_UNORM:
 361         case PIPE_FORMAT_I8_UINT:
 362         case PIPE_FORMAT_I8_SINT:
 363         case PIPE_FORMAT_L8_UNORM:
 364         case PIPE_FORMAT_L8_UINT:
 365         case PIPE_FORMAT_L8_SINT:
 366         case PIPE_FORMAT_L8_SRGB:
 367         case PIPE_FORMAT_R8_UNORM:
 368         case PIPE_FORMAT_R8_SNORM:
 369         case PIPE_FORMAT_R8_UINT:
 370         case PIPE_FORMAT_R8_SINT:
 371                 return V_028C70_COLOR_8;
 372
 373         /* 16-bit buffers. */
 374         case PIPE_FORMAT_B5G6R5_UNORM:
 375                 return V_028C70_COLOR_5_6_5;
 376
 377         case PIPE_FORMAT_B5G5R5A1_UNORM:
 378         case PIPE_FORMAT_B5G5R5X1_UNORM:
 379                 return V_028C70_COLOR_1_5_5_5;
 380
 381         case PIPE_FORMAT_B4G4R4A4_UNORM:
 382         case PIPE_FORMAT_B4G4R4X4_UNORM:
 383                 return V_028C70_COLOR_4_4_4_4;
 384
 385         case PIPE_FORMAT_Z16_UNORM:
 386                 return V_028C70_COLOR_16;
 387
 388         case PIPE_FORMAT_L8A8_UNORM:
 389         case PIPE_FORMAT_L8A8_UINT:
 390         case PIPE_FORMAT_L8A8_SINT:
 391         case PIPE_FORMAT_L8A8_SRGB:
 392         case PIPE_FORMAT_R8G8_UNORM:
 393         case PIPE_FORMAT_R8G8_UINT:
 394         case PIPE_FORMAT_R8G8_SINT:
 395                 return V_028C70_COLOR_8_8;
 396
 397         case PIPE_FORMAT_R16_UNORM:
 398         case PIPE_FORMAT_R16_UINT:
 399         case PIPE_FORMAT_R16_SINT:
 400                 return V_028C70_COLOR_16;
 401
 402         case PIPE_FORMAT_R16_FLOAT:
 403                 return V_028C70_COLOR_16_FLOAT;
 404
 405         /* 32-bit buffers. */
 406         case PIPE_FORMAT_A8B8G8R8_SRGB:
 407         case PIPE_FORMAT_A8B8G8R8_UNORM:
 408         case PIPE_FORMAT_A8R8G8B8_UNORM:
 409         case PIPE_FORMAT_B8G8R8A8_SRGB:
 410         case PIPE_FORMAT_B8G8R8A8_UNORM:
 411         case PIPE_FORMAT_B8G8R8X8_UNORM:
 412         case PIPE_FORMAT_R8G8B8A8_SNORM:
 413         case PIPE_FORMAT_R8G8B8A8_UNORM:
 414         case PIPE_FORMAT_R8G8B8X8_UNORM:
 415         case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
 416         case PIPE_FORMAT_X8B8G8R8_UNORM:
 417         case PIPE_FORMAT_X8R8G8B8_UNORM:
 418         case PIPE_FORMAT_R8G8B8_UNORM:
 419         case PIPE_FORMAT_R8G8B8A8_SSCALED:
 420         case PIPE_FORMAT_R8G8B8A8_USCALED:
 421         case PIPE_FORMAT_R8G8B8A8_SINT:
 422         case PIPE_FORMAT_R8G8B8A8_UINT:
 423                 return V_028C70_COLOR_8_8_8_8;
 424
 425         case PIPE_FORMAT_R10G10B10A2_UNORM:
 426         case PIPE_FORMAT_R10G10B10X2_SNORM:
 427         case PIPE_FORMAT_B10G10R10A2_UNORM:
 428         case PIPE_FORMAT_B10G10R10A2_UINT:
 429         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 430                 return V_028C70_COLOR_2_10_10_10;
 431
 432         case PIPE_FORMAT_Z24X8_UNORM:
 433         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 434                 return V_028C70_COLOR_8_24;
 435
 436         case PIPE_FORMAT_X8Z24_UNORM:
 437         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 438                 return V_028C70_COLOR_24_8;
 439
 440         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 441                 return V_028C70_COLOR_X24_8_32_FLOAT;
 442
 443         case PIPE_FORMAT_R32_UINT:
 444         case PIPE_FORMAT_R32_SINT:
 445                 return V_028C70_COLOR_32;
 446
 447         case PIPE_FORMAT_R32_FLOAT:
 448         case PIPE_FORMAT_Z32_FLOAT:
 449                 return V_028C70_COLOR_32_FLOAT;
 450
 451         case PIPE_FORMAT_R16G16_FLOAT:
 452                 return V_028C70_COLOR_16_16_FLOAT;
 453
 454         case PIPE_FORMAT_R16G16_SSCALED:
 455         case PIPE_FORMAT_R16G16_UNORM:
 456         case PIPE_FORMAT_R16G16_UINT:
 457         case PIPE_FORMAT_R16G16_SINT:
 458                 return V_028C70_COLOR_16_16;
 459
 460         case PIPE_FORMAT_R11G11B10_FLOAT:
 461                 return V_028C70_COLOR_10_11_11_FLOAT;
 462
 463         /* 64-bit buffers. */
 464         case PIPE_FORMAT_R16G16B16_USCALED:
 465         case PIPE_FORMAT_R16G16B16_SSCALED:
 466         case PIPE_FORMAT_R16G16B16A16_UINT:
 467         case PIPE_FORMAT_R16G16B16A16_SINT:
 468         case PIPE_FORMAT_R16G16B16A16_USCALED:
 469         case PIPE_FORMAT_R16G16B16A16_SSCALED:
 470         case PIPE_FORMAT_R16G16B16A16_UNORM:
 471         case PIPE_FORMAT_R16G16B16A16_SNORM:
 472                 return V_028C70_COLOR_16_16_16_16;
 473
 474         case PIPE_FORMAT_R16G16B16_FLOAT:
 475         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 476                 return V_028C70_COLOR_16_16_16_16_FLOAT;
 477
 478         case PIPE_FORMAT_R32G32_FLOAT:
 479                 return V_028C70_COLOR_32_32_FLOAT;
 480
 481         case PIPE_FORMAT_R32G32_USCALED:
 482         case PIPE_FORMAT_R32G32_SSCALED:
 483         case PIPE_FORMAT_R32G32_SINT:
 484         case PIPE_FORMAT_R32G32_UINT:
 485                 return V_028C70_COLOR_32_32;
 486
 487         /* 96-bit buffers. */
 488         case PIPE_FORMAT_R32G32B32_FLOAT:
 489                 return V_028C70_COLOR_32_32_32_FLOAT;
 490
 491         /* 128-bit buffers. */
 492         case PIPE_FORMAT_R32G32B32A32_SNORM:
 493         case PIPE_FORMAT_R32G32B32A32_UNORM:
 494         case PIPE_FORMAT_R32G32B32A32_SSCALED:
 495         case PIPE_FORMAT_R32G32B32A32_USCALED:
 496         case PIPE_FORMAT_R32G32B32A32_SINT:
 497         case PIPE_FORMAT_R32G32B32A32_UINT:
 498                 return V_028C70_COLOR_32_32_32_32;
 499         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 500                 return V_028C70_COLOR_32_32_32_32_FLOAT;
 501
 502         /* YUV buffers. */
 503         case PIPE_FORMAT_UYVY:
 504         case PIPE_FORMAT_YUYV:
 505         default:
 506                 return ~0U; /* Unsupported. */
 507         }
 508 }
 509
 510 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
 511 {
 512         if (R600_BIG_ENDIAN) {
 513                 switch(colorformat) {
 514
 515                 /* 8-bit buffers. */
 516                 case V_028C70_COLOR_8:
 517                         return ENDIAN_NONE;
 518
 519                 /* 16-bit buffers. */
 520                 case V_028C70_COLOR_5_6_5:
 521                 case V_028C70_COLOR_1_5_5_5:
 522                 case V_028C70_COLOR_4_4_4_4:
 523                 case V_028C70_COLOR_16:
 524                 case V_028C70_COLOR_8_8:
 525                         return ENDIAN_8IN16;
 526
 527                 /* 32-bit buffers. */
 528                 case V_028C70_COLOR_8_8_8_8:
 529                 case V_028C70_COLOR_2_10_10_10:
 530                 case V_028C70_COLOR_8_24:
 531                 case V_028C70_COLOR_24_8:
 532                 case V_028C70_COLOR_32_FLOAT:
 533                 case V_028C70_COLOR_16_16_FLOAT:
 534                 case V_028C70_COLOR_16_16:
 535                         return ENDIAN_8IN32;
 536
 537                 /* 64-bit buffers. */
 538                 case V_028C70_COLOR_16_16_16_16:
 539                 case V_028C70_COLOR_16_16_16_16_FLOAT:
 540                         return ENDIAN_8IN16;
 541
 542                 case V_028C70_COLOR_32_32_FLOAT:
 543                 case V_028C70_COLOR_32_32:
 544                 case V_028C70_COLOR_X24_8_32_FLOAT:
 545                         return ENDIAN_8IN32;
 546
 547                 /* 96-bit buffers. */
 548                 case V_028C70_COLOR_32_32_32_FLOAT:
 549                 /* 128-bit buffers. */
 550                 case V_028C70_COLOR_32_32_32_32_FLOAT:
 551                 case V_028C70_COLOR_32_32_32_32:
 552                         return ENDIAN_8IN32;
 553                 default:
 554                         return ENDIAN_NONE; /* Unsupported. */
 555                 }
 556         } else {
 557                 return ENDIAN_NONE;
 558         }
 559 }
 560
 561 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
 562 {
 563         return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
 564 }
 565
 566 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
 567 {
 568         return r600_translate_colorformat(format) != ~0U &&
 569                 r600_translate_colorswap(format) != ~0U;
 570 }
 571
 572 static bool r600_is_zs_format_supported(enum pipe_format format)
 573 {
 574         return r600_translate_dbformat(format) != ~0U;
 575 }
 576
 577 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 578                                       enum pipe_format format,
 579                                       enum pipe_texture_target target,
 580                                       unsigned sample_count,
 581                                       unsigned usage)
 582 {
 583         unsigned retval = 0;
 584
 585         if (target >= PIPE_MAX_TEXTURE_TYPES) {
 586                 R600_ERR("r600: unsupported texture type %d\n", target);
 587                 return FALSE;
 588         }
 589
 590         if (!util_format_is_supported(format, usage))
 591                 return FALSE;
 592
 593         /* Multisample */
 594         if (sample_count > 1)
 595                 return FALSE;
 596
 597         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 598             r600_is_sampler_format_supported(screen, format)) {
 599                 retval |= PIPE_BIND_SAMPLER_VIEW;
 600         }
 601
 602         if ((usage & (PIPE_BIND_RENDER_TARGET |
 603                       PIPE_BIND_DISPLAY_TARGET |
 604                       PIPE_BIND_SCANOUT |
 605                       PIPE_BIND_SHARED)) &&
 606             r600_is_colorbuffer_format_supported(format)) {
 607                 retval |= usage &
 608                           (PIPE_BIND_RENDER_TARGET |
 609                            PIPE_BIND_DISPLAY_TARGET |
 610                            PIPE_BIND_SCANOUT |
 611                            PIPE_BIND_SHARED);
 612         }
 613
 614         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 615             r600_is_zs_format_supported(format)) {
 616                 retval |= PIPE_BIND_DEPTH_STENCIL;
 617         }
 618
 619         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
 620             r600_is_vertex_format_supported(format)) {
 621                 retval |= PIPE_BIND_VERTEX_BUFFER;
 622         }
 623
 624         if (usage & PIPE_BIND_TRANSFER_READ)
 625                 retval |= PIPE_BIND_TRANSFER_READ;
 626         if (usage & PIPE_BIND_TRANSFER_WRITE)
 627                 retval |= PIPE_BIND_TRANSFER_WRITE;
 628
 629         return retval == usage;
 630 }
 631
 632 static void evergreen_set_blend_color(struct pipe_context *ctx,
 633                                         const struct pipe_blend_color *state)
 634 {
 635         struct r600_context *rctx = (struct r600_context *)ctx;
 636         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 637
 638         if (rstate == NULL)
 639                 return;
 640
 641         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 642         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
 643         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
 644         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
 645         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
 646
 647         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 648         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 649         r600_context_pipe_state_set(rctx, rstate);
 650 }
 651
 652 static void *evergreen_create_blend_state(struct pipe_context *ctx,
 653                                         const struct pipe_blend_state *state)
 654 {
 655         struct r600_context *rctx = (struct r600_context *)ctx;
 656         struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
 657         struct r600_pipe_state *rstate;
 658         uint32_t color_control, target_mask;
 659         /* FIXME there is more then 8 framebuffer */
 660         unsigned blend_cntl[8];
 661
 662         if (blend == NULL) {
 663                 return NULL;
 664         }
 665
 666         rstate = &blend->rstate;
 667
 668         rstate->id = R600_PIPE_STATE_BLEND;
 669
 670         target_mask = 0;
 671         color_control = S_028808_MODE(1);
 672         if (state->logicop_enable) {
 673                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 674         } else {
 675                 color_control |= (0xcc << 16);
 676         }
 677         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 678         if (state->independent_blend_enable) {
 679                 for (int i = 0; i < 8; i++) {
 680                         target_mask |= (state->rt[i].colormask << (4 * i));
 681                 }
 682         } else {
 683                 for (int i = 0; i < 8; i++) {
 684                         target_mask |= (state->rt[0].colormask << (4 * i));
 685                 }
 686         }
 687         blend->cb_target_mask = target_mask;
 688
 689         r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 690                                 color_control, NULL, 0);
 691
 692         if (rctx->chip_class != CAYMAN)
 693                 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, ~0, NULL, 0);
 694         else {
 695                 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0, NULL, 0);
 696                 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0, NULL, 0);
 697         }
 698
 699         for (int i = 0; i < 8; i++) {
 700                 /* state->rt entries > 0 only written if independent blending */
 701                 const int j = state->independent_blend_enable ? i : 0;
 702
 703                 unsigned eqRGB = state->rt[j].rgb_func;
 704                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 705                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 706                 unsigned eqA = state->rt[j].alpha_func;
 707                 unsigned srcA = state->rt[j].alpha_src_factor;
 708                 unsigned dstA = state->rt[j].alpha_dst_factor;
 709
 710                 blend_cntl[i] = 0;
 711                 if (!state->rt[j].blend_enable)
 712                         continue;
 713
 714                 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
 715                 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 716                 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 717                 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 718
 719                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 720                         blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
 721                         blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 722                         blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 723                         blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 724                 }
 725         }
 726         for (int i = 0; i < 8; i++) {
 727                 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0);
 728         }
 729
 730         return rstate;
 731 }
 732
 733 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
 734                                    const struct pipe_depth_stencil_alpha_state *state)
 735 {
 736         struct r600_context *rctx = (struct r600_context *)ctx;
 737         struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
 738         unsigned db_depth_control, alpha_test_control, alpha_ref;
 739         unsigned db_render_override, db_render_control;
 740         struct r600_pipe_state *rstate;
 741
 742         if (dsa == NULL) {
 743                 return NULL;
 744         }
 745
 746         dsa->valuemask[0] = state->stencil[0].valuemask;
 747         dsa->valuemask[1] = state->stencil[1].valuemask;
 748         dsa->writemask[0] = state->stencil[0].writemask;
 749         dsa->writemask[1] = state->stencil[1].writemask;
 750
 751         rstate = &dsa->rstate;
 752
 753         rstate->id = R600_PIPE_STATE_DSA;
 754         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 755                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 756                 S_028800_ZFUNC(state->depth.func);
 757
 758         /* stencil */
 759         if (state->stencil[0].enabled) {
 760                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 761                 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
 762                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 763                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 764                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 765
 766                 if (state->stencil[1].enabled) {
 767                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 768                         db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
 769                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 770                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 771                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 772                 }
 773         }
 774
 775         /* alpha */
 776         alpha_test_control = 0;
 777         alpha_ref = 0;
 778         if (state->alpha.enabled) {
 779                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 780                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 781                 alpha_ref = fui(state->alpha.ref_value);
 782         }
 783         dsa->alpha_ref = alpha_ref;
 784
 785         /* misc */
 786         db_render_control = 0;
 787         db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
 788                 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
 789                 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
 790         /* TODO db_render_override depends on query */
 791         r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0);
 792         r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0);
 793         r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
 794         r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, NULL, 0);
 795         r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
 796         /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
 797          * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
 798          * evergreen_pipe_shader_ps().*/
 799         r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
 800         r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, NULL, 0);
 801         r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, NULL, 0);
 802         r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, NULL, 0);
 803         r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, NULL, 0);
 804         r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0);
 805         dsa->db_render_override = db_render_override;
 806
 807         return rstate;
 808 }
 809
 810 static void *evergreen_create_rs_state(struct pipe_context *ctx,
 811                                         const struct pipe_rasterizer_state *state)
 812 {
 813         struct r600_context *rctx = (struct r600_context *)ctx;
 814         struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
 815         struct r600_pipe_state *rstate;
 816         unsigned tmp;
 817         unsigned prov_vtx = 1, polygon_dual_mode;
 818         unsigned clip_rule;
 819         float psize_min, psize_max;
 820
 821         if (rs == NULL) {
 822                 return NULL;
 823         }
 824
 825         polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
 826                                 state->fill_back != PIPE_POLYGON_MODE_FILL);
 827
 828         if (state->flatshade_first)
 829                 prov_vtx = 0;
 830
 831         rstate = &rs->rstate;
 832         rs->flatshade = state->flatshade;
 833         rs->sprite_coord_enable = state->sprite_coord_enable;
 834         rs->two_side = state->light_twoside;
 835         rs->clip_plane_enable = state->clip_plane_enable;
 836         rs->pa_sc_line_stipple = state->line_stipple_enable ?
 837                                 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
 838                                 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 839         rs->pa_su_sc_mode_cntl =
 840                 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 841                 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 842                 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 843                 S_028814_FACE(!state->front_ccw) |
 844                 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 845                 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 846                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 847                 S_028814_POLY_MODE(polygon_dual_mode) |
 848                 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 849                 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
 850         rs->pa_cl_clip_cntl =
 851                 S_028810_PS_UCP_MODE(3) |
 852                 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
 853                 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
 854                 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
 855
 856         clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
 857
 858         /* offset */
 859         rs->offset_units = state->offset_units;
 860         rs->offset_scale = state->offset_scale * 12.0f;
 861
 862         rstate->id = R600_PIPE_STATE_RASTERIZER;
 863         tmp = S_0286D4_FLAT_SHADE_ENA(1);
 864         if (state->sprite_coord_enable) {
 865                 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
 866                         S_0286D4_PNT_SPRITE_OVRD_X(2) |
 867                         S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 868                         S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 869                         S_0286D4_PNT_SPRITE_OVRD_W(1);
 870                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 871                         tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 872                 }
 873         }
 874         r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
 875
 876         r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0);
 877         /* point size 12.4 fixed point */
 878         tmp = (unsigned)(state->point_size * 8.0);
 879         r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
 880
 881         if (state->point_size_per_vertex) {
 882                 psize_min = util_get_min_point_size(state);
 883                 psize_max = 8192;
 884         } else {
 885                 /* Force the point size to be as if the vertex output was disabled. */
 886                 psize_min = state->point_size;
 887                 psize_max = state->point_size;
 888         }
 889         /* Divide by two, because 0.5 = 1 pixel. */
 890         r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
 891                                 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
 892                                 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
 893                                 NULL, 0);
 894
 895         tmp = (unsigned)state->line_width * 8;
 896         r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
 897         r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
 898                                 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
 899                                 NULL, 0);
 900
 901         if (rctx->chip_class == CAYMAN) {
 902                 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
 903                 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
 904                                         S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
 905                                         NULL, 0);
 906                 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
 907                 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
 908                 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
 909                 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
 910
 911
 912         } else {
 913                 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
 914
 915                 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
 916                 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
 917                 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
 918                 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
 919
 920                 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
 921                                         S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
 922                                         NULL, 0);
 923         }
 924         r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
 925         r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
 926         return rstate;
 927 }
 928
 929 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
 930                                         const struct pipe_sampler_state *state)
 931 {
 932         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 933         union util_color uc;
 934         unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
 935
 936         if (rstate == NULL) {
 937                 return NULL;
 938         }
 939
 940         rstate->id = R600_PIPE_STATE_SAMPLER;
 941         util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
 942         r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
 943                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 944                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 945                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 946                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
 947                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
 948                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 949                         S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
 950                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 951                         S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
 952         r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
 953                         S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
 954                         S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
 955                         NULL, 0);
 956         r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
 957                                         S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
 958                                         (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
 959                                         S_03C008_TYPE(1),
 960                                         NULL, 0);
 961
 962         if (uc.ui) {
 963                 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
 964                 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
 965                 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
 966                 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
 967         }
 968         return rstate;
 969 }
 970
 971 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
 972                                                         struct pipe_resource *texture,
 973                                                         const struct pipe_sampler_view *state)
 974 {
 975         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
 976         struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
 977         struct r600_pipe_resource_state *rstate;
 978         struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
 979         unsigned format, endian;
 980         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 981         unsigned char swizzle[4], array_mode = 0, tile_type = 0;
 982         unsigned height, depth, width;
 983         unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
 984
 985         if (view == NULL)
 986                 return NULL;
 987         rstate = &view->state;
 988
 989         /* initialize base object */
 990         view->base = *state;
 991         view->base.texture = NULL;
 992         pipe_reference(NULL, &texture->reference);
 993         view->base.texture = texture;
 994         view->base.reference.count = 1;
 995         view->base.context = ctx;
 996
 997         swizzle[0] = state->swizzle_r;
 998         swizzle[1] = state->swizzle_g;
 999         swizzle[2] = state->swizzle_b;
1000         swizzle[3] = state->swizzle_a;
1001
1002         format = r600_translate_texformat(ctx->screen, state->format,
1003                                           swizzle,
1004                                           &word4, &yuv_format);
1005         if (format == ~0) {
1006                 format = 0;
1007         }
1008
1009         if (tmp->depth && !tmp->is_flushing_texture) {
1010                 r600_texture_depth_flush(ctx, texture, TRUE);
1011                 tmp = tmp->flushed_depth_texture;
1012         }
1013
1014         endian = r600_colorformat_endian_swap(format);
1015
1016         if (!rscreen->use_surface) {
1017                 height = texture->height0;
1018                 depth = texture->depth0;
1019                 width = texture->width0;
1020                 pitch = align(tmp->pitch_in_blocks[0] *
1021                                 util_format_get_blockwidth(state->format), 8);
1022                 array_mode = tmp->array_mode[0];
1023                 tile_type = tmp->tile_type;
1024                 tile_split = 0;
1025                 macro_aspect = 0;
1026                 bankw = 0;
1027                 bankh = 0;
1028         } else {
1029                 width = tmp->surface.level[0].npix_x;
1030                 height = tmp->surface.level[0].npix_y;
1031                 depth = tmp->surface.level[0].npix_z;
1032                 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1033                 tile_type = tmp->tile_type;
1034
1035                 switch (tmp->surface.level[0].mode) {
1036                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1037                         array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1038                         break;
1039                 case RADEON_SURF_MODE_2D:
1040                         array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1041                         break;
1042                 case RADEON_SURF_MODE_1D:
1043                         array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1044                         break;
1045                 case RADEON_SURF_MODE_LINEAR:
1046                 default:
1047                         array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1048                         break;
1049                 }
1050                 tile_split = tmp->surface.tile_split;
1051                 macro_aspect = tmp->surface.mtilea;
1052                 bankw = tmp->surface.bankw;
1053                 bankh = tmp->surface.bankh;
1054                 tile_split = eg_tile_split(tile_split);
1055                 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1056                 bankw = eg_bank_wh(bankw);
1057                 bankh = eg_bank_wh(bankh);
1058         }
1059         /* 128 bit formats require tile type = 1 */
1060         if (rscreen->chip_class == CAYMAN) {
1061                 if (util_format_get_blocksize(state->format) >= 16)
1062                         tile_type = 1;
1063         }
1064         nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1065
1066         if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1067                 height = 1;
1068                 depth = texture->array_size;
1069         } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1070                 depth = texture->array_size;
1071         }
1072
1073         rstate->bo[0] = &tmp->resource;
1074         rstate->bo[1] = &tmp->resource;
1075         rstate->bo_usage[0] = RADEON_USAGE_READ;
1076         rstate->bo_usage[1] = RADEON_USAGE_READ;
1077
1078         rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1079                           S_030000_PITCH((pitch / 8) - 1) |
1080                           S_030000_TEX_WIDTH(width - 1));
1081         if (rscreen->chip_class == CAYMAN)
1082                 rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1083         else
1084                 rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1085         rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1086                           S_030004_TEX_DEPTH(depth - 1) |
1087                           S_030004_ARRAY_MODE(array_mode));
1088         rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1089         if (state->u.tex.last_level) {
1090                 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1091         } else {
1092                 rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1093         }
1094         rstate->val[4] = (word4 |
1095                           S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1096                           S_030010_ENDIAN_SWAP(endian) |
1097                           S_030010_BASE_LEVEL(state->u.tex.first_level));
1098         rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1099                           S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1100                           S_030014_LAST_ARRAY(state->u.tex.last_layer));
1101         /* aniso max 16 samples */
1102         rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1103                          (S_030018_TILE_SPLIT(tile_split));
1104         rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1105                          S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1106                          S_03001C_BANK_WIDTH(bankw) |
1107                          S_03001C_BANK_HEIGHT(bankh) |
1108                          S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1109                          S_03001C_NUM_BANKS(nbanks);
1110
1111         return &view->base;
1112 }
1113
1114 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1115                                         struct pipe_sampler_view **views)
1116 {
1117         struct r600_context *rctx = (struct r600_context *)ctx;
1118         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1119
1120         for (int i = 0; i < count; i++) {
1121                 if (resource[i]) {
1122                         evergreen_context_pipe_state_set_vs_resource(rctx, &resource[i]->state,
1123                                                                      i + R600_MAX_CONST_BUFFERS);
1124                 }
1125         }
1126 }
1127
1128 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1129                                         struct pipe_sampler_view **views)
1130 {
1131         struct r600_context *rctx = (struct r600_context *)ctx;
1132         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1133         int i;
1134         int has_depth = 0;
1135
1136         for (i = 0; i < count; i++) {
1137                 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1138                         if (resource[i]) {
1139                                 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1140                                         has_depth = 1;
1141                                 evergreen_context_pipe_state_set_ps_resource(rctx, &resource[i]->state,
1142                                                                              i + R600_MAX_CONST_BUFFERS);
1143                         } else
1144                                 evergreen_context_pipe_state_set_ps_resource(rctx, NULL,
1145                                                                              i + R600_MAX_CONST_BUFFERS);
1146
1147                         pipe_sampler_view_reference(
1148                                 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1149                                 views[i]);
1150                 } else {
1151                         if (resource[i]) {
1152                                 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1153                                         has_depth = 1;
1154                         }
1155                 }
1156         }
1157         for (i = count; i < NUM_TEX_UNITS; i++) {
1158                 if (rctx->ps_samplers.views[i]) {
1159                         evergreen_context_pipe_state_set_ps_resource(rctx, NULL,
1160                                                                      i + R600_MAX_CONST_BUFFERS);
1161                         pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1162                 }
1163         }
1164         rctx->have_depth_texture = has_depth;
1165         rctx->ps_samplers.n_views = count;
1166 }
1167
1168 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1169 {
1170         struct r600_context *rctx = (struct r600_context *)ctx;
1171         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1172
1173         if (count)
1174                 r600_inval_texture_cache(rctx);
1175
1176         memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1177         rctx->ps_samplers.n_samplers = count;
1178
1179         for (int i = 0; i < count; i++) {
1180                 evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1181         }
1182 }
1183
1184 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1185 {
1186         struct r600_context *rctx = (struct r600_context *)ctx;
1187         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1188
1189         if (count)
1190                 r600_inval_texture_cache(rctx);
1191
1192         for (int i = 0; i < count; i++) {
1193                 evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1194         }
1195 }
1196
1197 static void evergreen_set_clip_state(struct pipe_context *ctx,
1198                                 const struct pipe_clip_state *state)
1199 {
1200         struct r600_context *rctx = (struct r600_context *)ctx;
1201         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1202         struct pipe_resource *cbuf;
1203
1204         if (rstate == NULL)
1205                 return;
1206
1207         rctx->clip = *state;
1208         rstate->id = R600_PIPE_STATE_CLIP;
1209         for (int i = 0; i < 6; i++) {
1210                 r600_pipe_state_add_reg(rstate,
1211                                         R_0285BC_PA_CL_UCP0_X + i * 16,
1212                                         fui(state->ucp[i][0]), NULL, 0);
1213                 r600_pipe_state_add_reg(rstate,
1214                                         R_0285C0_PA_CL_UCP0_Y + i * 16,
1215                                         fui(state->ucp[i][1]) , NULL, 0);
1216                 r600_pipe_state_add_reg(rstate,
1217                                         R_0285C4_PA_CL_UCP0_Z + i * 16,
1218                                         fui(state->ucp[i][2]), NULL, 0);
1219                 r600_pipe_state_add_reg(rstate,
1220                                         R_0285C8_PA_CL_UCP0_W + i * 16,
1221                                         fui(state->ucp[i][3]), NULL, 0);
1222         }
1223
1224         free(rctx->states[R600_PIPE_STATE_CLIP]);
1225         rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1226         r600_context_pipe_state_set(rctx, rstate);
1227
1228         cbuf = pipe_user_buffer_create(ctx->screen,
1229                                    state->ucp,
1230                                    4*4*8, /* 8*4 floats */
1231                                    PIPE_BIND_CONSTANT_BUFFER);
1232         r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1233         pipe_resource_reference(&cbuf, NULL);
1234 }
1235
1236 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1237                                          const struct pipe_poly_stipple *state)
1238 {
1239 }
1240
1241 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1242 {
1243 }
1244
1245 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1246                                         const struct pipe_scissor_state *state)
1247 {
1248         struct r600_context *rctx = (struct r600_context *)ctx;
1249         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1250         uint32_t tl, br;
1251
1252         if (rstate == NULL)
1253                 return;
1254
1255         rstate->id = R600_PIPE_STATE_SCISSOR;
1256         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1257         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1258         r600_pipe_state_add_reg(rstate,
1259                                 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1260                                 NULL, 0);
1261         r600_pipe_state_add_reg(rstate,
1262                                 R_028214_PA_SC_CLIPRECT_0_BR, br,
1263                                 NULL, 0);
1264         r600_pipe_state_add_reg(rstate,
1265                                 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1266                                 NULL, 0);
1267         r600_pipe_state_add_reg(rstate,
1268                                 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1269                                 NULL, 0);
1270         r600_pipe_state_add_reg(rstate,
1271                                 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1272                                 NULL, 0);
1273         r600_pipe_state_add_reg(rstate,
1274                                 R_028224_PA_SC_CLIPRECT_2_BR, br,
1275                                 NULL, 0);
1276         r600_pipe_state_add_reg(rstate,
1277                                 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1278                                 NULL, 0);
1279         r600_pipe_state_add_reg(rstate,
1280                                 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1281                                 NULL, 0);
1282
1283         free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1284         rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1285         r600_context_pipe_state_set(rctx, rstate);
1286 }
1287
1288 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1289                                         const struct pipe_viewport_state *state)
1290 {
1291         struct r600_context *rctx = (struct r600_context *)ctx;
1292         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1293
1294         if (rstate == NULL)
1295                 return;
1296
1297         rctx->viewport = *state;
1298         rstate->id = R600_PIPE_STATE_VIEWPORT;
1299         r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0);
1300         r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0);
1301         r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1302         r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1303         r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1304         r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1305         r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1306         r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1307         r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0);
1308
1309         free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1310         rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1311         r600_context_pipe_state_set(rctx, rstate);
1312 }
1313
1314 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1315                          const struct pipe_framebuffer_state *state, int cb)
1316 {
1317         struct r600_screen *rscreen = rctx->screen;
1318         struct r600_resource_texture *rtex;
1319         struct r600_surface *surf;
1320         unsigned level = state->cbufs[cb]->u.tex.level;
1321         unsigned pitch, slice;
1322         unsigned color_info, color_attrib;
1323         unsigned format, swap, ntype, endian;
1324         uint64_t offset;
1325         unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1326         const struct util_format_description *desc;
1327         int i;
1328         unsigned blend_clamp = 0, blend_bypass = 0;
1329
1330         surf = (struct r600_surface *)state->cbufs[cb];
1331         rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1332
1333         if (rtex->depth)
1334                 rctx->have_depth_fb = TRUE;
1335
1336         if (rtex->depth && !rtex->is_flushing_texture) {
1337                 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1338                 rtex = rtex->flushed_depth_texture;
1339         }
1340
1341         /* XXX quite sure for dx10+ hw don't need any offset hacks */
1342         if (!rscreen->use_surface) {
1343                 offset = r600_texture_get_offset(rtex,
1344                                 level, state->cbufs[cb]->u.tex.first_layer);
1345                 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1346                 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1347                 if (slice) {
1348                         slice = slice - 1;
1349                 }
1350                 color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1351                 tile_split = 0;
1352                 macro_aspect = 0;
1353                 bankw = 0;
1354                 bankh = 0;
1355                 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1356                         tile_type = rtex->tile_type;
1357                 } else {
1358                         /* workaround for linear buffers */
1359                         tile_type = 1;
1360                 }
1361         } else {
1362                 offset = rtex->surface.level[level].offset;
1363                 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1364                         offset += rtex->surface.level[level].slice_size *
1365                                   state->cbufs[cb]->u.tex.first_layer;
1366                 }
1367                 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1368                 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1369                 if (slice) {
1370                         slice = slice - 1;
1371                 }
1372                 color_info = 0;
1373                 switch (rtex->surface.level[level].mode) {
1374                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1375                         color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1376                         tile_type = 1;
1377                         break;
1378                 case RADEON_SURF_MODE_1D:
1379                         color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1380                         tile_type = rtex->tile_type;
1381                         break;
1382                 case RADEON_SURF_MODE_2D:
1383                         color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1384                         tile_type = rtex->tile_type;
1385                         break;
1386                 case RADEON_SURF_MODE_LINEAR:
1387                 default:
1388                         color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1389                         tile_type = 1;
1390                         break;
1391                 }
1392                 tile_split = rtex->surface.tile_split;
1393                 macro_aspect = rtex->surface.mtilea;
1394                 bankw = rtex->surface.bankw;
1395                 bankh = rtex->surface.bankh;
1396                 tile_split = eg_tile_split(tile_split);
1397                 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1398                 bankw = eg_bank_wh(bankw);
1399                 bankh = eg_bank_wh(bankh);
1400         }
1401         /* 128 bit formats require tile type = 1 */
1402         if (rscreen->chip_class == CAYMAN) {
1403                 if (util_format_get_blocksize(surf->base.format) >= 16)
1404                         tile_type = 1;
1405         }
1406         nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1407         desc = util_format_description(surf->base.format);
1408         for (i = 0; i < 4; i++) {
1409                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1410                         break;
1411                 }
1412         }
1413
1414         color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1415                         S_028C74_NUM_BANKS(nbanks) |
1416                         S_028C74_BANK_WIDTH(bankw) |
1417                         S_028C74_BANK_HEIGHT(bankh) |
1418                         S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1419                         S_028C74_NON_DISP_TILING_ORDER(tile_type);
1420
1421         ntype = V_028C70_NUMBER_UNORM;
1422         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1423                 ntype = V_028C70_NUMBER_SRGB;
1424         else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1425                 if (desc->channel[i].normalized)
1426                         ntype = V_028C70_NUMBER_SNORM;
1427                 else if (desc->channel[i].pure_integer)
1428                         ntype = V_028C70_NUMBER_SINT;
1429         } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1430                 if (desc->channel[i].normalized)
1431                         ntype = V_028C70_NUMBER_UNORM;
1432                 else if (desc->channel[i].pure_integer)
1433                         ntype = V_028C70_NUMBER_UINT;
1434         }
1435
1436         format = r600_translate_colorformat(surf->base.format);
1437         swap = r600_translate_colorswap(surf->base.format);
1438         if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1439                 endian = ENDIAN_NONE;
1440         } else {
1441                 endian = r600_colorformat_endian_swap(format);
1442         }
1443
1444         /* blend clamp should be set for all NORM/SRGB types */
1445         if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1446             ntype == V_028C70_NUMBER_SRGB)
1447                 blend_clamp = 1;
1448
1449         /* set blend bypass according to docs if SINT/UINT or
1450            8/24 COLOR variants */
1451         if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1452             format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1453             format == V_028C70_COLOR_X24_8_32_FLOAT) {
1454                 blend_clamp = 0;
1455                 blend_bypass = 1;
1456         }
1457
1458         color_info |= S_028C70_FORMAT(format) |
1459                 S_028C70_COMP_SWAP(swap) |
1460                 S_028C70_BLEND_CLAMP(blend_clamp) |
1461                 S_028C70_BLEND_BYPASS(blend_bypass) |
1462                 S_028C70_NUMBER_TYPE(ntype) |
1463                 S_028C70_ENDIAN(endian);
1464
1465         /* EXPORT_NORM is an optimzation that can be enabled for better
1466          * performance in certain cases.
1467          * EXPORT_NORM can be enabled if:
1468          * - 11-bit or smaller UNORM/SNORM/SRGB
1469          * - 16-bit or smaller FLOAT
1470          */
1471         /* FIXME: This should probably be the same for all CBs if we want
1472          * useful alpha tests. */
1473         if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1474             ((desc->channel[i].size < 12 &&
1475               desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1476               ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1477              (desc->channel[i].size < 17 &&
1478               desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1479                 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1480                 rctx->export_16bpc = true;
1481         } else {
1482                 rctx->export_16bpc = false;
1483         }
1484         rctx->alpha_ref_dirty = true;
1485
1486
1487         offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1488         offset >>= 8;
1489
1490         /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1491         r600_pipe_state_add_reg(rstate,
1492                                 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1493                                 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1494         r600_pipe_state_add_reg(rstate,
1495                                 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1496                                 0x0, NULL, 0);
1497         r600_pipe_state_add_reg(rstate,
1498                                 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1499                                 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1500         r600_pipe_state_add_reg(rstate,
1501                                 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1502                                 S_028C64_PITCH_TILE_MAX(pitch),
1503                                 NULL, 0);
1504         r600_pipe_state_add_reg(rstate,
1505                                 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1506                                 S_028C68_SLICE_TILE_MAX(slice),
1507                                 NULL, 0);
1508         if (!rscreen->use_surface) {
1509                 r600_pipe_state_add_reg(rstate,
1510                                         R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1511                                         0x00000000, NULL, 0);
1512         } else {
1513                 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1514                         r600_pipe_state_add_reg(rstate,
1515                                                 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1516                                                 0x00000000, NULL, 0);
1517                 } else {
1518                         r600_pipe_state_add_reg(rstate,
1519                                                 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1520                                                 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1521                                                 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1522                                                 NULL, 0);
1523                 }
1524         }
1525         r600_pipe_state_add_reg(rstate,
1526                                 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1527                                 color_attrib,
1528                                 &rtex->resource, RADEON_USAGE_READWRITE);
1529 }
1530
1531 static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1532                          const struct pipe_framebuffer_state *state)
1533 {
1534         struct r600_screen *rscreen = rctx->screen;
1535         struct r600_resource_texture *rtex;
1536         struct r600_surface *surf;
1537         uint64_t offset;
1538         unsigned level, first_layer, pitch, slice, format, array_mode;
1539         unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1540
1541         if (state->zsbuf == NULL)
1542                 return;
1543
1544         surf = (struct r600_surface *)state->zsbuf;
1545         level = surf->base.u.tex.level;
1546         rtex = (struct r600_resource_texture*)surf->base.texture;
1547         first_layer = surf->base.u.tex.first_layer;
1548         format = r600_translate_dbformat(rtex->real_format);
1549
1550         offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1551         /* XXX remove this once tiling is properly supported */
1552         if (!rscreen->use_surface) {
1553                 /* XXX remove this once tiling is properly supported */
1554                 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1555                                 V_028C70_ARRAY_1D_TILED_THIN1;
1556
1557                 offset += r600_texture_get_offset(rtex, level, first_layer);
1558                 pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1559                 slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1560                 if (slice) {
1561                         slice = slice - 1;
1562                 }
1563                 tile_split = 0;
1564                 macro_aspect = 0;
1565                 bankw = 0;
1566                 bankh = 0;
1567         } else {
1568                 offset += rtex->surface.level[level].offset;
1569                 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1570                 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1571                 if (slice) {
1572                         slice = slice - 1;
1573                 }
1574                 switch (rtex->surface.level[level].mode) {
1575                 case RADEON_SURF_MODE_2D:
1576                         array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1577                         break;
1578                 case RADEON_SURF_MODE_1D:
1579                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1580                 case RADEON_SURF_MODE_LINEAR:
1581                 default:
1582                         array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1583                         break;
1584                 }
1585                 tile_split = rtex->surface.tile_split;
1586                 macro_aspect = rtex->surface.mtilea;
1587                 bankw = rtex->surface.bankw;
1588                 bankh = rtex->surface.bankh;
1589                 tile_split = eg_tile_split(tile_split);
1590                 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1591                 bankw = eg_bank_wh(bankw);
1592                 bankh = eg_bank_wh(bankh);
1593         }
1594         nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1595         offset >>= 8;
1596
1597         z_info = S_028040_ARRAY_MODE(array_mode) |
1598                  S_028040_FORMAT(format) |
1599                  S_028040_TILE_SPLIT(tile_split)|
1600                  S_028040_NUM_BANKS(nbanks) |
1601                  S_028040_BANK_WIDTH(bankw) |
1602                  S_028040_BANK_HEIGHT(bankh) |
1603                  S_028040_MACRO_TILE_ASPECT(macro_aspect);
1604
1605         r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1606                                 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1607         r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1608                                 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1609         if (!rscreen->use_surface) {
1610                 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1611                                         0x00000000, NULL, 0);
1612         } else {
1613                 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1614                                         S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1615                                         S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1616                                         NULL, 0);
1617         }
1618
1619         if (rtex->stencil) {
1620                 uint64_t stencil_offset =
1621                         r600_texture_get_offset(rtex->stencil, level, first_layer);
1622                 unsigned stile_split;
1623
1624                 stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1625                 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1626                 stencil_offset >>= 8;
1627
1628                 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1629                                         stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1630                 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1631                                         stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1632                 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1633                                         1 | S_028044_TILE_SPLIT(stile_split),
1634                                         &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1635         } else {
1636                 if (rscreen->use_surface && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1637                         uint64_t stencil_offset = rtex->surface.stencil_offset;
1638                         unsigned stile_split = rtex->surface.stencil_tile_split;
1639
1640                         stile_split = eg_tile_split(stile_split);
1641                         stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1642                         stencil_offset += rtex->surface.level[level].offset / 4;
1643                         stencil_offset >>= 8;
1644
1645                         r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1646                                                 stencil_offset, &rtex->resource,
1647                                                 RADEON_USAGE_READWRITE);
1648                         r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1649                                                 stencil_offset, &rtex->resource,
1650                                                 RADEON_USAGE_READWRITE);
1651                         r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1652                                                 1 | S_028044_TILE_SPLIT(stile_split),
1653                                                 &rtex->resource,
1654                                                 RADEON_USAGE_READWRITE);
1655                 } else {
1656                         r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1657                                                 offset, &rtex->resource,
1658                                                 RADEON_USAGE_READWRITE);
1659                         r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1660                                                 offset, &rtex->resource,
1661                                                 RADEON_USAGE_READWRITE);
1662                         r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1663                                                 0, NULL, RADEON_USAGE_READWRITE);
1664                 }
1665         }
1666
1667         r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, z_info,
1668                                 &rtex->resource, RADEON_USAGE_READWRITE);
1669         r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1670                                 S_028058_PITCH_TILE_MAX(pitch),
1671                                 NULL, 0);
1672         r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1673                                 S_02805C_SLICE_TILE_MAX(slice),
1674                                 NULL, 0);
1675 }
1676
1677 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1678                                         const struct pipe_framebuffer_state *state)
1679 {
1680         struct r600_context *rctx = (struct r600_context *)ctx;
1681         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1682         uint32_t shader_mask, tl, br;
1683         int tl_x, tl_y, br_x, br_y;
1684
1685         if (rstate == NULL)
1686                 return;
1687
1688         r600_flush_framebuffer(rctx, false);
1689
1690         /* unreference old buffer and reference new one */
1691         rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1692
1693         util_copy_framebuffer_state(&rctx->framebuffer, state);
1694
1695         /* build states */
1696         rctx->have_depth_fb = 0;
1697         rctx->nr_cbufs = state->nr_cbufs;
1698         for (int i = 0; i < state->nr_cbufs; i++) {
1699                 evergreen_cb(rctx, rstate, state, i);
1700         }
1701         if (state->zsbuf) {
1702                 evergreen_db(rctx, rstate, state);
1703         }
1704
1705         shader_mask = 0;
1706         for (int i = 0; i < state->nr_cbufs; i++) {
1707                 shader_mask |= 0xf << (i * 4);
1708         }
1709         tl_x = 0;
1710         tl_y = 0;
1711         br_x = state->width;
1712         br_y = state->height;
1713         /* EG hw workaround */
1714         if (br_x == 0)
1715                 tl_x = 1;
1716         if (br_y == 0)
1717                 tl_y = 1;
1718         /* cayman hw workaround */
1719         if (rctx->chip_class == CAYMAN) {
1720                 if (br_x == 1 && br_y == 1)
1721                         br_x = 2;
1722         }
1723         tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1724         br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1725
1726         r600_pipe_state_add_reg(rstate,
1727                                 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1728                                 NULL, 0);
1729         r600_pipe_state_add_reg(rstate,
1730                                 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1731                                 NULL, 0);
1732         r600_pipe_state_add_reg(rstate,
1733                                 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1734                                 NULL, 0);
1735         r600_pipe_state_add_reg(rstate,
1736                                 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1737                                 NULL, 0);
1738         r600_pipe_state_add_reg(rstate,
1739                                 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1740                                 NULL, 0);
1741         r600_pipe_state_add_reg(rstate,
1742                                 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1743                                 NULL, 0);
1744         r600_pipe_state_add_reg(rstate,
1745                                 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1746                                 NULL, 0);
1747         r600_pipe_state_add_reg(rstate,
1748                                 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1749                                 NULL, 0);
1750         r600_pipe_state_add_reg(rstate,
1751                                 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1752                                 NULL, 0);
1753         r600_pipe_state_add_reg(rstate,
1754                                 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1755                                 NULL, 0);
1756         r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1757                                 shader_mask, NULL, 0);
1758
1759
1760         if (rctx->chip_class == CAYMAN) {
1761                 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1762                                         0x00000000, NULL, 0);
1763         } else {
1764                 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1765                                         0x00000000, NULL, 0);
1766                 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0,
1767                                         0x00000000, NULL, 0);
1768         }
1769
1770         free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1771         rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1772         r600_context_pipe_state_set(rctx, rstate);
1773
1774         if (state->zsbuf) {
1775                 evergreen_polygon_offset_update(rctx);
1776         }
1777 }
1778
1779 void evergreen_init_state_functions(struct r600_context *rctx)
1780 {
1781         rctx->context.create_blend_state = evergreen_create_blend_state;
1782         rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1783         rctx->context.create_fs_state = r600_create_shader_state;
1784         rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1785         rctx->context.create_sampler_state = evergreen_create_sampler_state;
1786         rctx->context.create_sampler_view = evergreen_create_sampler_view;
1787         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1788         rctx->context.create_vs_state = r600_create_shader_state;
1789         rctx->context.bind_blend_state = r600_bind_blend_state;
1790         rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1791         rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1792         rctx->context.bind_fs_state = r600_bind_ps_shader;
1793         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1794         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1795         rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1796         rctx->context.bind_vs_state = r600_bind_vs_shader;
1797         rctx->context.delete_blend_state = r600_delete_state;
1798         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1799         rctx->context.delete_fs_state = r600_delete_ps_shader;
1800         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1801         rctx->context.delete_sampler_state = r600_delete_state;
1802         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1803         rctx->context.delete_vs_state = r600_delete_vs_shader;
1804         rctx->context.set_blend_color = evergreen_set_blend_color;
1805         rctx->context.set_clip_state = evergreen_set_clip_state;
1806         rctx->context.set_constant_buffer = r600_set_constant_buffer;
1807         rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1808         rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1809         rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1810         rctx->context.set_sample_mask = evergreen_set_sample_mask;
1811         rctx->context.set_scissor_state = evergreen_set_scissor_state;
1812         rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1813         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1814         rctx->context.set_index_buffer = r600_set_index_buffer;
1815         rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1816         rctx->context.set_viewport_state = evergreen_set_viewport_state;
1817         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1818         rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1819         rctx->context.texture_barrier = r600_texture_barrier;
1820         rctx->context.create_stream_output_target = r600_create_so_target;
1821         rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1822         rctx->context.set_stream_output_targets = r600_set_so_targets;
1823 }
1824
1825 static void cayman_init_config(struct r600_context *rctx)
1826 {
1827         struct r600_pipe_state *rstate = &rctx->config;
1828         unsigned tmp;
1829
1830         tmp = 0x00000000;
1831         tmp |= S_008C00_EXPORT_SRC_C(1);
1832         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
1833
1834         /* always set the temp clauses */
1835         r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), NULL, 0);
1836         r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, NULL, 0);
1837         r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, NULL, 0);
1838         r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), NULL, 0);
1839
1840         r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
1841
1842         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
1843         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
1844         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
1845         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
1846         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
1847         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
1848         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
1849         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
1850         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
1851         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
1852         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
1853         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
1854         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
1855         r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
1856         r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
1857         r600_pipe_state_add_reg(rstate, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), NULL, 0);
1858         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
1859         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
1860         r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
1861
1862         r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, NULL, 0);
1863         r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, NULL, 0);
1864         r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, NULL, 0);
1865         r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, NULL, 0);
1866         r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, NULL, 0);
1867         r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, NULL, 0);
1868         r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, NULL, 0);
1869         r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, NULL, 0);
1870         r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, NULL, 0);
1871         r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, NULL, 0);
1872         r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, NULL, 0);
1873         r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, NULL, 0);
1874         r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, NULL, 0);
1875         r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, NULL, 0);
1876         r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, NULL, 0);
1877         r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, NULL, 0);
1878         r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, NULL, 0);
1879         r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, NULL, 0);
1880         r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, NULL, 0);
1881         r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, NULL, 0);
1882         r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, NULL, 0);
1883         r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, NULL, 0);
1884         r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, NULL, 0);
1885         r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, NULL, 0);
1886         r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, NULL, 0);
1887         r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, NULL, 0);
1888         r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, NULL, 0);
1889         r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, NULL, 0);
1890         r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, NULL, 0);
1891         r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, NULL, 0);
1892         r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, NULL, 0);
1893         r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, NULL, 0);
1894
1895         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
1896
1897         r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, NULL, 0);
1898         r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, NULL, 0);
1899
1900         r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, NULL, 0);
1901         r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, NULL, 0);
1902
1903         r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, NULL, 0);
1904         r600_context_pipe_state_set(rctx, rstate);
1905 }
1906
1907 void evergreen_init_config(struct r600_context *rctx)
1908 {
1909         struct r600_pipe_state *rstate = &rctx->config;
1910         int ps_prio;
1911         int vs_prio;
1912         int gs_prio;
1913         int es_prio;
1914         int hs_prio, cs_prio, ls_prio;
1915         int num_ps_gprs;
1916         int num_vs_gprs;
1917         int num_gs_gprs;
1918         int num_es_gprs;
1919         int num_hs_gprs;
1920         int num_ls_gprs;
1921         int num_temp_gprs;
1922         int num_ps_threads;
1923         int num_vs_threads;
1924         int num_gs_threads;
1925         int num_es_threads;
1926         int num_hs_threads;
1927         int num_ls_threads;
1928         int num_ps_stack_entries;
1929         int num_vs_stack_entries;
1930         int num_gs_stack_entries;
1931         int num_es_stack_entries;
1932         int num_hs_stack_entries;
1933         int num_ls_stack_entries;
1934         enum radeon_family family;
1935         unsigned tmp;
1936
1937         family = rctx->family;
1938
1939         if (rctx->chip_class == CAYMAN) {
1940                 cayman_init_config(rctx);
1941                 return;
1942         }
1943
1944         ps_prio = 0;
1945         vs_prio = 1;
1946         gs_prio = 2;
1947         es_prio = 3;
1948         hs_prio = 0;
1949         ls_prio = 0;
1950         cs_prio = 0;
1951
1952         switch (family) {
1953         case CHIP_CEDAR:
1954         default:
1955                 num_ps_gprs = 93;
1956                 num_vs_gprs = 46;
1957                 num_temp_gprs = 4;
1958                 num_gs_gprs = 31;
1959                 num_es_gprs = 31;
1960                 num_hs_gprs = 23;
1961                 num_ls_gprs = 23;
1962                 num_ps_threads = 96;
1963                 num_vs_threads = 16;
1964                 num_gs_threads = 16;
1965                 num_es_threads = 16;
1966                 num_hs_threads = 16;
1967                 num_ls_threads = 16;
1968                 num_ps_stack_entries = 42;
1969                 num_vs_stack_entries = 42;
1970                 num_gs_stack_entries = 42;
1971                 num_es_stack_entries = 42;
1972                 num_hs_stack_entries = 42;
1973                 num_ls_stack_entries = 42;
1974                 break;
1975         case CHIP_REDWOOD:
1976                 num_ps_gprs = 93;
1977                 num_vs_gprs = 46;
1978                 num_temp_gprs = 4;
1979                 num_gs_gprs = 31;
1980                 num_es_gprs = 31;
1981                 num_hs_gprs = 23;
1982                 num_ls_gprs = 23;
1983                 num_ps_threads = 128;
1984                 num_vs_threads = 20;
1985                 num_gs_threads = 20;
1986                 num_es_threads = 20;
1987                 num_hs_threads = 20;
1988                 num_ls_threads = 20;
1989                 num_ps_stack_entries = 42;
1990                 num_vs_stack_entries = 42;
1991                 num_gs_stack_entries = 42;
1992                 num_es_stack_entries = 42;
1993                 num_hs_stack_entries = 42;
1994                 num_ls_stack_entries = 42;
1995                 break;
1996         case CHIP_JUNIPER:
1997                 num_ps_gprs = 93;
1998                 num_vs_gprs = 46;
1999                 num_temp_gprs = 4;
2000                 num_gs_gprs = 31;
2001                 num_es_gprs = 31;
2002                 num_hs_gprs = 23;
2003                 num_ls_gprs = 23;
2004                 num_ps_threads = 128;
2005                 num_vs_threads = 20;
2006                 num_gs_threads = 20;
2007                 num_es_threads = 20;
2008                 num_hs_threads = 20;
2009                 num_ls_threads = 20;
2010                 num_ps_stack_entries = 85;
2011                 num_vs_stack_entries = 85;
2012                 num_gs_stack_entries = 85;
2013                 num_es_stack_entries = 85;
2014                 num_hs_stack_entries = 85;
2015                 num_ls_stack_entries = 85;
2016                 break;
2017         case CHIP_CYPRESS:
2018         case CHIP_HEMLOCK:
2019                 num_ps_gprs = 93;
2020                 num_vs_gprs = 46;
2021                 num_temp_gprs = 4;
2022                 num_gs_gprs = 31;
2023                 num_es_gprs = 31;
2024                 num_hs_gprs = 23;
2025                 num_ls_gprs = 23;
2026                 num_ps_threads = 128;
2027                 num_vs_threads = 20;
2028                 num_gs_threads = 20;
2029                 num_es_threads = 20;
2030                 num_hs_threads = 20;
2031                 num_ls_threads = 20;
2032                 num_ps_stack_entries = 85;
2033                 num_vs_stack_entries = 85;
2034                 num_gs_stack_entries = 85;
2035                 num_es_stack_entries = 85;
2036                 num_hs_stack_entries = 85;
2037                 num_ls_stack_entries = 85;
2038                 break;
2039         case CHIP_PALM:
2040                 num_ps_gprs = 93;
2041                 num_vs_gprs = 46;
2042                 num_temp_gprs = 4;
2043                 num_gs_gprs = 31;
2044                 num_es_gprs = 31;
2045                 num_hs_gprs = 23;
2046                 num_ls_gprs = 23;
2047                 num_ps_threads = 96;
2048                 num_vs_threads = 16;
2049                 num_gs_threads = 16;
2050                 num_es_threads = 16;
2051                 num_hs_threads = 16;
2052                 num_ls_threads = 16;
2053                 num_ps_stack_entries = 42;
2054                 num_vs_stack_entries = 42;
2055                 num_gs_stack_entries = 42;
2056                 num_es_stack_entries = 42;
2057                 num_hs_stack_entries = 42;
2058                 num_ls_stack_entries = 42;
2059                 break;
2060         case CHIP_SUMO:
2061                 num_ps_gprs = 93;
2062                 num_vs_gprs = 46;
2063                 num_temp_gprs = 4;
2064                 num_gs_gprs = 31;
2065                 num_es_gprs = 31;
2066                 num_hs_gprs = 23;
2067                 num_ls_gprs = 23;
2068                 num_ps_threads = 96;
2069                 num_vs_threads = 25;
2070                 num_gs_threads = 25;
2071                 num_es_threads = 25;
2072                 num_hs_threads = 25;
2073                 num_ls_threads = 25;
2074                 num_ps_stack_entries = 42;
2075                 num_vs_stack_entries = 42;
2076                 num_gs_stack_entries = 42;
2077                 num_es_stack_entries = 42;
2078                 num_hs_stack_entries = 42;
2079                 num_ls_stack_entries = 42;
2080                 break;
2081         case CHIP_SUMO2:
2082                 num_ps_gprs = 93;
2083                 num_vs_gprs = 46;
2084                 num_temp_gprs = 4;
2085                 num_gs_gprs = 31;
2086                 num_es_gprs = 31;
2087                 num_hs_gprs = 23;
2088                 num_ls_gprs = 23;
2089                 num_ps_threads = 96;
2090                 num_vs_threads = 25;
2091                 num_gs_threads = 25;
2092                 num_es_threads = 25;
2093                 num_hs_threads = 25;
2094                 num_ls_threads = 25;
2095                 num_ps_stack_entries = 85;
2096                 num_vs_stack_entries = 85;
2097                 num_gs_stack_entries = 85;
2098                 num_es_stack_entries = 85;
2099                 num_hs_stack_entries = 85;
2100                 num_ls_stack_entries = 85;
2101                 break;
2102         case CHIP_BARTS:
2103                 num_ps_gprs = 93;
2104                 num_vs_gprs = 46;
2105                 num_temp_gprs = 4;
2106                 num_gs_gprs = 31;
2107                 num_es_gprs = 31;
2108                 num_hs_gprs = 23;
2109                 num_ls_gprs = 23;
2110                 num_ps_threads = 128;
2111                 num_vs_threads = 20;
2112                 num_gs_threads = 20;
2113                 num_es_threads = 20;
2114                 num_hs_threads = 20;
2115                 num_ls_threads = 20;
2116                 num_ps_stack_entries = 85;
2117                 num_vs_stack_entries = 85;
2118                 num_gs_stack_entries = 85;
2119                 num_es_stack_entries = 85;
2120                 num_hs_stack_entries = 85;
2121                 num_ls_stack_entries = 85;
2122                 break;
2123         case CHIP_TURKS:
2124                 num_ps_gprs = 93;
2125                 num_vs_gprs = 46;
2126                 num_temp_gprs = 4;
2127                 num_gs_gprs = 31;
2128                 num_es_gprs = 31;
2129                 num_hs_gprs = 23;
2130                 num_ls_gprs = 23;
2131                 num_ps_threads = 128;
2132                 num_vs_threads = 20;
2133                 num_gs_threads = 20;
2134                 num_es_threads = 20;
2135                 num_hs_threads = 20;
2136                 num_ls_threads = 20;
2137                 num_ps_stack_entries = 42;
2138                 num_vs_stack_entries = 42;
2139                 num_gs_stack_entries = 42;
2140                 num_es_stack_entries = 42;
2141                 num_hs_stack_entries = 42;
2142                 num_ls_stack_entries = 42;
2143                 break;
2144         case CHIP_CAICOS:
2145                 num_ps_gprs = 93;
2146                 num_vs_gprs = 46;
2147                 num_temp_gprs = 4;
2148                 num_gs_gprs = 31;
2149                 num_es_gprs = 31;
2150                 num_hs_gprs = 23;
2151                 num_ls_gprs = 23;
2152                 num_ps_threads = 128;
2153                 num_vs_threads = 10;
2154                 num_gs_threads = 10;
2155                 num_es_threads = 10;
2156                 num_hs_threads = 10;
2157                 num_ls_threads = 10;
2158                 num_ps_stack_entries = 42;
2159                 num_vs_stack_entries = 42;
2160                 num_gs_stack_entries = 42;
2161                 num_es_stack_entries = 42;
2162                 num_hs_stack_entries = 42;
2163                 num_ls_stack_entries = 42;
2164                 break;
2165         }
2166
2167         tmp = 0x00000000;
2168         switch (family) {
2169         case CHIP_CEDAR:
2170         case CHIP_PALM:
2171         case CHIP_SUMO:
2172         case CHIP_SUMO2:
2173         case CHIP_CAICOS:
2174                 break;
2175         default:
2176                 tmp |= S_008C00_VC_ENABLE(1);
2177                 break;
2178         }
2179         tmp |= S_008C00_EXPORT_SRC_C(1);
2180         tmp |= S_008C00_CS_PRIO(cs_prio);
2181         tmp |= S_008C00_LS_PRIO(ls_prio);
2182         tmp |= S_008C00_HS_PRIO(hs_prio);
2183         tmp |= S_008C00_PS_PRIO(ps_prio);
2184         tmp |= S_008C00_VS_PRIO(vs_prio);
2185         tmp |= S_008C00_GS_PRIO(gs_prio);
2186         tmp |= S_008C00_ES_PRIO(es_prio);
2187         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
2188
2189         /* enable dynamic GPR resource management */
2190         if (rctx->screen->info.drm_minor >= 7) {
2191                 /* always set temp clauses */
2192                 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
2193                                         S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), NULL, 0);
2194                 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, NULL, 0);
2195                 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, NULL, 0);
2196                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), NULL, 0);
2197                 r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2198                                         S_028838_PS_GPRS(0x1e) |
2199                                         S_028838_VS_GPRS(0x1e) |
2200                                         S_028838_GS_GPRS(0x1e) |
2201                                         S_028838_ES_GPRS(0x1e) |
2202                                         S_028838_HS_GPRS(0x1e) |
2203                                         S_028838_LS_GPRS(0x1e), NULL, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2204         } else {
2205                 tmp = 0;
2206                 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2207                 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2208                 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2209                 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0);
2210
2211                 tmp = 0;
2212                 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2213                 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2214                 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, NULL, 0);
2215
2216                 tmp = 0;
2217                 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2218                 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2219                 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, NULL, 0);
2220         }
2221
2222         tmp = 0;
2223         tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
2224         tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2225         tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2226         tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2227         r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, NULL, 0);
2228
2229         tmp = 0;
2230         tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
2231         tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2232         r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, NULL, 0);
2233
2234         tmp = 0;
2235         tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2236         tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2237         r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, NULL, 0);
2238
2239         tmp = 0;
2240         tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2241         tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2242         r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, NULL, 0);
2243
2244         tmp = 0;
2245         tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2246         tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2247         r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, NULL, 0);
2248
2249         tmp = 0;
2250         tmp |= S_008E2C_NUM_PS_LDS(0x1000);
2251         tmp |= S_008E2C_NUM_LS_LDS(0x1000);
2252         r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, NULL, 0);
2253
2254         r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, NULL, 0);
2255         r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), NULL, 0);
2256
2257 #if 0
2258         r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, NULL, 0);
2259
2260         r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, NULL, 0);
2261 #endif
2262         r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
2263
2264         r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, NULL, 0);
2265         r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, NULL, 0);
2266         r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2267         r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2268         r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2269         r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2270
2271         r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, NULL, 0);
2272         r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, NULL, 0);
2273         r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, NULL, 0);
2274         r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, NULL, 0);
2275
2276         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
2277         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
2278         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
2279         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
2280         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
2281         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
2282         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
2283         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
2284         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
2285         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
2286         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
2287         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
2288         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
2289         r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
2290         r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
2291         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
2292         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
2293         r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
2294
2295         r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, NULL, 0);
2296         r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, NULL, 0);
2297         r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, NULL, 0);
2298         r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, NULL, 0);
2299         r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, NULL, 0);
2300         r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, NULL, 0);
2301         r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, NULL, 0);
2302         r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, NULL, 0);
2303         r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, NULL, 0);
2304         r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, NULL, 0);
2305         r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, NULL, 0);
2306         r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, NULL, 0);
2307         r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, NULL, 0);
2308         r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, NULL, 0);
2309         r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, NULL, 0);
2310         r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, NULL, 0);
2311         r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, NULL, 0);
2312         r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, NULL, 0);
2313         r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, NULL, 0);
2314         r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, NULL, 0);
2315         r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, NULL, 0);
2316         r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, NULL, 0);
2317         r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, NULL, 0);
2318         r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, NULL, 0);
2319         r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, NULL, 0);
2320         r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, NULL, 0);
2321         r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, NULL, 0);
2322         r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, NULL, 0);
2323         r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, NULL, 0);
2324         r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, NULL, 0);
2325         r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, NULL, 0);
2326         r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, NULL, 0);
2327
2328         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
2329
2330         r600_context_pipe_state_set(rctx, rstate);
2331 }
2332
2333 void evergreen_polygon_offset_update(struct r600_context *rctx)
2334 {
2335         struct r600_pipe_state state;
2336
2337         state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2338         state.nregs = 0;
2339         if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2340                 float offset_units = rctx->rasterizer->offset_units;
2341                 unsigned offset_db_fmt_cntl = 0, depth;
2342
2343                 switch (rctx->framebuffer.zsbuf->texture->format) {
2344                 case PIPE_FORMAT_Z24X8_UNORM:
2345                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2346                         depth = -24;
2347                         offset_units *= 2.0f;
2348                         break;
2349                 case PIPE_FORMAT_Z32_FLOAT:
2350                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2351                         depth = -23;
2352                         offset_units *= 1.0f;
2353                         offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2354                         break;
2355                 case PIPE_FORMAT_Z16_UNORM:
2356                         depth = -16;
2357                         offset_units *= 4.0f;
2358                         break;
2359                 default:
2360                         return;
2361                 }
2362                 /* FIXME some of those reg can be computed with cso */
2363                 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2364                 r600_pipe_state_add_reg(&state,
2365                                 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2366                                 fui(rctx->rasterizer->offset_scale), NULL, 0);
2367                 r600_pipe_state_add_reg(&state,
2368                                 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2369                                 fui(offset_units), NULL, 0);
2370                 r600_pipe_state_add_reg(&state,
2371                                 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2372                                 fui(rctx->rasterizer->offset_scale), NULL, 0);
2373                 r600_pipe_state_add_reg(&state,
2374                                 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2375                                 fui(offset_units), NULL, 0);
2376                 r600_pipe_state_add_reg(&state,
2377                                 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2378                                 offset_db_fmt_cntl, NULL, 0);
2379                 r600_context_pipe_state_set(rctx, &state);
2380         }
2381 }
2382
2383 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2384 {
2385         struct r600_context *rctx = (struct r600_context *)ctx;
2386         struct r600_pipe_state *rstate = &shader->rstate;
2387         struct r600_shader *rshader = &shader->shader;
2388         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2389         int pos_index = -1, face_index = -1;
2390         int ninterp = 0;
2391         boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2392         unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2393
2394         rstate->nregs = 0;
2395
2396         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2397         for (i = 0; i < rshader->ninput; i++) {
2398                 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2399                    POSITION goes via GPRs from the SC so isn't counted */
2400                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2401                         pos_index = i;
2402                 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2403                         face_index = i;
2404                 else {
2405                         ninterp++;
2406                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2407                                 have_linear = TRUE;
2408                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2409                                 have_perspective = TRUE;
2410                         if (rshader->input[i].centroid)
2411                                 have_centroid = TRUE;
2412                 }
2413
2414                 sid = rshader->input[i].spi_sid;
2415
2416                 if (sid) {
2417
2418                         tmp = S_028644_SEMANTIC(sid);
2419
2420                         if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2421                                 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2422                                 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2423                                         rctx->rasterizer && rctx->rasterizer->flatshade)) {
2424                                 tmp |= S_028644_FLAT_SHADE(1);
2425                         }
2426
2427                         if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2428                                         (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2429                                 tmp |= S_028644_PT_SPRITE_TEX(1);
2430                         }
2431
2432                         r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2433                                         tmp, NULL, 0);
2434
2435                         idx++;
2436                 }
2437         }
2438
2439         for (i = 0; i < rshader->noutput; i++) {
2440                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2441                         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2442                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2443                         db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2444         }
2445         if (rshader->uses_kill)
2446                 db_shader_control |= S_02880C_KILL_ENABLE(1);
2447
2448         exports_ps = 0;
2449         num_cout = 0;
2450         for (i = 0; i < rshader->noutput; i++) {
2451                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2452                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2453                         exports_ps |= 1;
2454                 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2455                         if (rshader->fs_write_all)
2456                                 num_cout = rshader->nr_cbufs;
2457                         else
2458                                 num_cout++;
2459                 }
2460         }
2461         exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2462         if (!exports_ps) {
2463                 /* always at least export 1 component per pixel */
2464                 exports_ps = 2;
2465         }
2466
2467         if (ninterp == 0) {
2468                 ninterp = 1;
2469                 have_perspective = TRUE;
2470         }
2471
2472         if (!have_perspective && !have_linear)
2473                 have_perspective = TRUE;
2474
2475         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2476                               S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2477                               S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2478         spi_input_z = 0;
2479         if (pos_index != -1) {
2480                 spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
2481                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2482                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2483                 spi_input_z |= 1;
2484         }
2485
2486         spi_ps_in_control_1 = 0;
2487         if (face_index != -1) {
2488                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2489                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2490         }
2491
2492         spi_baryc_cntl = 0;
2493         if (have_perspective)
2494                 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2495                                   S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2496         if (have_linear)
2497                 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2498                                   S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2499
2500         r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2501                                 spi_ps_in_control_0, NULL, 0);
2502         r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2503                                 spi_ps_in_control_1, NULL, 0);
2504         r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2505                                 0, NULL, 0);
2506         r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
2507         r600_pipe_state_add_reg(rstate,
2508                                 R_0286E0_SPI_BARYC_CNTL,
2509                                 spi_baryc_cntl,
2510                                 NULL, 0);
2511
2512         r600_pipe_state_add_reg(rstate,
2513                                 R_028840_SQ_PGM_START_PS,
2514                                 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2515                                 shader->bo, RADEON_USAGE_READ);
2516         r600_pipe_state_add_reg(rstate,
2517                                 R_028844_SQ_PGM_RESOURCES_PS,
2518                                 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2519                                 S_028844_PRIME_CACHE_ON_DRAW(1) |
2520                                 S_028844_STACK_SIZE(rshader->bc.nstack),
2521                                 NULL, 0);
2522         r600_pipe_state_add_reg(rstate,
2523                                 R_028848_SQ_PGM_RESOURCES_2_PS,
2524                                 S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2525                                 NULL, 0);
2526         r600_pipe_state_add_reg(rstate,
2527                                 R_02884C_SQ_PGM_EXPORTS_PS,
2528                                 exports_ps, NULL, 0);
2529         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2530                                 db_shader_control,
2531                                 NULL, 0);
2532         r600_pipe_state_add_reg(rstate,
2533                                 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
2534                                 NULL, 0);
2535
2536         shader->sprite_coord_enable = rctx->sprite_coord_enable;
2537         if (rctx->rasterizer)
2538                 shader->flatshade = rctx->rasterizer->flatshade;
2539 }
2540
2541 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2542 {
2543         struct r600_context *rctx = (struct r600_context *)ctx;
2544         struct r600_pipe_state *rstate = &shader->rstate;
2545         struct r600_shader *rshader = &shader->shader;
2546         unsigned spi_vs_out_id[10] = {};
2547         unsigned i, tmp, nparams = 0;
2548
2549         /* clear previous register */
2550         rstate->nregs = 0;
2551
2552         for (i = 0; i < rshader->noutput; i++) {
2553                 if (rshader->output[i].spi_sid) {
2554                         tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2555                         spi_vs_out_id[nparams / 4] |= tmp;
2556                         nparams++;
2557                 }
2558         }
2559
2560         for (i = 0; i < 10; i++) {
2561                 r600_pipe_state_add_reg(rstate,
2562                                         R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2563                                         spi_vs_out_id[i], NULL, 0);
2564         }
2565
2566         /* Certain attributes (position, psize, etc.) don't count as params.
2567          * VS is required to export at least one param and r600_shader_from_tgsi()
2568          * takes care of adding a dummy export.
2569          */
2570         if (nparams < 1)
2571                 nparams = 1;
2572
2573         r600_pipe_state_add_reg(rstate,
2574                         R_0286C4_SPI_VS_OUT_CONFIG,
2575                         S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2576                         NULL, 0);
2577         r600_pipe_state_add_reg(rstate,
2578                         R_028860_SQ_PGM_RESOURCES_VS,
2579                         S_028860_NUM_GPRS(rshader->bc.ngpr) |
2580                         S_028860_STACK_SIZE(rshader->bc.nstack),
2581                         NULL, 0);
2582         r600_pipe_state_add_reg(rstate,
2583                                 R_028864_SQ_PGM_RESOURCES_2_VS,
2584                                 S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2585                                 NULL, 0);
2586         r600_pipe_state_add_reg(rstate,
2587                         R_02885C_SQ_PGM_START_VS,
2588                         r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2589                         shader->bo, RADEON_USAGE_READ);
2590
2591         r600_pipe_state_add_reg(rstate,
2592                                 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2593                                 NULL, 0);
2594
2595         shader->pa_cl_vs_out_cntl =
2596                 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2597                 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2598                 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2599                 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2600 }
2601
2602 void evergreen_fetch_shader(struct pipe_context *ctx,
2603                             struct r600_vertex_element *ve)
2604 {
2605         struct r600_context *rctx = (struct r600_context *)ctx;
2606         struct r600_pipe_state *rstate = &ve->rstate;
2607         rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2608         rstate->nregs = 0;
2609         r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
2610                                 0x00000000, NULL, 0);
2611         r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2612                                 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2613                                 ve->fetch_shader, RADEON_USAGE_READ);
2614 }
2615
2616 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2617 {
2618         struct pipe_depth_stencil_alpha_state dsa;
2619         struct r600_pipe_state *rstate;
2620
2621         memset(&dsa, 0, sizeof(dsa));
2622
2623         rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2624         r600_pipe_state_add_reg(rstate,
2625                                 R_028000_DB_RENDER_CONTROL,
2626                                 S_028000_DEPTH_COPY_ENABLE(1) |
2627                                 S_028000_STENCIL_COPY_ENABLE(1) |
2628                                 S_028000_COPY_CENTROID(1),
2629                                 NULL, 0);
2630         return rstate;
2631 }
2632
2633 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
2634                                          struct r600_pipe_resource_state *rstate)
2635 {
2636         rstate->id = R600_PIPE_STATE_RESOURCE;
2637
2638         rstate->val[0] = 0;
2639         rstate->bo[0] = NULL;
2640         rstate->val[1] = 0;
2641         rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2642         rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2643           S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2644           S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2645           S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2646         rstate->val[4] = 0;
2647         rstate->val[5] = 0;
2648         rstate->val[6] = 0;
2649         rstate->val[7] = 0xc0000000;
2650 }
2651
2652
2653 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
2654                                         struct r600_pipe_resource_state *rstate,
2655                                         struct r600_resource *rbuffer,
2656                                         unsigned offset, unsigned stride,
2657                                         enum radeon_bo_usage usage)
2658 {
2659         uint64_t va;
2660
2661         va = r600_resource_va(ctx->screen, (void *)rbuffer);
2662         rstate->bo[0] = rbuffer;
2663         rstate->bo_usage[0] = usage;
2664         rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
2665         rstate->val[1] = rbuffer->buf->size - offset - 1;
2666         rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2667                          S_030008_STRIDE(stride) |
2668                          (((va + offset) >> 32UL) & 0xFF);
2669 }