src/gallium/drivers/r600/evergreen_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /* TODO:
  25  *      - fix mask for depth control & cull for query
  26  */
  27 #include <stdio.h>
  28 #include <errno.h>
  29 #include "pipe/p_defines.h"
  30 #include "pipe/p_state.h"
  31 #include "pipe/p_context.h"
  32 #include "tgsi/tgsi_scan.h"
  33 #include "tgsi/tgsi_parse.h"
  34 #include "tgsi/tgsi_util.h"
  35 #include "util/u_blitter.h"
  36 #include "util/u_double_list.h"
  37 #include "util/u_transfer.h"
  38 #include "util/u_surface.h"
  39 #include "util/u_pack_color.h"
  40 #include "util/u_memory.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_framebuffer.h"
  43 #include "pipebuffer/pb_buffer.h"
  44 #include "r600.h"
  45 #include "evergreend.h"
  46 #include "r600_resource.h"
  47 #include "r600_shader.h"
  48 #include "r600_pipe.h"
  49 #include "r600_formats.h"
  50
  51 static uint32_t eg_num_banks(uint32_t nbanks)
  52 {
  53         switch (nbanks) {
  54         case 2:
  55                 return 0;
  56         case 4:
  57                 return 1;
  58         case 8:
  59         default:
  60                 return 2;
  61         case 16:
  62                 return 3;
  63         }
  64 }
  65
  66
  67 static unsigned eg_tile_split(unsigned tile_split)
  68 {
  69         switch (tile_split) {
  70         case 64:        tile_split = 0; break;
  71         case 128:       tile_split = 1; break;
  72         case 256:       tile_split = 2; break;
  73         case 512:       tile_split = 3; break;
  74         default:
  75         case 1024:      tile_split = 4; break;
  76         case 2048:      tile_split = 5; break;
  77         case 4096:      tile_split = 6; break;
  78         }
  79         return tile_split;
  80 }
  81
  82 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
  83 {
  84         switch (macro_tile_aspect) {
  85         default:
  86         case 1: macro_tile_aspect = 0;  break;
  87         case 2: macro_tile_aspect = 1;  break;
  88         case 4: macro_tile_aspect = 2;  break;
  89         case 8: macro_tile_aspect = 3;  break;
  90         }
  91         return macro_tile_aspect;
  92 }
  93
  94 static unsigned eg_bank_wh(unsigned bankwh)
  95 {
  96         switch (bankwh) {
  97         default:
  98         case 1: bankwh = 0;     break;
  99         case 2: bankwh = 1;     break;
 100         case 4: bankwh = 2;     break;
 101         case 8: bankwh = 3;     break;
 102         }
 103         return bankwh;
 104 }
 105
 106 static uint32_t r600_translate_blend_function(int blend_func)
 107 {
 108         switch (blend_func) {
 109         case PIPE_BLEND_ADD:
 110                 return V_028780_COMB_DST_PLUS_SRC;
 111         case PIPE_BLEND_SUBTRACT:
 112                 return V_028780_COMB_SRC_MINUS_DST;
 113         case PIPE_BLEND_REVERSE_SUBTRACT:
 114                 return V_028780_COMB_DST_MINUS_SRC;
 115         case PIPE_BLEND_MIN:
 116                 return V_028780_COMB_MIN_DST_SRC;
 117         case PIPE_BLEND_MAX:
 118                 return V_028780_COMB_MAX_DST_SRC;
 119         default:
 120                 R600_ERR("Unknown blend function %d\n", blend_func);
 121                 assert(0);
 122                 break;
 123         }
 124         return 0;
 125 }
 126
 127 static uint32_t r600_translate_blend_factor(int blend_fact)
 128 {
 129         switch (blend_fact) {
 130         case PIPE_BLENDFACTOR_ONE:
 131                 return V_028780_BLEND_ONE;
 132         case PIPE_BLENDFACTOR_SRC_COLOR:
 133                 return V_028780_BLEND_SRC_COLOR;
 134         case PIPE_BLENDFACTOR_SRC_ALPHA:
 135                 return V_028780_BLEND_SRC_ALPHA;
 136         case PIPE_BLENDFACTOR_DST_ALPHA:
 137                 return V_028780_BLEND_DST_ALPHA;
 138         case PIPE_BLENDFACTOR_DST_COLOR:
 139                 return V_028780_BLEND_DST_COLOR;
 140         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
 141                 return V_028780_BLEND_SRC_ALPHA_SATURATE;
 142         case PIPE_BLENDFACTOR_CONST_COLOR:
 143                 return V_028780_BLEND_CONST_COLOR;
 144         case PIPE_BLENDFACTOR_CONST_ALPHA:
 145                 return V_028780_BLEND_CONST_ALPHA;
 146         case PIPE_BLENDFACTOR_ZERO:
 147                 return V_028780_BLEND_ZERO;
 148         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
 149                 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
 150         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
 151                 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
 152         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
 153                 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
 154         case PIPE_BLENDFACTOR_INV_DST_COLOR:
 155                 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
 156         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
 157                 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
 158         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
 159                 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
 160         case PIPE_BLENDFACTOR_SRC1_COLOR:
 161                 return V_028780_BLEND_SRC1_COLOR;
 162         case PIPE_BLENDFACTOR_SRC1_ALPHA:
 163                 return V_028780_BLEND_SRC1_ALPHA;
 164         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
 165                 return V_028780_BLEND_INV_SRC1_COLOR;
 166         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
 167                 return V_028780_BLEND_INV_SRC1_ALPHA;
 168         default:
 169                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
 170                 assert(0);
 171                 break;
 172         }
 173         return 0;
 174 }
 175
 176 static unsigned r600_tex_wrap(unsigned wrap)
 177 {
 178         switch (wrap) {
 179         default:
 180         case PIPE_TEX_WRAP_REPEAT:
 181                 return V_03C000_SQ_TEX_WRAP;
 182         case PIPE_TEX_WRAP_CLAMP:
 183                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
 184         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 185                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
 186         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 187                 return V_03C000_SQ_TEX_CLAMP_BORDER;
 188         case PIPE_TEX_WRAP_MIRROR_REPEAT:
 189                 return V_03C000_SQ_TEX_MIRROR;
 190         case PIPE_TEX_WRAP_MIRROR_CLAMP:
 191                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
 192         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
 193                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
 194         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 195                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
 196         }
 197 }
 198
 199 static unsigned r600_tex_filter(unsigned filter)
 200 {
 201         switch (filter) {
 202         default:
 203         case PIPE_TEX_FILTER_NEAREST:
 204                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
 205         case PIPE_TEX_FILTER_LINEAR:
 206                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
 207         }
 208 }
 209
 210 static unsigned r600_tex_mipfilter(unsigned filter)
 211 {
 212         switch (filter) {
 213         case PIPE_TEX_MIPFILTER_NEAREST:
 214                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
 215         case PIPE_TEX_MIPFILTER_LINEAR:
 216                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
 217         default:
 218         case PIPE_TEX_MIPFILTER_NONE:
 219                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
 220         }
 221 }
 222
 223 static unsigned r600_tex_compare(unsigned compare)
 224 {
 225         switch (compare) {
 226         default:
 227         case PIPE_FUNC_NEVER:
 228                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
 229         case PIPE_FUNC_LESS:
 230                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
 231         case PIPE_FUNC_EQUAL:
 232                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
 233         case PIPE_FUNC_LEQUAL:
 234                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
 235         case PIPE_FUNC_GREATER:
 236                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
 237         case PIPE_FUNC_NOTEQUAL:
 238                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
 239         case PIPE_FUNC_GEQUAL:
 240                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
 241         case PIPE_FUNC_ALWAYS:
 242                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
 243         }
 244 }
 245
 246 static unsigned r600_tex_dim(unsigned dim)
 247 {
 248         switch (dim) {
 249         default:
 250         case PIPE_TEXTURE_1D:
 251                 return V_030000_SQ_TEX_DIM_1D;
 252         case PIPE_TEXTURE_1D_ARRAY:
 253                 return V_030000_SQ_TEX_DIM_1D_ARRAY;
 254         case PIPE_TEXTURE_2D:
 255         case PIPE_TEXTURE_RECT:
 256                 return V_030000_SQ_TEX_DIM_2D;
 257         case PIPE_TEXTURE_2D_ARRAY:
 258                 return V_030000_SQ_TEX_DIM_2D_ARRAY;
 259         case PIPE_TEXTURE_3D:
 260                 return V_030000_SQ_TEX_DIM_3D;
 261         case PIPE_TEXTURE_CUBE:
 262                 return V_030000_SQ_TEX_DIM_CUBEMAP;
 263         }
 264 }
 265
 266 static uint32_t r600_translate_dbformat(enum pipe_format format)
 267 {
 268         switch (format) {
 269         case PIPE_FORMAT_Z16_UNORM:
 270                 return V_028040_Z_16;
 271         case PIPE_FORMAT_Z24X8_UNORM:
 272         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 273                 return V_028040_Z_24;
 274         case PIPE_FORMAT_Z32_FLOAT:
 275         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 276                 return V_028040_Z_32_FLOAT;
 277         default:
 278                 return ~0U;
 279         }
 280 }
 281
 282 static uint32_t r600_translate_colorswap(enum pipe_format format)
 283 {
 284         switch (format) {
 285         /* 8-bit buffers. */
 286         case PIPE_FORMAT_L4A4_UNORM:
 287         case PIPE_FORMAT_A4R4_UNORM:
 288                 return V_028C70_SWAP_ALT;
 289
 290         case PIPE_FORMAT_A8_UNORM:
 291         case PIPE_FORMAT_A8_UINT:
 292         case PIPE_FORMAT_A8_SINT:
 293         case PIPE_FORMAT_R4A4_UNORM:
 294                 return V_028C70_SWAP_ALT_REV;
 295         case PIPE_FORMAT_I8_UNORM:
 296         case PIPE_FORMAT_L8_UNORM:
 297         case PIPE_FORMAT_I8_UINT:
 298         case PIPE_FORMAT_I8_SINT:
 299         case PIPE_FORMAT_L8_UINT:
 300         case PIPE_FORMAT_L8_SINT:
 301         case PIPE_FORMAT_L8_SRGB:
 302         case PIPE_FORMAT_R8_UNORM:
 303         case PIPE_FORMAT_R8_SNORM:
 304         case PIPE_FORMAT_R8_UINT:
 305         case PIPE_FORMAT_R8_SINT:
 306                 return V_028C70_SWAP_STD;
 307
 308         /* 16-bit buffers. */
 309         case PIPE_FORMAT_B5G6R5_UNORM:
 310                 return V_028C70_SWAP_STD_REV;
 311
 312         case PIPE_FORMAT_B5G5R5A1_UNORM:
 313         case PIPE_FORMAT_B5G5R5X1_UNORM:
 314                 return V_028C70_SWAP_ALT;
 315
 316         case PIPE_FORMAT_B4G4R4A4_UNORM:
 317         case PIPE_FORMAT_B4G4R4X4_UNORM:
 318                 return V_028C70_SWAP_ALT;
 319
 320         case PIPE_FORMAT_Z16_UNORM:
 321                 return V_028C70_SWAP_STD;
 322
 323         case PIPE_FORMAT_L8A8_UNORM:
 324         case PIPE_FORMAT_L8A8_UINT:
 325         case PIPE_FORMAT_L8A8_SINT:
 326         case PIPE_FORMAT_L8A8_SRGB:
 327                 return V_028C70_SWAP_ALT;
 328         case PIPE_FORMAT_R8G8_UNORM:
 329         case PIPE_FORMAT_R8G8_UINT:
 330         case PIPE_FORMAT_R8G8_SINT:
 331                 return V_028C70_SWAP_STD;
 332
 333         case PIPE_FORMAT_R16_UNORM:
 334         case PIPE_FORMAT_R16_UINT:
 335         case PIPE_FORMAT_R16_SINT:
 336         case PIPE_FORMAT_R16_FLOAT:
 337                 return V_028C70_SWAP_STD;
 338
 339         /* 32-bit buffers. */
 340         case PIPE_FORMAT_A8B8G8R8_SRGB:
 341                 return V_028C70_SWAP_STD_REV;
 342         case PIPE_FORMAT_B8G8R8A8_SRGB:
 343                 return V_028C70_SWAP_ALT;
 344
 345         case PIPE_FORMAT_B8G8R8A8_UNORM:
 346         case PIPE_FORMAT_B8G8R8X8_UNORM:
 347                 return V_028C70_SWAP_ALT;
 348
 349         case PIPE_FORMAT_A8R8G8B8_UNORM:
 350         case PIPE_FORMAT_X8R8G8B8_UNORM:
 351                 return V_028C70_SWAP_ALT_REV;
 352         case PIPE_FORMAT_R8G8B8A8_SNORM:
 353         case PIPE_FORMAT_R8G8B8A8_UNORM:
 354         case PIPE_FORMAT_R8G8B8A8_SSCALED:
 355         case PIPE_FORMAT_R8G8B8A8_USCALED:
 356         case PIPE_FORMAT_R8G8B8A8_SINT:
 357         case PIPE_FORMAT_R8G8B8A8_UINT:
 358         case PIPE_FORMAT_R8G8B8X8_UNORM:
 359                 return V_028C70_SWAP_STD;
 360
 361         case PIPE_FORMAT_A8B8G8R8_UNORM:
 362         case PIPE_FORMAT_X8B8G8R8_UNORM:
 363         /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
 364                 return V_028C70_SWAP_STD_REV;
 365
 366         case PIPE_FORMAT_Z24X8_UNORM:
 367         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 368                 return V_028C70_SWAP_STD;
 369
 370         case PIPE_FORMAT_X8Z24_UNORM:
 371         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 372                 return V_028C70_SWAP_STD;
 373
 374         case PIPE_FORMAT_R10G10B10A2_UNORM:
 375         case PIPE_FORMAT_R10G10B10X2_SNORM:
 376         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 377                 return V_028C70_SWAP_STD;
 378
 379         case PIPE_FORMAT_B10G10R10A2_UNORM:
 380         case PIPE_FORMAT_B10G10R10A2_UINT:
 381                 return V_028C70_SWAP_ALT;
 382
 383         case PIPE_FORMAT_R11G11B10_FLOAT:
 384         case PIPE_FORMAT_R32_FLOAT:
 385         case PIPE_FORMAT_R32_UINT:
 386         case PIPE_FORMAT_R32_SINT:
 387         case PIPE_FORMAT_Z32_FLOAT:
 388         case PIPE_FORMAT_R16G16_FLOAT:
 389         case PIPE_FORMAT_R16G16_UNORM:
 390         case PIPE_FORMAT_R16G16_UINT:
 391         case PIPE_FORMAT_R16G16_SINT:
 392                 return V_028C70_SWAP_STD;
 393
 394         /* 64-bit buffers. */
 395         case PIPE_FORMAT_R32G32_FLOAT:
 396         case PIPE_FORMAT_R32G32_UINT:
 397         case PIPE_FORMAT_R32G32_SINT:
 398         case PIPE_FORMAT_R16G16B16A16_UNORM:
 399         case PIPE_FORMAT_R16G16B16A16_SNORM:
 400         case PIPE_FORMAT_R16G16B16A16_USCALED:
 401         case PIPE_FORMAT_R16G16B16A16_SSCALED:
 402         case PIPE_FORMAT_R16G16B16A16_UINT:
 403         case PIPE_FORMAT_R16G16B16A16_SINT:
 404         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 405         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 406
 407         /* 128-bit buffers. */
 408         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 409         case PIPE_FORMAT_R32G32B32A32_SNORM:
 410         case PIPE_FORMAT_R32G32B32A32_UNORM:
 411         case PIPE_FORMAT_R32G32B32A32_SSCALED:
 412         case PIPE_FORMAT_R32G32B32A32_USCALED:
 413         case PIPE_FORMAT_R32G32B32A32_SINT:
 414         case PIPE_FORMAT_R32G32B32A32_UINT:
 415                 return V_028C70_SWAP_STD;
 416         default:
 417                 R600_ERR("unsupported colorswap format %d\n", format);
 418                 return ~0U;
 419         }
 420         return ~0U;
 421 }
 422
 423 static uint32_t r600_translate_colorformat(enum pipe_format format)
 424 {
 425         switch (format) {
 426         /* 8-bit buffers. */
 427         case PIPE_FORMAT_A8_UNORM:
 428         case PIPE_FORMAT_A8_UINT:
 429         case PIPE_FORMAT_A8_SINT:
 430         case PIPE_FORMAT_I8_UNORM:
 431         case PIPE_FORMAT_I8_UINT:
 432         case PIPE_FORMAT_I8_SINT:
 433         case PIPE_FORMAT_L8_UNORM:
 434         case PIPE_FORMAT_L8_UINT:
 435         case PIPE_FORMAT_L8_SINT:
 436         case PIPE_FORMAT_L8_SRGB:
 437         case PIPE_FORMAT_R8_UNORM:
 438         case PIPE_FORMAT_R8_SNORM:
 439         case PIPE_FORMAT_R8_UINT:
 440         case PIPE_FORMAT_R8_SINT:
 441                 return V_028C70_COLOR_8;
 442
 443         /* 16-bit buffers. */
 444         case PIPE_FORMAT_B5G6R5_UNORM:
 445                 return V_028C70_COLOR_5_6_5;
 446
 447         case PIPE_FORMAT_B5G5R5A1_UNORM:
 448         case PIPE_FORMAT_B5G5R5X1_UNORM:
 449                 return V_028C70_COLOR_1_5_5_5;
 450
 451         case PIPE_FORMAT_B4G4R4A4_UNORM:
 452         case PIPE_FORMAT_B4G4R4X4_UNORM:
 453                 return V_028C70_COLOR_4_4_4_4;
 454
 455         case PIPE_FORMAT_Z16_UNORM:
 456                 return V_028C70_COLOR_16;
 457
 458         case PIPE_FORMAT_L8A8_UNORM:
 459         case PIPE_FORMAT_L8A8_UINT:
 460         case PIPE_FORMAT_L8A8_SINT:
 461         case PIPE_FORMAT_L8A8_SRGB:
 462         case PIPE_FORMAT_R8G8_UNORM:
 463         case PIPE_FORMAT_R8G8_UINT:
 464         case PIPE_FORMAT_R8G8_SINT:
 465                 return V_028C70_COLOR_8_8;
 466
 467         case PIPE_FORMAT_R16_UNORM:
 468         case PIPE_FORMAT_R16_UINT:
 469         case PIPE_FORMAT_R16_SINT:
 470                 return V_028C70_COLOR_16;
 471
 472         case PIPE_FORMAT_R16_FLOAT:
 473                 return V_028C70_COLOR_16_FLOAT;
 474
 475         /* 32-bit buffers. */
 476         case PIPE_FORMAT_A8B8G8R8_SRGB:
 477         case PIPE_FORMAT_A8B8G8R8_UNORM:
 478         case PIPE_FORMAT_A8R8G8B8_UNORM:
 479         case PIPE_FORMAT_B8G8R8A8_SRGB:
 480         case PIPE_FORMAT_B8G8R8A8_UNORM:
 481         case PIPE_FORMAT_B8G8R8X8_UNORM:
 482         case PIPE_FORMAT_R8G8B8A8_SNORM:
 483         case PIPE_FORMAT_R8G8B8A8_UNORM:
 484         case PIPE_FORMAT_R8G8B8X8_UNORM:
 485         case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
 486         case PIPE_FORMAT_X8B8G8R8_UNORM:
 487         case PIPE_FORMAT_X8R8G8B8_UNORM:
 488         case PIPE_FORMAT_R8G8B8_UNORM:
 489         case PIPE_FORMAT_R8G8B8A8_SSCALED:
 490         case PIPE_FORMAT_R8G8B8A8_USCALED:
 491         case PIPE_FORMAT_R8G8B8A8_SINT:
 492         case PIPE_FORMAT_R8G8B8A8_UINT:
 493                 return V_028C70_COLOR_8_8_8_8;
 494
 495         case PIPE_FORMAT_R10G10B10A2_UNORM:
 496         case PIPE_FORMAT_R10G10B10X2_SNORM:
 497         case PIPE_FORMAT_B10G10R10A2_UNORM:
 498         case PIPE_FORMAT_B10G10R10A2_UINT:
 499         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 500                 return V_028C70_COLOR_2_10_10_10;
 501
 502         case PIPE_FORMAT_Z24X8_UNORM:
 503         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 504                 return V_028C70_COLOR_8_24;
 505
 506         case PIPE_FORMAT_X8Z24_UNORM:
 507         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 508                 return V_028C70_COLOR_24_8;
 509
 510         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 511                 return V_028C70_COLOR_X24_8_32_FLOAT;
 512
 513         case PIPE_FORMAT_R32_UINT:
 514         case PIPE_FORMAT_R32_SINT:
 515                 return V_028C70_COLOR_32;
 516
 517         case PIPE_FORMAT_R32_FLOAT:
 518         case PIPE_FORMAT_Z32_FLOAT:
 519                 return V_028C70_COLOR_32_FLOAT;
 520
 521         case PIPE_FORMAT_R16G16_FLOAT:
 522                 return V_028C70_COLOR_16_16_FLOAT;
 523
 524         case PIPE_FORMAT_R16G16_SSCALED:
 525         case PIPE_FORMAT_R16G16_UNORM:
 526         case PIPE_FORMAT_R16G16_UINT:
 527         case PIPE_FORMAT_R16G16_SINT:
 528                 return V_028C70_COLOR_16_16;
 529
 530         case PIPE_FORMAT_R11G11B10_FLOAT:
 531                 return V_028C70_COLOR_10_11_11_FLOAT;
 532
 533         /* 64-bit buffers. */
 534         case PIPE_FORMAT_R16G16B16_USCALED:
 535         case PIPE_FORMAT_R16G16B16_SSCALED:
 536         case PIPE_FORMAT_R16G16B16A16_UINT:
 537         case PIPE_FORMAT_R16G16B16A16_SINT:
 538         case PIPE_FORMAT_R16G16B16A16_USCALED:
 539         case PIPE_FORMAT_R16G16B16A16_SSCALED:
 540         case PIPE_FORMAT_R16G16B16A16_UNORM:
 541         case PIPE_FORMAT_R16G16B16A16_SNORM:
 542                 return V_028C70_COLOR_16_16_16_16;
 543
 544         case PIPE_FORMAT_R16G16B16_FLOAT:
 545         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 546                 return V_028C70_COLOR_16_16_16_16_FLOAT;
 547
 548         case PIPE_FORMAT_R32G32_FLOAT:
 549                 return V_028C70_COLOR_32_32_FLOAT;
 550
 551         case PIPE_FORMAT_R32G32_USCALED:
 552         case PIPE_FORMAT_R32G32_SSCALED:
 553         case PIPE_FORMAT_R32G32_SINT:
 554         case PIPE_FORMAT_R32G32_UINT:
 555                 return V_028C70_COLOR_32_32;
 556
 557         /* 96-bit buffers. */
 558         case PIPE_FORMAT_R32G32B32_FLOAT:
 559                 return V_028C70_COLOR_32_32_32_FLOAT;
 560
 561         /* 128-bit buffers. */
 562         case PIPE_FORMAT_R32G32B32A32_SNORM:
 563         case PIPE_FORMAT_R32G32B32A32_UNORM:
 564         case PIPE_FORMAT_R32G32B32A32_SSCALED:
 565         case PIPE_FORMAT_R32G32B32A32_USCALED:
 566         case PIPE_FORMAT_R32G32B32A32_SINT:
 567         case PIPE_FORMAT_R32G32B32A32_UINT:
 568                 return V_028C70_COLOR_32_32_32_32;
 569         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 570                 return V_028C70_COLOR_32_32_32_32_FLOAT;
 571
 572         /* YUV buffers. */
 573         case PIPE_FORMAT_UYVY:
 574         case PIPE_FORMAT_YUYV:
 575         default:
 576                 return ~0U; /* Unsupported. */
 577         }
 578 }
 579
 580 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
 581 {
 582         if (R600_BIG_ENDIAN) {
 583                 switch(colorformat) {
 584
 585                 /* 8-bit buffers. */
 586                 case V_028C70_COLOR_8:
 587                         return ENDIAN_NONE;
 588
 589                 /* 16-bit buffers. */
 590                 case V_028C70_COLOR_5_6_5:
 591                 case V_028C70_COLOR_1_5_5_5:
 592                 case V_028C70_COLOR_4_4_4_4:
 593                 case V_028C70_COLOR_16:
 594                 case V_028C70_COLOR_8_8:
 595                         return ENDIAN_8IN16;
 596
 597                 /* 32-bit buffers. */
 598                 case V_028C70_COLOR_8_8_8_8:
 599                 case V_028C70_COLOR_2_10_10_10:
 600                 case V_028C70_COLOR_8_24:
 601                 case V_028C70_COLOR_24_8:
 602                 case V_028C70_COLOR_32_FLOAT:
 603                 case V_028C70_COLOR_16_16_FLOAT:
 604                 case V_028C70_COLOR_16_16:
 605                         return ENDIAN_8IN32;
 606
 607                 /* 64-bit buffers. */
 608                 case V_028C70_COLOR_16_16_16_16:
 609                 case V_028C70_COLOR_16_16_16_16_FLOAT:
 610                         return ENDIAN_8IN16;
 611
 612                 case V_028C70_COLOR_32_32_FLOAT:
 613                 case V_028C70_COLOR_32_32:
 614                 case V_028C70_COLOR_X24_8_32_FLOAT:
 615                         return ENDIAN_8IN32;
 616
 617                 /* 96-bit buffers. */
 618                 case V_028C70_COLOR_32_32_32_FLOAT:
 619                 /* 128-bit buffers. */
 620                 case V_028C70_COLOR_32_32_32_32_FLOAT:
 621                 case V_028C70_COLOR_32_32_32_32:
 622                         return ENDIAN_8IN32;
 623                 default:
 624                         return ENDIAN_NONE; /* Unsupported. */
 625                 }
 626         } else {
 627                 return ENDIAN_NONE;
 628         }
 629 }
 630
 631 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
 632 {
 633         return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
 634 }
 635
 636 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
 637 {
 638         return r600_translate_colorformat(format) != ~0U &&
 639                 r600_translate_colorswap(format) != ~0U;
 640 }
 641
 642 static bool r600_is_zs_format_supported(enum pipe_format format)
 643 {
 644         return r600_translate_dbformat(format) != ~0U;
 645 }
 646
 647 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 648                                       enum pipe_format format,
 649                                       enum pipe_texture_target target,
 650                                       unsigned sample_count,
 651                                       unsigned usage)
 652 {
 653         unsigned retval = 0;
 654
 655         if (target >= PIPE_MAX_TEXTURE_TYPES) {
 656                 R600_ERR("r600: unsupported texture type %d\n", target);
 657                 return FALSE;
 658         }
 659
 660         if (!util_format_is_supported(format, usage))
 661                 return FALSE;
 662
 663         /* Multisample */
 664         if (sample_count > 1)
 665                 return FALSE;
 666
 667         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 668             r600_is_sampler_format_supported(screen, format)) {
 669                 retval |= PIPE_BIND_SAMPLER_VIEW;
 670         }
 671
 672         if ((usage & (PIPE_BIND_RENDER_TARGET |
 673                       PIPE_BIND_DISPLAY_TARGET |
 674                       PIPE_BIND_SCANOUT |
 675                       PIPE_BIND_SHARED)) &&
 676             r600_is_colorbuffer_format_supported(format)) {
 677                 retval |= usage &
 678                           (PIPE_BIND_RENDER_TARGET |
 679                            PIPE_BIND_DISPLAY_TARGET |
 680                            PIPE_BIND_SCANOUT |
 681                            PIPE_BIND_SHARED);
 682         }
 683
 684         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 685             r600_is_zs_format_supported(format)) {
 686                 retval |= PIPE_BIND_DEPTH_STENCIL;
 687         }
 688
 689         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
 690             r600_is_vertex_format_supported(format)) {
 691                 retval |= PIPE_BIND_VERTEX_BUFFER;
 692         }
 693
 694         if (usage & PIPE_BIND_TRANSFER_READ)
 695                 retval |= PIPE_BIND_TRANSFER_READ;
 696         if (usage & PIPE_BIND_TRANSFER_WRITE)
 697                 retval |= PIPE_BIND_TRANSFER_WRITE;
 698
 699         return retval == usage;
 700 }
 701
 702 static void evergreen_set_blend_color(struct pipe_context *ctx,
 703                                         const struct pipe_blend_color *state)
 704 {
 705         struct r600_context *rctx = (struct r600_context *)ctx;
 706         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 707
 708         if (rstate == NULL)
 709                 return;
 710
 711         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 712         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
 713         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
 714         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
 715         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
 716
 717         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 718         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 719         r600_context_pipe_state_set(rctx, rstate);
 720 }
 721
 722 static void *evergreen_create_blend_state(struct pipe_context *ctx,
 723                                         const struct pipe_blend_state *state)
 724 {
 725         struct r600_context *rctx = (struct r600_context *)ctx;
 726         struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
 727         struct r600_pipe_state *rstate;
 728         uint32_t color_control, target_mask;
 729         /* FIXME there is more then 8 framebuffer */
 730         unsigned blend_cntl[8];
 731
 732         if (blend == NULL) {
 733                 return NULL;
 734         }
 735
 736         rstate = &blend->rstate;
 737
 738         rstate->id = R600_PIPE_STATE_BLEND;
 739
 740         target_mask = 0;
 741         color_control = S_028808_MODE(1);
 742         if (state->logicop_enable) {
 743                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 744         } else {
 745                 color_control |= (0xcc << 16);
 746         }
 747         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 748         if (state->independent_blend_enable) {
 749                 for (int i = 0; i < 8; i++) {
 750                         target_mask |= (state->rt[i].colormask << (4 * i));
 751                 }
 752         } else {
 753                 for (int i = 0; i < 8; i++) {
 754                         target_mask |= (state->rt[0].colormask << (4 * i));
 755                 }
 756         }
 757         blend->cb_target_mask = target_mask;
 758
 759         r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 760                                 color_control, NULL, 0);
 761
 762         if (rctx->chip_class != CAYMAN)
 763                 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, ~0, NULL, 0);
 764         else {
 765                 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0, NULL, 0);
 766                 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0, NULL, 0);
 767         }
 768
 769         for (int i = 0; i < 8; i++) {
 770                 /* state->rt entries > 0 only written if independent blending */
 771                 const int j = state->independent_blend_enable ? i : 0;
 772
 773                 unsigned eqRGB = state->rt[j].rgb_func;
 774                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 775                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 776                 unsigned eqA = state->rt[j].alpha_func;
 777                 unsigned srcA = state->rt[j].alpha_src_factor;
 778                 unsigned dstA = state->rt[j].alpha_dst_factor;
 779
 780                 blend_cntl[i] = 0;
 781                 if (!state->rt[j].blend_enable)
 782                         continue;
 783
 784                 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
 785                 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 786                 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 787                 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 788
 789                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 790                         blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
 791                         blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 792                         blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 793                         blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 794                 }
 795         }
 796         for (int i = 0; i < 8; i++) {
 797                 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0);
 798         }
 799
 800         return rstate;
 801 }
 802
 803 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
 804                                    const struct pipe_depth_stencil_alpha_state *state)
 805 {
 806         struct r600_context *rctx = (struct r600_context *)ctx;
 807         struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
 808         unsigned db_depth_control, alpha_test_control, alpha_ref;
 809         unsigned db_render_override, db_render_control;
 810         struct r600_pipe_state *rstate;
 811
 812         if (dsa == NULL) {
 813                 return NULL;
 814         }
 815
 816         dsa->valuemask[0] = state->stencil[0].valuemask;
 817         dsa->valuemask[1] = state->stencil[1].valuemask;
 818         dsa->writemask[0] = state->stencil[0].writemask;
 819         dsa->writemask[1] = state->stencil[1].writemask;
 820
 821         rstate = &dsa->rstate;
 822
 823         rstate->id = R600_PIPE_STATE_DSA;
 824         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 825                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 826                 S_028800_ZFUNC(state->depth.func);
 827
 828         /* stencil */
 829         if (state->stencil[0].enabled) {
 830                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 831                 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
 832                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 833                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 834                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 835
 836                 if (state->stencil[1].enabled) {
 837                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 838                         db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
 839                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 840                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 841                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 842                 }
 843         }
 844
 845         /* alpha */
 846         alpha_test_control = 0;
 847         alpha_ref = 0;
 848         if (state->alpha.enabled) {
 849                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 850                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 851                 alpha_ref = fui(state->alpha.ref_value);
 852         }
 853         dsa->alpha_ref = alpha_ref;
 854
 855         /* misc */
 856         db_render_control = 0;
 857         db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
 858                 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
 859                 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
 860         /* TODO db_render_override depends on query */
 861         r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0);
 862         r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0);
 863         r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
 864         r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, NULL, 0);
 865         r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
 866         /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
 867          * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
 868          * evergreen_pipe_shader_ps().*/
 869         r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
 870         r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, NULL, 0);
 871         r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, NULL, 0);
 872         r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, NULL, 0);
 873         r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, NULL, 0);
 874         r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0);
 875         dsa->db_render_override = db_render_override;
 876
 877         return rstate;
 878 }
 879
 880 static void *evergreen_create_rs_state(struct pipe_context *ctx,
 881                                         const struct pipe_rasterizer_state *state)
 882 {
 883         struct r600_context *rctx = (struct r600_context *)ctx;
 884         struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
 885         struct r600_pipe_state *rstate;
 886         unsigned tmp;
 887         unsigned prov_vtx = 1, polygon_dual_mode;
 888         unsigned clip_rule;
 889         float psize_min, psize_max;
 890
 891         if (rs == NULL) {
 892                 return NULL;
 893         }
 894
 895         polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
 896                                 state->fill_back != PIPE_POLYGON_MODE_FILL);
 897
 898         if (state->flatshade_first)
 899                 prov_vtx = 0;
 900
 901         rstate = &rs->rstate;
 902         rs->flatshade = state->flatshade;
 903         rs->sprite_coord_enable = state->sprite_coord_enable;
 904         rs->two_side = state->light_twoside;
 905         rs->clip_plane_enable = state->clip_plane_enable;
 906         rs->pa_sc_line_stipple = state->line_stipple_enable ?
 907                                 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
 908                                 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 909         rs->pa_su_sc_mode_cntl =
 910                 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 911                 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 912                 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 913                 S_028814_FACE(!state->front_ccw) |
 914                 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 915                 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 916                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 917                 S_028814_POLY_MODE(polygon_dual_mode) |
 918                 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 919                 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
 920         rs->pa_cl_clip_cntl =
 921                 S_028810_PS_UCP_MODE(3) |
 922                 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
 923                 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
 924                 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
 925
 926         clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
 927
 928         /* offset */
 929         rs->offset_units = state->offset_units;
 930         rs->offset_scale = state->offset_scale * 12.0f;
 931
 932         rstate->id = R600_PIPE_STATE_RASTERIZER;
 933         tmp = S_0286D4_FLAT_SHADE_ENA(1);
 934         if (state->sprite_coord_enable) {
 935                 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
 936                         S_0286D4_PNT_SPRITE_OVRD_X(2) |
 937                         S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 938                         S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 939                         S_0286D4_PNT_SPRITE_OVRD_W(1);
 940                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 941                         tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 942                 }
 943         }
 944         r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
 945
 946         r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0);
 947         /* point size 12.4 fixed point */
 948         tmp = (unsigned)(state->point_size * 8.0);
 949         r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
 950
 951         if (state->point_size_per_vertex) {
 952                 psize_min = util_get_min_point_size(state);
 953                 psize_max = 8192;
 954         } else {
 955                 /* Force the point size to be as if the vertex output was disabled. */
 956                 psize_min = state->point_size;
 957                 psize_max = state->point_size;
 958         }
 959         /* Divide by two, because 0.5 = 1 pixel. */
 960         r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
 961                                 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
 962                                 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
 963                                 NULL, 0);
 964
 965         tmp = (unsigned)state->line_width * 8;
 966         r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
 967         r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
 968                                 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
 969                                 NULL, 0);
 970
 971         if (rctx->chip_class == CAYMAN) {
 972                 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
 973                 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
 974                                         S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
 975                                         NULL, 0);
 976                 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
 977                 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
 978                 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
 979                 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
 980
 981
 982         } else {
 983                 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
 984
 985                 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
 986                 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
 987                 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
 988                 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
 989
 990                 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
 991                                         S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
 992                                         NULL, 0);
 993         }
 994         r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
 995         r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
 996         return rstate;
 997 }
 998
 999 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
1000                                         const struct pipe_sampler_state *state)
1001 {
1002         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1003         union util_color uc;
1004         unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
1005
1006         if (rstate == NULL) {
1007                 return NULL;
1008         }
1009
1010         rstate->id = R600_PIPE_STATE_SAMPLER;
1011         util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1012         r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1013                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1014                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1015                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1016                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1017                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1018                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1019                         S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1020                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1021                         S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
1022         r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1023                         S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1024                         S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
1025                         NULL, 0);
1026         r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
1027                                         S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1028                                         (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1029                                         S_03C008_TYPE(1),
1030                                         NULL, 0);
1031
1032         if (uc.ui) {
1033                 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
1034                 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
1035                 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
1036                 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
1037         }
1038         return rstate;
1039 }
1040
1041 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
1042                                                         struct pipe_resource *texture,
1043                                                         const struct pipe_sampler_view *state)
1044 {
1045         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
1046         struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1047         struct r600_pipe_resource_state *rstate;
1048         struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1049         unsigned format, endian;
1050         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1051         unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1052         unsigned height, depth, width;
1053         unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1054
1055         if (view == NULL)
1056                 return NULL;
1057         rstate = &view->state;
1058
1059         /* initialize base object */
1060         view->base = *state;
1061         view->base.texture = NULL;
1062         pipe_reference(NULL, &texture->reference);
1063         view->base.texture = texture;
1064         view->base.reference.count = 1;
1065         view->base.context = ctx;
1066
1067         swizzle[0] = state->swizzle_r;
1068         swizzle[1] = state->swizzle_g;
1069         swizzle[2] = state->swizzle_b;
1070         swizzle[3] = state->swizzle_a;
1071
1072         format = r600_translate_texformat(ctx->screen, state->format,
1073                                           swizzle,
1074                                           &word4, &yuv_format);
1075         if (format == ~0) {
1076                 format = 0;
1077         }
1078
1079         if (tmp->depth && !tmp->is_flushing_texture) {
1080                 r600_texture_depth_flush(ctx, texture, TRUE);
1081                 tmp = tmp->flushed_depth_texture;
1082         }
1083
1084         endian = r600_colorformat_endian_swap(format);
1085
1086         if (!rscreen->use_surface) {
1087                 height = texture->height0;
1088                 depth = texture->depth0;
1089                 width = texture->width0;
1090                 pitch = align(tmp->pitch_in_blocks[0] *
1091                                 util_format_get_blockwidth(state->format), 8);
1092                 array_mode = tmp->array_mode[0];
1093                 tile_type = tmp->tile_type;
1094                 tile_split = 0;
1095                 macro_aspect = 0;
1096                 bankw = 0;
1097                 bankh = 0;
1098         } else {
1099                 width = tmp->surface.level[0].npix_x;
1100                 height = tmp->surface.level[0].npix_y;
1101                 depth = tmp->surface.level[0].npix_z;
1102                 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1103                 tile_type = tmp->tile_type;
1104
1105                 switch (tmp->surface.level[0].mode) {
1106                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1107                         array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1108                         break;
1109                 case RADEON_SURF_MODE_2D:
1110                         array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1111                         break;
1112                 case RADEON_SURF_MODE_1D:
1113                         array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1114                         break;
1115                 case RADEON_SURF_MODE_LINEAR:
1116                 default:
1117                         array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1118                         break;
1119                 }
1120                 tile_split = tmp->surface.tile_split;
1121                 macro_aspect = tmp->surface.mtilea;
1122                 bankw = tmp->surface.bankw;
1123                 bankh = tmp->surface.bankh;
1124                 tile_split = eg_tile_split(tile_split);
1125                 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1126                 bankw = eg_bank_wh(bankw);
1127                 bankh = eg_bank_wh(bankh);
1128         }
1129         /* 128 bit formats require tile type = 1 */
1130         if (rscreen->chip_class == CAYMAN) {
1131                 if (util_format_get_blocksize(state->format) >= 16)
1132                         tile_type = 1;
1133         }
1134         nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1135
1136         if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1137                 height = 1;
1138                 depth = texture->array_size;
1139         } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1140                 depth = texture->array_size;
1141         }
1142
1143         rstate->bo[0] = &tmp->resource;
1144         rstate->bo[1] = &tmp->resource;
1145         rstate->bo_usage[0] = RADEON_USAGE_READ;
1146         rstate->bo_usage[1] = RADEON_USAGE_READ;
1147
1148         rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1149                           S_030000_PITCH((pitch / 8) - 1) |
1150                           S_030000_TEX_WIDTH(width - 1));
1151         if (rscreen->chip_class == CAYMAN)
1152                 rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1153         else
1154                 rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1155         rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1156                           S_030004_TEX_DEPTH(depth - 1) |
1157                           S_030004_ARRAY_MODE(array_mode));
1158         rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1159         if (state->u.tex.last_level) {
1160                 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1161         } else {
1162                 rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1163         }
1164         rstate->val[4] = (word4 |
1165                           S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1166                           S_030010_ENDIAN_SWAP(endian) |
1167                           S_030010_BASE_LEVEL(state->u.tex.first_level));
1168         rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1169                           S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1170                           S_030014_LAST_ARRAY(state->u.tex.last_layer));
1171         /* aniso max 16 samples */
1172         rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1173                          (S_030018_TILE_SPLIT(tile_split));
1174         rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1175                          S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1176                          S_03001C_BANK_WIDTH(bankw) |
1177                          S_03001C_BANK_HEIGHT(bankh) |
1178                          S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1179                          S_03001C_NUM_BANKS(nbanks);
1180
1181         return &view->base;
1182 }
1183
1184 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1185                                         struct pipe_sampler_view **views)
1186 {
1187         struct r600_context *rctx = (struct r600_context *)ctx;
1188         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1189
1190         for (int i = 0; i < count; i++) {
1191                 if (resource[i]) {
1192                         evergreen_context_pipe_state_set_vs_resource(rctx, &resource[i]->state,
1193                                                                      i + R600_MAX_CONST_BUFFERS);
1194                 }
1195         }
1196 }
1197
1198 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1199                                         struct pipe_sampler_view **views)
1200 {
1201         struct r600_context *rctx = (struct r600_context *)ctx;
1202         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1203         int i;
1204         int has_depth = 0;
1205
1206         for (i = 0; i < count; i++) {
1207                 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1208                         if (resource[i]) {
1209                                 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1210                                         has_depth = 1;
1211                                 evergreen_context_pipe_state_set_ps_resource(rctx, &resource[i]->state,
1212                                                                              i + R600_MAX_CONST_BUFFERS);
1213                         } else
1214                                 evergreen_context_pipe_state_set_ps_resource(rctx, NULL,
1215                                                                              i + R600_MAX_CONST_BUFFERS);
1216
1217                         pipe_sampler_view_reference(
1218                                 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1219                                 views[i]);
1220                 } else {
1221                         if (resource[i]) {
1222                                 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1223                                         has_depth = 1;
1224                         }
1225                 }
1226         }
1227         for (i = count; i < NUM_TEX_UNITS; i++) {
1228                 if (rctx->ps_samplers.views[i]) {
1229                         evergreen_context_pipe_state_set_ps_resource(rctx, NULL,
1230                                                                      i + R600_MAX_CONST_BUFFERS);
1231                         pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1232                 }
1233         }
1234         rctx->have_depth_texture = has_depth;
1235         rctx->ps_samplers.n_views = count;
1236 }
1237
1238 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1239 {
1240         struct r600_context *rctx = (struct r600_context *)ctx;
1241         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1242
1243         if (count)
1244                 r600_inval_texture_cache(rctx);
1245
1246         memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1247         rctx->ps_samplers.n_samplers = count;
1248
1249         for (int i = 0; i < count; i++) {
1250                 evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1251         }
1252 }
1253
1254 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1255 {
1256         struct r600_context *rctx = (struct r600_context *)ctx;
1257         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1258
1259         if (count)
1260                 r600_inval_texture_cache(rctx);
1261
1262         for (int i = 0; i < count; i++) {
1263                 evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1264         }
1265 }
1266
1267 static void evergreen_set_clip_state(struct pipe_context *ctx,
1268                                 const struct pipe_clip_state *state)
1269 {
1270         struct r600_context *rctx = (struct r600_context *)ctx;
1271         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1272         struct pipe_resource *cbuf;
1273
1274         if (rstate == NULL)
1275                 return;
1276
1277         rctx->clip = *state;
1278         rstate->id = R600_PIPE_STATE_CLIP;
1279         for (int i = 0; i < 6; i++) {
1280                 r600_pipe_state_add_reg(rstate,
1281                                         R_0285BC_PA_CL_UCP0_X + i * 16,
1282                                         fui(state->ucp[i][0]), NULL, 0);
1283                 r600_pipe_state_add_reg(rstate,
1284                                         R_0285C0_PA_CL_UCP0_Y + i * 16,
1285                                         fui(state->ucp[i][1]) , NULL, 0);
1286                 r600_pipe_state_add_reg(rstate,
1287                                         R_0285C4_PA_CL_UCP0_Z + i * 16,
1288                                         fui(state->ucp[i][2]), NULL, 0);
1289                 r600_pipe_state_add_reg(rstate,
1290                                         R_0285C8_PA_CL_UCP0_W + i * 16,
1291                                         fui(state->ucp[i][3]), NULL, 0);
1292         }
1293
1294         free(rctx->states[R600_PIPE_STATE_CLIP]);
1295         rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1296         r600_context_pipe_state_set(rctx, rstate);
1297
1298         cbuf = pipe_user_buffer_create(ctx->screen,
1299                                    state->ucp,
1300                                    4*4*8, /* 8*4 floats */
1301                                    PIPE_BIND_CONSTANT_BUFFER);
1302         r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1303         pipe_resource_reference(&cbuf, NULL);
1304 }
1305
1306 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1307                                          const struct pipe_poly_stipple *state)
1308 {
1309 }
1310
1311 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1312 {
1313 }
1314
1315 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1316                                         const struct pipe_scissor_state *state)
1317 {
1318         struct r600_context *rctx = (struct r600_context *)ctx;
1319         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1320         uint32_t tl, br;
1321
1322         if (rstate == NULL)
1323                 return;
1324
1325         rstate->id = R600_PIPE_STATE_SCISSOR;
1326         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1327         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1328         r600_pipe_state_add_reg(rstate,
1329                                 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1330                                 NULL, 0);
1331         r600_pipe_state_add_reg(rstate,
1332                                 R_028214_PA_SC_CLIPRECT_0_BR, br,
1333                                 NULL, 0);
1334         r600_pipe_state_add_reg(rstate,
1335                                 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1336                                 NULL, 0);
1337         r600_pipe_state_add_reg(rstate,
1338                                 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1339                                 NULL, 0);
1340         r600_pipe_state_add_reg(rstate,
1341                                 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1342                                 NULL, 0);
1343         r600_pipe_state_add_reg(rstate,
1344                                 R_028224_PA_SC_CLIPRECT_2_BR, br,
1345                                 NULL, 0);
1346         r600_pipe_state_add_reg(rstate,
1347                                 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1348                                 NULL, 0);
1349         r600_pipe_state_add_reg(rstate,
1350                                 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1351                                 NULL, 0);
1352
1353         free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1354         rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1355         r600_context_pipe_state_set(rctx, rstate);
1356 }
1357
1358 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1359                                         const struct pipe_viewport_state *state)
1360 {
1361         struct r600_context *rctx = (struct r600_context *)ctx;
1362         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1363
1364         if (rstate == NULL)
1365                 return;
1366
1367         rctx->viewport = *state;
1368         rstate->id = R600_PIPE_STATE_VIEWPORT;
1369         r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0);
1370         r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0);
1371         r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1372         r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1373         r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1374         r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1375         r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1376         r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1377         r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0);
1378
1379         free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1380         rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1381         r600_context_pipe_state_set(rctx, rstate);
1382 }
1383
1384 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1385                          const struct pipe_framebuffer_state *state, int cb)
1386 {
1387         struct r600_screen *rscreen = rctx->screen;
1388         struct r600_resource_texture *rtex;
1389         struct r600_surface *surf;
1390         unsigned level = state->cbufs[cb]->u.tex.level;
1391         unsigned pitch, slice;
1392         unsigned color_info, color_attrib;
1393         unsigned format, swap, ntype, endian;
1394         uint64_t offset;
1395         unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1396         const struct util_format_description *desc;
1397         int i;
1398         unsigned blend_clamp = 0, blend_bypass = 0;
1399
1400         surf = (struct r600_surface *)state->cbufs[cb];
1401         rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1402
1403         if (rtex->depth)
1404                 rctx->have_depth_fb = TRUE;
1405
1406         if (rtex->depth && !rtex->is_flushing_texture) {
1407                 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1408                 rtex = rtex->flushed_depth_texture;
1409         }
1410
1411         /* XXX quite sure for dx10+ hw don't need any offset hacks */
1412         if (!rscreen->use_surface) {
1413                 offset = r600_texture_get_offset(rtex,
1414                                 level, state->cbufs[cb]->u.tex.first_layer);
1415                 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1416                 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1417                 if (slice) {
1418                         slice = slice - 1;
1419                 }
1420                 color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1421                 tile_split = 0;
1422                 macro_aspect = 0;
1423                 bankw = 0;
1424                 bankh = 0;
1425                 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1426                         tile_type = rtex->tile_type;
1427                 } else {
1428                         /* workaround for linear buffers */
1429                         tile_type = 1;
1430                 }
1431         } else {
1432                 offset = rtex->surface.level[level].offset;
1433                 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1434                         offset += rtex->surface.level[level].slice_size *
1435                                   state->cbufs[cb]->u.tex.first_layer;
1436                 }
1437                 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1438                 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1439                 if (slice) {
1440                         slice = slice - 1;
1441                 }
1442                 color_info = 0;
1443                 switch (rtex->surface.level[level].mode) {
1444                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1445                         color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1446                         tile_type = 1;
1447                         break;
1448                 case RADEON_SURF_MODE_1D:
1449                         color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1450                         tile_type = rtex->tile_type;
1451                         break;
1452                 case RADEON_SURF_MODE_2D:
1453                         color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1454                         tile_type = rtex->tile_type;
1455                         break;
1456                 case RADEON_SURF_MODE_LINEAR:
1457                 default:
1458                         color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1459                         tile_type = 1;
1460                         break;
1461                 }
1462                 tile_split = rtex->surface.tile_split;
1463                 macro_aspect = rtex->surface.mtilea;
1464                 bankw = rtex->surface.bankw;
1465                 bankh = rtex->surface.bankh;
1466                 tile_split = eg_tile_split(tile_split);
1467                 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1468                 bankw = eg_bank_wh(bankw);
1469                 bankh = eg_bank_wh(bankh);
1470         }
1471         /* 128 bit formats require tile type = 1 */
1472         if (rscreen->chip_class == CAYMAN) {
1473                 if (util_format_get_blocksize(surf->base.format) >= 16)
1474                         tile_type = 1;
1475         }
1476         nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1477         desc = util_format_description(surf->base.format);
1478         for (i = 0; i < 4; i++) {
1479                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1480                         break;
1481                 }
1482         }
1483
1484         color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1485                         S_028C74_NUM_BANKS(nbanks) |
1486                         S_028C74_BANK_WIDTH(bankw) |
1487                         S_028C74_BANK_HEIGHT(bankh) |
1488                         S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1489                         S_028C74_NON_DISP_TILING_ORDER(tile_type);
1490
1491         ntype = V_028C70_NUMBER_UNORM;
1492         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1493                 ntype = V_028C70_NUMBER_SRGB;
1494         else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1495                 if (desc->channel[i].normalized)
1496                         ntype = V_028C70_NUMBER_SNORM;
1497                 else if (desc->channel[i].pure_integer)
1498                         ntype = V_028C70_NUMBER_SINT;
1499         } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1500                 if (desc->channel[i].normalized)
1501                         ntype = V_028C70_NUMBER_UNORM;
1502                 else if (desc->channel[i].pure_integer)
1503                         ntype = V_028C70_NUMBER_UINT;
1504         }
1505
1506         format = r600_translate_colorformat(surf->base.format);
1507         swap = r600_translate_colorswap(surf->base.format);
1508         if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1509                 endian = ENDIAN_NONE;
1510         } else {
1511                 endian = r600_colorformat_endian_swap(format);
1512         }
1513
1514         /* blend clamp should be set for all NORM/SRGB types */
1515         if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1516             ntype == V_028C70_NUMBER_SRGB)
1517                 blend_clamp = 1;
1518
1519         /* set blend bypass according to docs if SINT/UINT or
1520            8/24 COLOR variants */
1521         if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1522             format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1523             format == V_028C70_COLOR_X24_8_32_FLOAT) {
1524                 blend_clamp = 0;
1525                 blend_bypass = 1;
1526         }
1527
1528         color_info |= S_028C70_FORMAT(format) |
1529                 S_028C70_COMP_SWAP(swap) |
1530                 S_028C70_BLEND_CLAMP(blend_clamp) |
1531                 S_028C70_BLEND_BYPASS(blend_bypass) |
1532                 S_028C70_NUMBER_TYPE(ntype) |
1533                 S_028C70_ENDIAN(endian);
1534
1535         /* EXPORT_NORM is an optimzation that can be enabled for better
1536          * performance in certain cases.
1537          * EXPORT_NORM can be enabled if:
1538          * - 11-bit or smaller UNORM/SNORM/SRGB
1539          * - 16-bit or smaller FLOAT
1540          */
1541         /* FIXME: This should probably be the same for all CBs if we want
1542          * useful alpha tests. */
1543         if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1544             ((desc->channel[i].size < 12 &&
1545               desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1546               ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1547              (desc->channel[i].size < 17 &&
1548               desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1549                 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1550                 rctx->export_16bpc = true;
1551         } else {
1552                 rctx->export_16bpc = false;
1553         }
1554         rctx->alpha_ref_dirty = true;
1555
1556
1557         offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1558         offset >>= 8;
1559
1560         /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1561         r600_pipe_state_add_reg(rstate,
1562                                 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1563                                 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1564         r600_pipe_state_add_reg(rstate,
1565                                 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1566                                 0x0, NULL, 0);
1567         r600_pipe_state_add_reg(rstate,
1568                                 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1569                                 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1570         r600_pipe_state_add_reg(rstate,
1571                                 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1572                                 S_028C64_PITCH_TILE_MAX(pitch),
1573                                 NULL, 0);
1574         r600_pipe_state_add_reg(rstate,
1575                                 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1576                                 S_028C68_SLICE_TILE_MAX(slice),
1577                                 NULL, 0);
1578         if (!rscreen->use_surface) {
1579                 r600_pipe_state_add_reg(rstate,
1580                                         R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1581                                         0x00000000, NULL, 0);
1582         } else {
1583                 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1584                         r600_pipe_state_add_reg(rstate,
1585                                                 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1586                                                 0x00000000, NULL, 0);
1587                 } else {
1588                         r600_pipe_state_add_reg(rstate,
1589                                                 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1590                                                 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1591                                                 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1592                                                 NULL, 0);
1593                 }
1594         }
1595         r600_pipe_state_add_reg(rstate,
1596                                 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1597                                 color_attrib,
1598                                 &rtex->resource, RADEON_USAGE_READWRITE);
1599 }
1600
1601 static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1602                          const struct pipe_framebuffer_state *state)
1603 {
1604         struct r600_screen *rscreen = rctx->screen;
1605         struct r600_resource_texture *rtex;
1606         struct r600_surface *surf;
1607         uint64_t offset;
1608         unsigned level, first_layer, pitch, slice, format, array_mode;
1609         unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1610
1611         if (state->zsbuf == NULL)
1612                 return;
1613
1614         surf = (struct r600_surface *)state->zsbuf;
1615         level = surf->base.u.tex.level;
1616         rtex = (struct r600_resource_texture*)surf->base.texture;
1617         first_layer = surf->base.u.tex.first_layer;
1618         format = r600_translate_dbformat(rtex->real_format);
1619
1620         offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1621         /* XXX remove this once tiling is properly supported */
1622         if (!rscreen->use_surface) {
1623                 /* XXX remove this once tiling is properly supported */
1624                 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1625                                 V_028C70_ARRAY_1D_TILED_THIN1;
1626
1627                 offset += r600_texture_get_offset(rtex, level, first_layer);
1628                 pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1629                 slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1630                 if (slice) {
1631                         slice = slice - 1;
1632                 }
1633                 tile_split = 0;
1634                 macro_aspect = 0;
1635                 bankw = 0;
1636                 bankh = 0;
1637         } else {
1638                 offset += rtex->surface.level[level].offset;
1639                 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1640                 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1641                 if (slice) {
1642                         slice = slice - 1;
1643                 }
1644                 switch (rtex->surface.level[level].mode) {
1645                 case RADEON_SURF_MODE_2D:
1646                         array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1647                         break;
1648                 case RADEON_SURF_MODE_1D:
1649                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1650                 case RADEON_SURF_MODE_LINEAR:
1651                 default:
1652                         array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1653                         break;
1654                 }
1655                 tile_split = rtex->surface.tile_split;
1656                 macro_aspect = rtex->surface.mtilea;
1657                 bankw = rtex->surface.bankw;
1658                 bankh = rtex->surface.bankh;
1659                 tile_split = eg_tile_split(tile_split);
1660                 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1661                 bankw = eg_bank_wh(bankw);
1662                 bankh = eg_bank_wh(bankh);
1663         }
1664         nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1665         offset >>= 8;
1666
1667         z_info = S_028040_ARRAY_MODE(array_mode) |
1668                  S_028040_FORMAT(format) |
1669                  S_028040_TILE_SPLIT(tile_split)|
1670                  S_028040_NUM_BANKS(nbanks) |
1671                  S_028040_BANK_WIDTH(bankw) |
1672                  S_028040_BANK_HEIGHT(bankh) |
1673                  S_028040_MACRO_TILE_ASPECT(macro_aspect);
1674
1675         r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1676                                 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1677         r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1678                                 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1679         if (!rscreen->use_surface) {
1680                 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1681                                         0x00000000, NULL, 0);
1682         } else {
1683                 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1684                                         S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1685                                         S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1686                                         NULL, 0);
1687         }
1688
1689         if (rtex->stencil) {
1690                 uint64_t stencil_offset =
1691                         r600_texture_get_offset(rtex->stencil, level, first_layer);
1692                 unsigned stile_split;
1693
1694                 stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1695                 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1696                 stencil_offset >>= 8;
1697
1698                 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1699                                         stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1700                 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1701                                         stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1702                 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1703                                         1 | S_028044_TILE_SPLIT(stile_split),
1704                                         &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1705         } else {
1706                 if (rscreen->use_surface && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1707                         uint64_t stencil_offset = rtex->surface.stencil_offset;
1708                         unsigned stile_split = rtex->surface.stencil_tile_split;
1709
1710                         stile_split = eg_tile_split(stile_split);
1711                         stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1712                         stencil_offset += rtex->surface.level[level].offset / 4;
1713                         stencil_offset >>= 8;
1714
1715                         r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1716                                                 stencil_offset, &rtex->resource,
1717                                                 RADEON_USAGE_READWRITE);
1718                         r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1719                                                 stencil_offset, &rtex->resource,
1720                                                 RADEON_USAGE_READWRITE);
1721                         r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1722                                                 1 | S_028044_TILE_SPLIT(stile_split),
1723                                                 &rtex->resource,
1724                                                 RADEON_USAGE_READWRITE);
1725                 } else {
1726                         r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1727                                                 offset, &rtex->resource,
1728                                                 RADEON_USAGE_READWRITE);
1729                         r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1730                                                 offset, &rtex->resource,
1731                                                 RADEON_USAGE_READWRITE);
1732                         r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1733                                                 0, NULL, RADEON_USAGE_READWRITE);
1734                 }
1735         }
1736
1737         r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, z_info,
1738                                 &rtex->resource, RADEON_USAGE_READWRITE);
1739         r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1740                                 S_028058_PITCH_TILE_MAX(pitch),
1741                                 NULL, 0);
1742         r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1743                                 S_02805C_SLICE_TILE_MAX(slice),
1744                                 NULL, 0);
1745 }
1746
1747 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1748                                         const struct pipe_framebuffer_state *state)
1749 {
1750         struct r600_context *rctx = (struct r600_context *)ctx;
1751         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1752         uint32_t shader_mask, tl, br;
1753         int tl_x, tl_y, br_x, br_y;
1754
1755         if (rstate == NULL)
1756                 return;
1757
1758         r600_flush_framebuffer(rctx, false);
1759
1760         /* unreference old buffer and reference new one */
1761         rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1762
1763         util_copy_framebuffer_state(&rctx->framebuffer, state);
1764
1765         /* build states */
1766         rctx->have_depth_fb = 0;
1767         rctx->nr_cbufs = state->nr_cbufs;
1768         for (int i = 0; i < state->nr_cbufs; i++) {
1769                 evergreen_cb(rctx, rstate, state, i);
1770         }
1771         if (state->zsbuf) {
1772                 evergreen_db(rctx, rstate, state);
1773         }
1774
1775         shader_mask = 0;
1776         for (int i = 0; i < state->nr_cbufs; i++) {
1777                 shader_mask |= 0xf << (i * 4);
1778         }
1779         tl_x = 0;
1780         tl_y = 0;
1781         br_x = state->width;
1782         br_y = state->height;
1783         /* EG hw workaround */
1784         if (br_x == 0)
1785                 tl_x = 1;
1786         if (br_y == 0)
1787                 tl_y = 1;
1788         /* cayman hw workaround */
1789         if (rctx->chip_class == CAYMAN) {
1790                 if (br_x == 1 && br_y == 1)
1791                         br_x = 2;
1792         }
1793         tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1794         br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1795
1796         r600_pipe_state_add_reg(rstate,
1797                                 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1798                                 NULL, 0);
1799         r600_pipe_state_add_reg(rstate,
1800                                 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1801                                 NULL, 0);
1802         r600_pipe_state_add_reg(rstate,
1803                                 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1804                                 NULL, 0);
1805         r600_pipe_state_add_reg(rstate,
1806                                 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1807                                 NULL, 0);
1808         r600_pipe_state_add_reg(rstate,
1809                                 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1810                                 NULL, 0);
1811         r600_pipe_state_add_reg(rstate,
1812                                 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1813                                 NULL, 0);
1814         r600_pipe_state_add_reg(rstate,
1815                                 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1816                                 NULL, 0);
1817         r600_pipe_state_add_reg(rstate,
1818                                 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1819                                 NULL, 0);
1820         r600_pipe_state_add_reg(rstate,
1821                                 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1822                                 NULL, 0);
1823         r600_pipe_state_add_reg(rstate,
1824                                 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1825                                 NULL, 0);
1826         r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1827                                 shader_mask, NULL, 0);
1828
1829
1830         if (rctx->chip_class == CAYMAN) {
1831                 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1832                                         0x00000000, NULL, 0);
1833         } else {
1834                 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1835                                         0x00000000, NULL, 0);
1836                 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0,
1837                                         0x00000000, NULL, 0);
1838         }
1839
1840         free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1841         rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1842         r600_context_pipe_state_set(rctx, rstate);
1843
1844         if (state->zsbuf) {
1845                 evergreen_polygon_offset_update(rctx);
1846         }
1847 }
1848
1849 void evergreen_init_state_functions(struct r600_context *rctx)
1850 {
1851         rctx->context.create_blend_state = evergreen_create_blend_state;
1852         rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1853         rctx->context.create_fs_state = r600_create_shader_state;
1854         rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1855         rctx->context.create_sampler_state = evergreen_create_sampler_state;
1856         rctx->context.create_sampler_view = evergreen_create_sampler_view;
1857         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1858         rctx->context.create_vs_state = r600_create_shader_state;
1859         rctx->context.bind_blend_state = r600_bind_blend_state;
1860         rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1861         rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1862         rctx->context.bind_fs_state = r600_bind_ps_shader;
1863         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1864         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1865         rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1866         rctx->context.bind_vs_state = r600_bind_vs_shader;
1867         rctx->context.delete_blend_state = r600_delete_state;
1868         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1869         rctx->context.delete_fs_state = r600_delete_ps_shader;
1870         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1871         rctx->context.delete_sampler_state = r600_delete_state;
1872         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1873         rctx->context.delete_vs_state = r600_delete_vs_shader;
1874         rctx->context.set_blend_color = evergreen_set_blend_color;
1875         rctx->context.set_clip_state = evergreen_set_clip_state;
1876         rctx->context.set_constant_buffer = r600_set_constant_buffer;
1877         rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1878         rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1879         rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1880         rctx->context.set_sample_mask = evergreen_set_sample_mask;
1881         rctx->context.set_scissor_state = evergreen_set_scissor_state;
1882         rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1883         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1884         rctx->context.set_index_buffer = r600_set_index_buffer;
1885         rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1886         rctx->context.set_viewport_state = evergreen_set_viewport_state;
1887         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1888         rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1889         rctx->context.texture_barrier = r600_texture_barrier;
1890         rctx->context.create_stream_output_target = r600_create_so_target;
1891         rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1892         rctx->context.set_stream_output_targets = r600_set_so_targets;
1893 }
1894
1895 static void cayman_init_config(struct r600_context *rctx)
1896 {
1897         struct r600_pipe_state *rstate = &rctx->config;
1898         unsigned tmp;
1899
1900         tmp = 0x00000000;
1901         tmp |= S_008C00_EXPORT_SRC_C(1);
1902         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
1903
1904         /* always set the temp clauses */
1905         r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), NULL, 0);
1906         r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, NULL, 0);
1907         r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, NULL, 0);
1908         r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), NULL, 0);
1909
1910         r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
1911
1912         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
1913         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
1914         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
1915         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
1916         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
1917         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
1918         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
1919         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
1920         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
1921         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
1922         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
1923         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
1924         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
1925         r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
1926         r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
1927         r600_pipe_state_add_reg(rstate, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), NULL, 0);
1928         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
1929         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
1930         r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
1931
1932         r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, NULL, 0);
1933         r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, NULL, 0);
1934         r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, NULL, 0);
1935         r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, NULL, 0);
1936         r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, NULL, 0);
1937         r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, NULL, 0);
1938         r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, NULL, 0);
1939         r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, NULL, 0);
1940         r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, NULL, 0);
1941         r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, NULL, 0);
1942         r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, NULL, 0);
1943         r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, NULL, 0);
1944         r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, NULL, 0);
1945         r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, NULL, 0);
1946         r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, NULL, 0);
1947         r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, NULL, 0);
1948         r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, NULL, 0);
1949         r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, NULL, 0);
1950         r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, NULL, 0);
1951         r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, NULL, 0);
1952         r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, NULL, 0);
1953         r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, NULL, 0);
1954         r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, NULL, 0);
1955         r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, NULL, 0);
1956         r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, NULL, 0);
1957         r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, NULL, 0);
1958         r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, NULL, 0);
1959         r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, NULL, 0);
1960         r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, NULL, 0);
1961         r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, NULL, 0);
1962         r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, NULL, 0);
1963         r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, NULL, 0);
1964
1965         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
1966
1967         r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, NULL, 0);
1968         r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, NULL, 0);
1969
1970         r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, NULL, 0);
1971         r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, NULL, 0);
1972
1973         r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, NULL, 0);
1974         r600_context_pipe_state_set(rctx, rstate);
1975 }
1976
1977 void evergreen_init_config(struct r600_context *rctx)
1978 {
1979         struct r600_pipe_state *rstate = &rctx->config;
1980         int ps_prio;
1981         int vs_prio;
1982         int gs_prio;
1983         int es_prio;
1984         int hs_prio, cs_prio, ls_prio;
1985         int num_ps_gprs;
1986         int num_vs_gprs;
1987         int num_gs_gprs;
1988         int num_es_gprs;
1989         int num_hs_gprs;
1990         int num_ls_gprs;
1991         int num_temp_gprs;
1992         int num_ps_threads;
1993         int num_vs_threads;
1994         int num_gs_threads;
1995         int num_es_threads;
1996         int num_hs_threads;
1997         int num_ls_threads;
1998         int num_ps_stack_entries;
1999         int num_vs_stack_entries;
2000         int num_gs_stack_entries;
2001         int num_es_stack_entries;
2002         int num_hs_stack_entries;
2003         int num_ls_stack_entries;
2004         enum radeon_family family;
2005         unsigned tmp;
2006
2007         family = rctx->family;
2008
2009         if (rctx->chip_class == CAYMAN) {
2010                 cayman_init_config(rctx);
2011                 return;
2012         }
2013
2014         ps_prio = 0;
2015         vs_prio = 1;
2016         gs_prio = 2;
2017         es_prio = 3;
2018         hs_prio = 0;
2019         ls_prio = 0;
2020         cs_prio = 0;
2021
2022         switch (family) {
2023         case CHIP_CEDAR:
2024         default:
2025                 num_ps_gprs = 93;
2026                 num_vs_gprs = 46;
2027                 num_temp_gprs = 4;
2028                 num_gs_gprs = 31;
2029                 num_es_gprs = 31;
2030                 num_hs_gprs = 23;
2031                 num_ls_gprs = 23;
2032                 num_ps_threads = 96;
2033                 num_vs_threads = 16;
2034                 num_gs_threads = 16;
2035                 num_es_threads = 16;
2036                 num_hs_threads = 16;
2037                 num_ls_threads = 16;
2038                 num_ps_stack_entries = 42;
2039                 num_vs_stack_entries = 42;
2040                 num_gs_stack_entries = 42;
2041                 num_es_stack_entries = 42;
2042                 num_hs_stack_entries = 42;
2043                 num_ls_stack_entries = 42;
2044                 break;
2045         case CHIP_REDWOOD:
2046                 num_ps_gprs = 93;
2047                 num_vs_gprs = 46;
2048                 num_temp_gprs = 4;
2049                 num_gs_gprs = 31;
2050                 num_es_gprs = 31;
2051                 num_hs_gprs = 23;
2052                 num_ls_gprs = 23;
2053                 num_ps_threads = 128;
2054                 num_vs_threads = 20;
2055                 num_gs_threads = 20;
2056                 num_es_threads = 20;
2057                 num_hs_threads = 20;
2058                 num_ls_threads = 20;
2059                 num_ps_stack_entries = 42;
2060                 num_vs_stack_entries = 42;
2061                 num_gs_stack_entries = 42;
2062                 num_es_stack_entries = 42;
2063                 num_hs_stack_entries = 42;
2064                 num_ls_stack_entries = 42;
2065                 break;
2066         case CHIP_JUNIPER:
2067                 num_ps_gprs = 93;
2068                 num_vs_gprs = 46;
2069                 num_temp_gprs = 4;
2070                 num_gs_gprs = 31;
2071                 num_es_gprs = 31;
2072                 num_hs_gprs = 23;
2073                 num_ls_gprs = 23;
2074                 num_ps_threads = 128;
2075                 num_vs_threads = 20;
2076                 num_gs_threads = 20;
2077                 num_es_threads = 20;
2078                 num_hs_threads = 20;
2079                 num_ls_threads = 20;
2080                 num_ps_stack_entries = 85;
2081                 num_vs_stack_entries = 85;
2082                 num_gs_stack_entries = 85;
2083                 num_es_stack_entries = 85;
2084                 num_hs_stack_entries = 85;
2085                 num_ls_stack_entries = 85;
2086                 break;
2087         case CHIP_CYPRESS:
2088         case CHIP_HEMLOCK:
2089                 num_ps_gprs = 93;
2090                 num_vs_gprs = 46;
2091                 num_temp_gprs = 4;
2092                 num_gs_gprs = 31;
2093                 num_es_gprs = 31;
2094                 num_hs_gprs = 23;
2095                 num_ls_gprs = 23;
2096                 num_ps_threads = 128;
2097                 num_vs_threads = 20;
2098                 num_gs_threads = 20;
2099                 num_es_threads = 20;
2100                 num_hs_threads = 20;
2101                 num_ls_threads = 20;
2102                 num_ps_stack_entries = 85;
2103                 num_vs_stack_entries = 85;
2104                 num_gs_stack_entries = 85;
2105                 num_es_stack_entries = 85;
2106                 num_hs_stack_entries = 85;
2107                 num_ls_stack_entries = 85;
2108                 break;
2109         case CHIP_PALM:
2110                 num_ps_gprs = 93;
2111                 num_vs_gprs = 46;
2112                 num_temp_gprs = 4;
2113                 num_gs_gprs = 31;
2114                 num_es_gprs = 31;
2115                 num_hs_gprs = 23;
2116                 num_ls_gprs = 23;
2117                 num_ps_threads = 96;
2118                 num_vs_threads = 16;
2119                 num_gs_threads = 16;
2120                 num_es_threads = 16;
2121                 num_hs_threads = 16;
2122                 num_ls_threads = 16;
2123                 num_ps_stack_entries = 42;
2124                 num_vs_stack_entries = 42;
2125                 num_gs_stack_entries = 42;
2126                 num_es_stack_entries = 42;
2127                 num_hs_stack_entries = 42;
2128                 num_ls_stack_entries = 42;
2129                 break;
2130         case CHIP_SUMO:
2131                 num_ps_gprs = 93;
2132                 num_vs_gprs = 46;
2133                 num_temp_gprs = 4;
2134                 num_gs_gprs = 31;
2135                 num_es_gprs = 31;
2136                 num_hs_gprs = 23;
2137                 num_ls_gprs = 23;
2138                 num_ps_threads = 96;
2139                 num_vs_threads = 25;
2140                 num_gs_threads = 25;
2141                 num_es_threads = 25;
2142                 num_hs_threads = 25;
2143                 num_ls_threads = 25;
2144                 num_ps_stack_entries = 42;
2145                 num_vs_stack_entries = 42;
2146                 num_gs_stack_entries = 42;
2147                 num_es_stack_entries = 42;
2148                 num_hs_stack_entries = 42;
2149                 num_ls_stack_entries = 42;
2150                 break;
2151         case CHIP_SUMO2:
2152                 num_ps_gprs = 93;
2153                 num_vs_gprs = 46;
2154                 num_temp_gprs = 4;
2155                 num_gs_gprs = 31;
2156                 num_es_gprs = 31;
2157                 num_hs_gprs = 23;
2158                 num_ls_gprs = 23;
2159                 num_ps_threads = 96;
2160                 num_vs_threads = 25;
2161                 num_gs_threads = 25;
2162                 num_es_threads = 25;
2163                 num_hs_threads = 25;
2164                 num_ls_threads = 25;
2165                 num_ps_stack_entries = 85;
2166                 num_vs_stack_entries = 85;
2167                 num_gs_stack_entries = 85;
2168                 num_es_stack_entries = 85;
2169                 num_hs_stack_entries = 85;
2170                 num_ls_stack_entries = 85;
2171                 break;
2172         case CHIP_BARTS:
2173                 num_ps_gprs = 93;
2174                 num_vs_gprs = 46;
2175                 num_temp_gprs = 4;
2176                 num_gs_gprs = 31;
2177                 num_es_gprs = 31;
2178                 num_hs_gprs = 23;
2179                 num_ls_gprs = 23;
2180                 num_ps_threads = 128;
2181                 num_vs_threads = 20;
2182                 num_gs_threads = 20;
2183                 num_es_threads = 20;
2184                 num_hs_threads = 20;
2185                 num_ls_threads = 20;
2186                 num_ps_stack_entries = 85;
2187                 num_vs_stack_entries = 85;
2188                 num_gs_stack_entries = 85;
2189                 num_es_stack_entries = 85;
2190                 num_hs_stack_entries = 85;
2191                 num_ls_stack_entries = 85;
2192                 break;
2193         case CHIP_TURKS:
2194                 num_ps_gprs = 93;
2195                 num_vs_gprs = 46;
2196                 num_temp_gprs = 4;
2197                 num_gs_gprs = 31;
2198                 num_es_gprs = 31;
2199                 num_hs_gprs = 23;
2200                 num_ls_gprs = 23;
2201                 num_ps_threads = 128;
2202                 num_vs_threads = 20;
2203                 num_gs_threads = 20;
2204                 num_es_threads = 20;
2205                 num_hs_threads = 20;
2206                 num_ls_threads = 20;
2207                 num_ps_stack_entries = 42;
2208                 num_vs_stack_entries = 42;
2209                 num_gs_stack_entries = 42;
2210                 num_es_stack_entries = 42;
2211                 num_hs_stack_entries = 42;
2212                 num_ls_stack_entries = 42;
2213                 break;
2214         case CHIP_CAICOS:
2215                 num_ps_gprs = 93;
2216                 num_vs_gprs = 46;
2217                 num_temp_gprs = 4;
2218                 num_gs_gprs = 31;
2219                 num_es_gprs = 31;
2220                 num_hs_gprs = 23;
2221                 num_ls_gprs = 23;
2222                 num_ps_threads = 128;
2223                 num_vs_threads = 10;
2224                 num_gs_threads = 10;
2225                 num_es_threads = 10;
2226                 num_hs_threads = 10;
2227                 num_ls_threads = 10;
2228                 num_ps_stack_entries = 42;
2229                 num_vs_stack_entries = 42;
2230                 num_gs_stack_entries = 42;
2231                 num_es_stack_entries = 42;
2232                 num_hs_stack_entries = 42;
2233                 num_ls_stack_entries = 42;
2234                 break;
2235         }
2236
2237         tmp = 0x00000000;
2238         switch (family) {
2239         case CHIP_CEDAR:
2240         case CHIP_PALM:
2241         case CHIP_SUMO:
2242         case CHIP_SUMO2:
2243         case CHIP_CAICOS:
2244                 break;
2245         default:
2246                 tmp |= S_008C00_VC_ENABLE(1);
2247                 break;
2248         }
2249         tmp |= S_008C00_EXPORT_SRC_C(1);
2250         tmp |= S_008C00_CS_PRIO(cs_prio);
2251         tmp |= S_008C00_LS_PRIO(ls_prio);
2252         tmp |= S_008C00_HS_PRIO(hs_prio);
2253         tmp |= S_008C00_PS_PRIO(ps_prio);
2254         tmp |= S_008C00_VS_PRIO(vs_prio);
2255         tmp |= S_008C00_GS_PRIO(gs_prio);
2256         tmp |= S_008C00_ES_PRIO(es_prio);
2257         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
2258
2259         /* enable dynamic GPR resource management */
2260         if (rctx->screen->info.drm_minor >= 7) {
2261                 /* always set temp clauses */
2262                 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
2263                                         S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), NULL, 0);
2264                 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, NULL, 0);
2265                 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, NULL, 0);
2266                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), NULL, 0);
2267                 r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2268                                         S_028838_PS_GPRS(0x1e) |
2269                                         S_028838_VS_GPRS(0x1e) |
2270                                         S_028838_GS_GPRS(0x1e) |
2271                                         S_028838_ES_GPRS(0x1e) |
2272                                         S_028838_HS_GPRS(0x1e) |
2273                                         S_028838_LS_GPRS(0x1e), NULL, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2274         } else {
2275                 tmp = 0;
2276                 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2277                 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2278                 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2279                 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0);
2280
2281                 tmp = 0;
2282                 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2283                 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2284                 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, NULL, 0);
2285
2286                 tmp = 0;
2287                 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2288                 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2289                 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, NULL, 0);
2290         }
2291
2292         tmp = 0;
2293         tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
2294         tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2295         tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2296         tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2297         r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, NULL, 0);
2298
2299         tmp = 0;
2300         tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
2301         tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2302         r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, NULL, 0);
2303
2304         tmp = 0;
2305         tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2306         tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2307         r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, NULL, 0);
2308
2309         tmp = 0;
2310         tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2311         tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2312         r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, NULL, 0);
2313
2314         tmp = 0;
2315         tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2316         tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2317         r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, NULL, 0);
2318
2319         tmp = 0;
2320         tmp |= S_008E2C_NUM_PS_LDS(0x1000);
2321         tmp |= S_008E2C_NUM_LS_LDS(0x1000);
2322         r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, NULL, 0);
2323
2324         r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, NULL, 0);
2325         r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), NULL, 0);
2326
2327 #if 0
2328         r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, NULL, 0);
2329
2330         r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, NULL, 0);
2331 #endif
2332         r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
2333
2334         r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, NULL, 0);
2335         r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, NULL, 0);
2336         r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2337         r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2338         r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2339         r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2340
2341         r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, NULL, 0);
2342         r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, NULL, 0);
2343         r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, NULL, 0);
2344         r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, NULL, 0);
2345
2346         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
2347         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
2348         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
2349         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
2350         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
2351         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
2352         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
2353         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
2354         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
2355         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
2356         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
2357         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
2358         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
2359         r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
2360         r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
2361         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
2362         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
2363         r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
2364
2365         r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, NULL, 0);
2366         r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, NULL, 0);
2367         r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, NULL, 0);
2368         r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, NULL, 0);
2369         r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, NULL, 0);
2370         r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, NULL, 0);
2371         r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, NULL, 0);
2372         r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, NULL, 0);
2373         r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, NULL, 0);
2374         r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, NULL, 0);
2375         r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, NULL, 0);
2376         r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, NULL, 0);
2377         r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, NULL, 0);
2378         r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, NULL, 0);
2379         r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, NULL, 0);
2380         r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, NULL, 0);
2381         r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, NULL, 0);
2382         r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, NULL, 0);
2383         r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, NULL, 0);
2384         r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, NULL, 0);
2385         r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, NULL, 0);
2386         r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, NULL, 0);
2387         r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, NULL, 0);
2388         r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, NULL, 0);
2389         r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, NULL, 0);
2390         r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, NULL, 0);
2391         r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, NULL, 0);
2392         r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, NULL, 0);
2393         r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, NULL, 0);
2394         r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, NULL, 0);
2395         r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, NULL, 0);
2396         r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, NULL, 0);
2397
2398         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
2399
2400         r600_context_pipe_state_set(rctx, rstate);
2401 }
2402
2403 void evergreen_polygon_offset_update(struct r600_context *rctx)
2404 {
2405         struct r600_pipe_state state;
2406
2407         state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2408         state.nregs = 0;
2409         if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2410                 float offset_units = rctx->rasterizer->offset_units;
2411                 unsigned offset_db_fmt_cntl = 0, depth;
2412
2413                 switch (rctx->framebuffer.zsbuf->texture->format) {
2414                 case PIPE_FORMAT_Z24X8_UNORM:
2415                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2416                         depth = -24;
2417                         offset_units *= 2.0f;
2418                         break;
2419                 case PIPE_FORMAT_Z32_FLOAT:
2420                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2421                         depth = -23;
2422                         offset_units *= 1.0f;
2423                         offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2424                         break;
2425                 case PIPE_FORMAT_Z16_UNORM:
2426                         depth = -16;
2427                         offset_units *= 4.0f;
2428                         break;
2429                 default:
2430                         return;
2431                 }
2432                 /* FIXME some of those reg can be computed with cso */
2433                 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2434                 r600_pipe_state_add_reg(&state,
2435                                 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2436                                 fui(rctx->rasterizer->offset_scale), NULL, 0);
2437                 r600_pipe_state_add_reg(&state,
2438                                 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2439                                 fui(offset_units), NULL, 0);
2440                 r600_pipe_state_add_reg(&state,
2441                                 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2442                                 fui(rctx->rasterizer->offset_scale), NULL, 0);
2443                 r600_pipe_state_add_reg(&state,
2444                                 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2445                                 fui(offset_units), NULL, 0);
2446                 r600_pipe_state_add_reg(&state,
2447                                 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2448                                 offset_db_fmt_cntl, NULL, 0);
2449                 r600_context_pipe_state_set(rctx, &state);
2450         }
2451 }
2452
2453 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2454 {
2455         struct r600_context *rctx = (struct r600_context *)ctx;
2456         struct r600_pipe_state *rstate = &shader->rstate;
2457         struct r600_shader *rshader = &shader->shader;
2458         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2459         int pos_index = -1, face_index = -1;
2460         int ninterp = 0;
2461         boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2462         unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2463
2464         rstate->nregs = 0;
2465
2466         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2467         for (i = 0; i < rshader->ninput; i++) {
2468                 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2469                    POSITION goes via GPRs from the SC so isn't counted */
2470                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2471                         pos_index = i;
2472                 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2473                         face_index = i;
2474                 else {
2475                         ninterp++;
2476                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2477                                 have_linear = TRUE;
2478                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2479                                 have_perspective = TRUE;
2480                         if (rshader->input[i].centroid)
2481                                 have_centroid = TRUE;
2482                 }
2483
2484                 sid = rshader->input[i].spi_sid;
2485
2486                 if (sid) {
2487
2488                         tmp = S_028644_SEMANTIC(sid);
2489
2490                         if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2491                                 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2492                                 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2493                                         rctx->rasterizer && rctx->rasterizer->flatshade)) {
2494                                 tmp |= S_028644_FLAT_SHADE(1);
2495                         }
2496
2497                         if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2498                                         (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2499                                 tmp |= S_028644_PT_SPRITE_TEX(1);
2500                         }
2501
2502                         r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2503                                         tmp, NULL, 0);
2504
2505                         idx++;
2506                 }
2507         }
2508
2509         for (i = 0; i < rshader->noutput; i++) {
2510                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2511                         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2512                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2513                         db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2514         }
2515         if (rshader->uses_kill)
2516                 db_shader_control |= S_02880C_KILL_ENABLE(1);
2517
2518         exports_ps = 0;
2519         num_cout = 0;
2520         for (i = 0; i < rshader->noutput; i++) {
2521                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2522                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2523                         exports_ps |= 1;
2524                 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2525                         if (rshader->fs_write_all)
2526                                 num_cout = rshader->nr_cbufs;
2527                         else
2528                                 num_cout++;
2529                 }
2530         }
2531         exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2532         if (!exports_ps) {
2533                 /* always at least export 1 component per pixel */
2534                 exports_ps = 2;
2535         }
2536
2537         if (ninterp == 0) {
2538                 ninterp = 1;
2539                 have_perspective = TRUE;
2540         }
2541
2542         if (!have_perspective && !have_linear)
2543                 have_perspective = TRUE;
2544
2545         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2546                               S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2547                               S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2548         spi_input_z = 0;
2549         if (pos_index != -1) {
2550                 spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
2551                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2552                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2553                 spi_input_z |= 1;
2554         }
2555
2556         spi_ps_in_control_1 = 0;
2557         if (face_index != -1) {
2558                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2559                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2560         }
2561
2562         spi_baryc_cntl = 0;
2563         if (have_perspective)
2564                 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2565                                   S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2566         if (have_linear)
2567                 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2568                                   S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2569
2570         r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2571                                 spi_ps_in_control_0, NULL, 0);
2572         r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2573                                 spi_ps_in_control_1, NULL, 0);
2574         r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2575                                 0, NULL, 0);
2576         r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
2577         r600_pipe_state_add_reg(rstate,
2578                                 R_0286E0_SPI_BARYC_CNTL,
2579                                 spi_baryc_cntl,
2580                                 NULL, 0);
2581
2582         r600_pipe_state_add_reg(rstate,
2583                                 R_028840_SQ_PGM_START_PS,
2584                                 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2585                                 shader->bo, RADEON_USAGE_READ);
2586         r600_pipe_state_add_reg(rstate,
2587                                 R_028844_SQ_PGM_RESOURCES_PS,
2588                                 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2589                                 S_028844_PRIME_CACHE_ON_DRAW(1) |
2590                                 S_028844_STACK_SIZE(rshader->bc.nstack),
2591                                 NULL, 0);
2592         r600_pipe_state_add_reg(rstate,
2593                                 R_028848_SQ_PGM_RESOURCES_2_PS,
2594                                 S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2595                                 NULL, 0);
2596         r600_pipe_state_add_reg(rstate,
2597                                 R_02884C_SQ_PGM_EXPORTS_PS,
2598                                 exports_ps, NULL, 0);
2599         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2600                                 db_shader_control,
2601                                 NULL, 0);
2602         r600_pipe_state_add_reg(rstate,
2603                                 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
2604                                 NULL, 0);
2605
2606         shader->sprite_coord_enable = rctx->sprite_coord_enable;
2607         if (rctx->rasterizer)
2608                 shader->flatshade = rctx->rasterizer->flatshade;
2609 }
2610
2611 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2612 {
2613         struct r600_context *rctx = (struct r600_context *)ctx;
2614         struct r600_pipe_state *rstate = &shader->rstate;
2615         struct r600_shader *rshader = &shader->shader;
2616         unsigned spi_vs_out_id[10] = {};
2617         unsigned i, tmp, nparams = 0;
2618
2619         /* clear previous register */
2620         rstate->nregs = 0;
2621
2622         for (i = 0; i < rshader->noutput; i++) {
2623                 if (rshader->output[i].spi_sid) {
2624                         tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2625                         spi_vs_out_id[nparams / 4] |= tmp;
2626                         nparams++;
2627                 }
2628         }
2629
2630         for (i = 0; i < 10; i++) {
2631                 r600_pipe_state_add_reg(rstate,
2632                                         R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2633                                         spi_vs_out_id[i], NULL, 0);
2634         }
2635
2636         /* Certain attributes (position, psize, etc.) don't count as params.
2637          * VS is required to export at least one param and r600_shader_from_tgsi()
2638          * takes care of adding a dummy export.
2639          */
2640         if (nparams < 1)
2641                 nparams = 1;
2642
2643         r600_pipe_state_add_reg(rstate,
2644                         R_0286C4_SPI_VS_OUT_CONFIG,
2645                         S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2646                         NULL, 0);
2647         r600_pipe_state_add_reg(rstate,
2648                         R_028860_SQ_PGM_RESOURCES_VS,
2649                         S_028860_NUM_GPRS(rshader->bc.ngpr) |
2650                         S_028860_STACK_SIZE(rshader->bc.nstack),
2651                         NULL, 0);
2652         r600_pipe_state_add_reg(rstate,
2653                                 R_028864_SQ_PGM_RESOURCES_2_VS,
2654                                 S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2655                                 NULL, 0);
2656         r600_pipe_state_add_reg(rstate,
2657                         R_02885C_SQ_PGM_START_VS,
2658                         r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2659                         shader->bo, RADEON_USAGE_READ);
2660
2661         r600_pipe_state_add_reg(rstate,
2662                                 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2663                                 NULL, 0);
2664
2665         shader->pa_cl_vs_out_cntl =
2666                 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2667                 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2668                 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2669                 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2670 }
2671
2672 void evergreen_fetch_shader(struct pipe_context *ctx,
2673                             struct r600_vertex_element *ve)
2674 {
2675         struct r600_context *rctx = (struct r600_context *)ctx;
2676         struct r600_pipe_state *rstate = &ve->rstate;
2677         rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2678         rstate->nregs = 0;
2679         r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
2680                                 0x00000000, NULL, 0);
2681         r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2682                                 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2683                                 ve->fetch_shader, RADEON_USAGE_READ);
2684 }
2685
2686 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2687 {
2688         struct pipe_depth_stencil_alpha_state dsa;
2689         struct r600_pipe_state *rstate;
2690
2691         memset(&dsa, 0, sizeof(dsa));
2692
2693         rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2694         r600_pipe_state_add_reg(rstate,
2695                                 R_028000_DB_RENDER_CONTROL,
2696                                 S_028000_DEPTH_COPY_ENABLE(1) |
2697                                 S_028000_STENCIL_COPY_ENABLE(1) |
2698                                 S_028000_COPY_CENTROID(1),
2699                                 NULL, 0);
2700         return rstate;
2701 }
2702
2703 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
2704                                          struct r600_pipe_resource_state *rstate)
2705 {
2706         rstate->id = R600_PIPE_STATE_RESOURCE;
2707
2708         rstate->val[0] = 0;
2709         rstate->bo[0] = NULL;
2710         rstate->val[1] = 0;
2711         rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2712         rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2713           S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2714           S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2715           S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2716         rstate->val[4] = 0;
2717         rstate->val[5] = 0;
2718         rstate->val[6] = 0;
2719         rstate->val[7] = 0xc0000000;
2720 }
2721
2722
2723 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
2724                                         struct r600_pipe_resource_state *rstate,
2725                                         struct r600_resource *rbuffer,
2726                                         unsigned offset, unsigned stride,
2727                                         enum radeon_bo_usage usage)
2728 {
2729         uint64_t va;
2730
2731         va = r600_resource_va(ctx->screen, (void *)rbuffer);
2732         rstate->bo[0] = rbuffer;
2733         rstate->bo_usage[0] = usage;
2734         rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
2735         rstate->val[1] = rbuffer->buf->size - offset - 1;
2736         rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2737                          S_030008_STRIDE(stride) |
2738                          (((va + offset) >> 32UL) & 0xFF);
2739 }