src/gallium/drivers/r600/evergreen_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /* TODO:
  25  *      - fix mask for depth control & cull for query
  26  */
  27 #include <stdio.h>
  28 #include <errno.h>
  29 #include "pipe/p_defines.h"
  30 #include "pipe/p_state.h"
  31 #include "pipe/p_context.h"
  32 #include "tgsi/tgsi_scan.h"
  33 #include "tgsi/tgsi_parse.h"
  34 #include "tgsi/tgsi_util.h"
  35 #include "util/u_blitter.h"
  36 #include "util/u_double_list.h"
  37 #include "util/u_transfer.h"
  38 #include "util/u_surface.h"
  39 #include "util/u_pack_color.h"
  40 #include "util/u_memory.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_framebuffer.h"
  43 #include "pipebuffer/pb_buffer.h"
  44 #include "r600.h"
  45 #include "evergreend.h"
  46 #include "r600_resource.h"
  47 #include "r600_shader.h"
  48 #include "r600_pipe.h"
  49 #include "r600_formats.h"
  50
  51 static uint32_t eg_num_banks(uint32_t nbanks)
  52 {
  53         switch (nbanks) {
  54         case 2:
  55                 return 0;
  56         case 4:
  57                 return 1;
  58         case 8:
  59         default:
  60                 return 2;
  61         case 16:
  62                 return 3;
  63         }
  64 }
  65
  66
  67 static unsigned eg_tile_split(unsigned tile_split)
  68 {
  69         switch (tile_split) {
  70         case 64:        tile_split = 0; break;
  71         case 128:       tile_split = 1; break;
  72         case 256:       tile_split = 2; break;
  73         case 512:       tile_split = 3; break;
  74         default:
  75         case 1024:      tile_split = 4; break;
  76         case 2048:      tile_split = 5; break;
  77         case 4096:      tile_split = 6; break;
  78         }
  79         return tile_split;
  80 }
  81
  82 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
  83 {
  84         switch (macro_tile_aspect) {
  85         default:
  86         case 1: macro_tile_aspect = 0;  break;
  87         case 2: macro_tile_aspect = 1;  break;
  88         case 4: macro_tile_aspect = 2;  break;
  89         case 8: macro_tile_aspect = 3;  break;
  90         }
  91         return macro_tile_aspect;
  92 }
  93
  94 static unsigned eg_bank_wh(unsigned bankwh)
  95 {
  96         switch (bankwh) {
  97         default:
  98         case 1: bankwh = 0;     break;
  99         case 2: bankwh = 1;     break;
 100         case 4: bankwh = 2;     break;
 101         case 8: bankwh = 3;     break;
 102         }
 103         return bankwh;
 104 }
 105
 106 static uint32_t r600_translate_blend_function(int blend_func)
 107 {
 108         switch (blend_func) {
 109         case PIPE_BLEND_ADD:
 110                 return V_028780_COMB_DST_PLUS_SRC;
 111         case PIPE_BLEND_SUBTRACT:
 112                 return V_028780_COMB_SRC_MINUS_DST;
 113         case PIPE_BLEND_REVERSE_SUBTRACT:
 114                 return V_028780_COMB_DST_MINUS_SRC;
 115         case PIPE_BLEND_MIN:
 116                 return V_028780_COMB_MIN_DST_SRC;
 117         case PIPE_BLEND_MAX:
 118                 return V_028780_COMB_MAX_DST_SRC;
 119         default:
 120                 R600_ERR("Unknown blend function %d\n", blend_func);
 121                 assert(0);
 122                 break;
 123         }
 124         return 0;
 125 }
 126
 127 static uint32_t r600_translate_blend_factor(int blend_fact)
 128 {
 129         switch (blend_fact) {
 130         case PIPE_BLENDFACTOR_ONE:
 131                 return V_028780_BLEND_ONE;
 132         case PIPE_BLENDFACTOR_SRC_COLOR:
 133                 return V_028780_BLEND_SRC_COLOR;
 134         case PIPE_BLENDFACTOR_SRC_ALPHA:
 135                 return V_028780_BLEND_SRC_ALPHA;
 136         case PIPE_BLENDFACTOR_DST_ALPHA:
 137                 return V_028780_BLEND_DST_ALPHA;
 138         case PIPE_BLENDFACTOR_DST_COLOR:
 139                 return V_028780_BLEND_DST_COLOR;
 140         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
 141                 return V_028780_BLEND_SRC_ALPHA_SATURATE;
 142         case PIPE_BLENDFACTOR_CONST_COLOR:
 143                 return V_028780_BLEND_CONST_COLOR;
 144         case PIPE_BLENDFACTOR_CONST_ALPHA:
 145                 return V_028780_BLEND_CONST_ALPHA;
 146         case PIPE_BLENDFACTOR_ZERO:
 147                 return V_028780_BLEND_ZERO;
 148         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
 149                 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
 150         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
 151                 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
 152         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
 153                 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
 154         case PIPE_BLENDFACTOR_INV_DST_COLOR:
 155                 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
 156         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
 157                 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
 158         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
 159                 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
 160         case PIPE_BLENDFACTOR_SRC1_COLOR:
 161                 return V_028780_BLEND_SRC1_COLOR;
 162         case PIPE_BLENDFACTOR_SRC1_ALPHA:
 163                 return V_028780_BLEND_SRC1_ALPHA;
 164         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
 165                 return V_028780_BLEND_INV_SRC1_COLOR;
 166         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
 167                 return V_028780_BLEND_INV_SRC1_ALPHA;
 168         default:
 169                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
 170                 assert(0);
 171                 break;
 172         }
 173         return 0;
 174 }
 175
 176 /* translates straight */
 177 static uint32_t r600_translate_ds_func(int func)
 178 {
 179         return func;
 180 }
 181
 182 static unsigned r600_tex_wrap(unsigned wrap)
 183 {
 184         switch (wrap) {
 185         default:
 186         case PIPE_TEX_WRAP_REPEAT:
 187                 return V_03C000_SQ_TEX_WRAP;
 188         case PIPE_TEX_WRAP_CLAMP:
 189                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
 190         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 191                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
 192         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 193                 return V_03C000_SQ_TEX_CLAMP_BORDER;
 194         case PIPE_TEX_WRAP_MIRROR_REPEAT:
 195                 return V_03C000_SQ_TEX_MIRROR;
 196         case PIPE_TEX_WRAP_MIRROR_CLAMP:
 197                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
 198         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
 199                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
 200         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 201                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
 202         }
 203 }
 204
 205 static unsigned r600_tex_filter(unsigned filter)
 206 {
 207         switch (filter) {
 208         default:
 209         case PIPE_TEX_FILTER_NEAREST:
 210                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
 211         case PIPE_TEX_FILTER_LINEAR:
 212                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
 213         }
 214 }
 215
 216 static unsigned r600_tex_mipfilter(unsigned filter)
 217 {
 218         switch (filter) {
 219         case PIPE_TEX_MIPFILTER_NEAREST:
 220                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
 221         case PIPE_TEX_MIPFILTER_LINEAR:
 222                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
 223         default:
 224         case PIPE_TEX_MIPFILTER_NONE:
 225                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
 226         }
 227 }
 228
 229 static unsigned r600_tex_compare(unsigned compare)
 230 {
 231         switch (compare) {
 232         default:
 233         case PIPE_FUNC_NEVER:
 234                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
 235         case PIPE_FUNC_LESS:
 236                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
 237         case PIPE_FUNC_EQUAL:
 238                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
 239         case PIPE_FUNC_LEQUAL:
 240                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
 241         case PIPE_FUNC_GREATER:
 242                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
 243         case PIPE_FUNC_NOTEQUAL:
 244                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
 245         case PIPE_FUNC_GEQUAL:
 246                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
 247         case PIPE_FUNC_ALWAYS:
 248                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
 249         }
 250 }
 251
 252 static unsigned r600_tex_dim(unsigned dim)
 253 {
 254         switch (dim) {
 255         default:
 256         case PIPE_TEXTURE_1D:
 257                 return V_030000_SQ_TEX_DIM_1D;
 258         case PIPE_TEXTURE_1D_ARRAY:
 259                 return V_030000_SQ_TEX_DIM_1D_ARRAY;
 260         case PIPE_TEXTURE_2D:
 261         case PIPE_TEXTURE_RECT:
 262                 return V_030000_SQ_TEX_DIM_2D;
 263         case PIPE_TEXTURE_2D_ARRAY:
 264                 return V_030000_SQ_TEX_DIM_2D_ARRAY;
 265         case PIPE_TEXTURE_3D:
 266                 return V_030000_SQ_TEX_DIM_3D;
 267         case PIPE_TEXTURE_CUBE:
 268                 return V_030000_SQ_TEX_DIM_CUBEMAP;
 269         }
 270 }
 271
 272 static uint32_t r600_translate_dbformat(enum pipe_format format)
 273 {
 274         switch (format) {
 275         case PIPE_FORMAT_Z16_UNORM:
 276                 return V_028040_Z_16;
 277         case PIPE_FORMAT_Z24X8_UNORM:
 278         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 279                 return V_028040_Z_24;
 280         case PIPE_FORMAT_Z32_FLOAT:
 281         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 282                 return V_028040_Z_32_FLOAT;
 283         default:
 284                 return ~0U;
 285         }
 286 }
 287
 288 static uint32_t r600_translate_colorswap(enum pipe_format format)
 289 {
 290         switch (format) {
 291         /* 8-bit buffers. */
 292         case PIPE_FORMAT_L4A4_UNORM:
 293         case PIPE_FORMAT_A4R4_UNORM:
 294                 return V_028C70_SWAP_ALT;
 295
 296         case PIPE_FORMAT_A8_UNORM:
 297         case PIPE_FORMAT_A8_UINT:
 298         case PIPE_FORMAT_A8_SINT:
 299         case PIPE_FORMAT_R4A4_UNORM:
 300                 return V_028C70_SWAP_ALT_REV;
 301         case PIPE_FORMAT_I8_UNORM:
 302         case PIPE_FORMAT_L8_UNORM:
 303         case PIPE_FORMAT_I8_UINT:
 304         case PIPE_FORMAT_I8_SINT:
 305         case PIPE_FORMAT_L8_UINT:
 306         case PIPE_FORMAT_L8_SINT:
 307         case PIPE_FORMAT_L8_SRGB:
 308         case PIPE_FORMAT_R8_UNORM:
 309         case PIPE_FORMAT_R8_SNORM:
 310         case PIPE_FORMAT_R8_UINT:
 311         case PIPE_FORMAT_R8_SINT:
 312                 return V_028C70_SWAP_STD;
 313
 314         /* 16-bit buffers. */
 315         case PIPE_FORMAT_B5G6R5_UNORM:
 316                 return V_028C70_SWAP_STD_REV;
 317
 318         case PIPE_FORMAT_B5G5R5A1_UNORM:
 319         case PIPE_FORMAT_B5G5R5X1_UNORM:
 320                 return V_028C70_SWAP_ALT;
 321
 322         case PIPE_FORMAT_B4G4R4A4_UNORM:
 323         case PIPE_FORMAT_B4G4R4X4_UNORM:
 324                 return V_028C70_SWAP_ALT;
 325
 326         case PIPE_FORMAT_Z16_UNORM:
 327                 return V_028C70_SWAP_STD;
 328
 329         case PIPE_FORMAT_L8A8_UNORM:
 330         case PIPE_FORMAT_L8A8_UINT:
 331         case PIPE_FORMAT_L8A8_SINT:
 332         case PIPE_FORMAT_L8A8_SRGB:
 333                 return V_028C70_SWAP_ALT;
 334         case PIPE_FORMAT_R8G8_UNORM:
 335         case PIPE_FORMAT_R8G8_UINT:
 336         case PIPE_FORMAT_R8G8_SINT:
 337                 return V_028C70_SWAP_STD;
 338
 339         case PIPE_FORMAT_R16_UNORM:
 340         case PIPE_FORMAT_R16_UINT:
 341         case PIPE_FORMAT_R16_SINT:
 342         case PIPE_FORMAT_R16_FLOAT:
 343                 return V_028C70_SWAP_STD;
 344
 345         /* 32-bit buffers. */
 346         case PIPE_FORMAT_A8B8G8R8_SRGB:
 347                 return V_028C70_SWAP_STD_REV;
 348         case PIPE_FORMAT_B8G8R8A8_SRGB:
 349                 return V_028C70_SWAP_ALT;
 350
 351         case PIPE_FORMAT_B8G8R8A8_UNORM:
 352         case PIPE_FORMAT_B8G8R8X8_UNORM:
 353                 return V_028C70_SWAP_ALT;
 354
 355         case PIPE_FORMAT_A8R8G8B8_UNORM:
 356         case PIPE_FORMAT_X8R8G8B8_UNORM:
 357                 return V_028C70_SWAP_ALT_REV;
 358         case PIPE_FORMAT_R8G8B8A8_SNORM:
 359         case PIPE_FORMAT_R8G8B8A8_UNORM:
 360         case PIPE_FORMAT_R8G8B8A8_SSCALED:
 361         case PIPE_FORMAT_R8G8B8A8_USCALED:
 362         case PIPE_FORMAT_R8G8B8A8_SINT:
 363         case PIPE_FORMAT_R8G8B8A8_UINT:
 364         case PIPE_FORMAT_R8G8B8X8_UNORM:
 365                 return V_028C70_SWAP_STD;
 366
 367         case PIPE_FORMAT_A8B8G8R8_UNORM:
 368         case PIPE_FORMAT_X8B8G8R8_UNORM:
 369         /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
 370                 return V_028C70_SWAP_STD_REV;
 371
 372         case PIPE_FORMAT_Z24X8_UNORM:
 373         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 374                 return V_028C70_SWAP_STD;
 375
 376         case PIPE_FORMAT_X8Z24_UNORM:
 377         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 378                 return V_028C70_SWAP_STD;
 379
 380         case PIPE_FORMAT_R10G10B10A2_UNORM:
 381         case PIPE_FORMAT_R10G10B10X2_SNORM:
 382         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 383                 return V_028C70_SWAP_STD;
 384
 385         case PIPE_FORMAT_B10G10R10A2_UNORM:
 386         case PIPE_FORMAT_B10G10R10A2_UINT:
 387                 return V_028C70_SWAP_ALT;
 388
 389         case PIPE_FORMAT_R11G11B10_FLOAT:
 390         case PIPE_FORMAT_R32_FLOAT:
 391         case PIPE_FORMAT_R32_UINT:
 392         case PIPE_FORMAT_R32_SINT:
 393         case PIPE_FORMAT_Z32_FLOAT:
 394         case PIPE_FORMAT_R16G16_FLOAT:
 395         case PIPE_FORMAT_R16G16_UNORM:
 396         case PIPE_FORMAT_R16G16_UINT:
 397         case PIPE_FORMAT_R16G16_SINT:
 398                 return V_028C70_SWAP_STD;
 399
 400         /* 64-bit buffers. */
 401         case PIPE_FORMAT_R32G32_FLOAT:
 402         case PIPE_FORMAT_R32G32_UINT:
 403         case PIPE_FORMAT_R32G32_SINT:
 404         case PIPE_FORMAT_R16G16B16A16_UNORM:
 405         case PIPE_FORMAT_R16G16B16A16_SNORM:
 406         case PIPE_FORMAT_R16G16B16A16_USCALED:
 407         case PIPE_FORMAT_R16G16B16A16_SSCALED:
 408         case PIPE_FORMAT_R16G16B16A16_UINT:
 409         case PIPE_FORMAT_R16G16B16A16_SINT:
 410         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 411         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 412
 413         /* 128-bit buffers. */
 414         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 415         case PIPE_FORMAT_R32G32B32A32_SNORM:
 416         case PIPE_FORMAT_R32G32B32A32_UNORM:
 417         case PIPE_FORMAT_R32G32B32A32_SSCALED:
 418         case PIPE_FORMAT_R32G32B32A32_USCALED:
 419         case PIPE_FORMAT_R32G32B32A32_SINT:
 420         case PIPE_FORMAT_R32G32B32A32_UINT:
 421                 return V_028C70_SWAP_STD;
 422         default:
 423                 R600_ERR("unsupported colorswap format %d\n", format);
 424                 return ~0U;
 425         }
 426         return ~0U;
 427 }
 428
 429 static uint32_t r600_translate_colorformat(enum pipe_format format)
 430 {
 431         switch (format) {
 432         /* 8-bit buffers. */
 433         case PIPE_FORMAT_A8_UNORM:
 434         case PIPE_FORMAT_A8_UINT:
 435         case PIPE_FORMAT_A8_SINT:
 436         case PIPE_FORMAT_I8_UNORM:
 437         case PIPE_FORMAT_I8_UINT:
 438         case PIPE_FORMAT_I8_SINT:
 439         case PIPE_FORMAT_L8_UNORM:
 440         case PIPE_FORMAT_L8_UINT:
 441         case PIPE_FORMAT_L8_SINT:
 442         case PIPE_FORMAT_L8_SRGB:
 443         case PIPE_FORMAT_R8_UNORM:
 444         case PIPE_FORMAT_R8_SNORM:
 445         case PIPE_FORMAT_R8_UINT:
 446         case PIPE_FORMAT_R8_SINT:
 447                 return V_028C70_COLOR_8;
 448
 449         /* 16-bit buffers. */
 450         case PIPE_FORMAT_B5G6R5_UNORM:
 451                 return V_028C70_COLOR_5_6_5;
 452
 453         case PIPE_FORMAT_B5G5R5A1_UNORM:
 454         case PIPE_FORMAT_B5G5R5X1_UNORM:
 455                 return V_028C70_COLOR_1_5_5_5;
 456
 457         case PIPE_FORMAT_B4G4R4A4_UNORM:
 458         case PIPE_FORMAT_B4G4R4X4_UNORM:
 459                 return V_028C70_COLOR_4_4_4_4;
 460
 461         case PIPE_FORMAT_Z16_UNORM:
 462                 return V_028C70_COLOR_16;
 463
 464         case PIPE_FORMAT_L8A8_UNORM:
 465         case PIPE_FORMAT_L8A8_UINT:
 466         case PIPE_FORMAT_L8A8_SINT:
 467         case PIPE_FORMAT_L8A8_SRGB:
 468         case PIPE_FORMAT_R8G8_UNORM:
 469         case PIPE_FORMAT_R8G8_UINT:
 470         case PIPE_FORMAT_R8G8_SINT:
 471                 return V_028C70_COLOR_8_8;
 472
 473         case PIPE_FORMAT_R16_UNORM:
 474         case PIPE_FORMAT_R16_UINT:
 475         case PIPE_FORMAT_R16_SINT:
 476                 return V_028C70_COLOR_16;
 477
 478         case PIPE_FORMAT_R16_FLOAT:
 479                 return V_028C70_COLOR_16_FLOAT;
 480
 481         /* 32-bit buffers. */
 482         case PIPE_FORMAT_A8B8G8R8_SRGB:
 483         case PIPE_FORMAT_A8B8G8R8_UNORM:
 484         case PIPE_FORMAT_A8R8G8B8_UNORM:
 485         case PIPE_FORMAT_B8G8R8A8_SRGB:
 486         case PIPE_FORMAT_B8G8R8A8_UNORM:
 487         case PIPE_FORMAT_B8G8R8X8_UNORM:
 488         case PIPE_FORMAT_R8G8B8A8_SNORM:
 489         case PIPE_FORMAT_R8G8B8A8_UNORM:
 490         case PIPE_FORMAT_R8G8B8X8_UNORM:
 491         case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
 492         case PIPE_FORMAT_X8B8G8R8_UNORM:
 493         case PIPE_FORMAT_X8R8G8B8_UNORM:
 494         case PIPE_FORMAT_R8G8B8_UNORM:
 495         case PIPE_FORMAT_R8G8B8A8_SSCALED:
 496         case PIPE_FORMAT_R8G8B8A8_USCALED:
 497         case PIPE_FORMAT_R8G8B8A8_SINT:
 498         case PIPE_FORMAT_R8G8B8A8_UINT:
 499                 return V_028C70_COLOR_8_8_8_8;
 500
 501         case PIPE_FORMAT_R10G10B10A2_UNORM:
 502         case PIPE_FORMAT_R10G10B10X2_SNORM:
 503         case PIPE_FORMAT_B10G10R10A2_UNORM:
 504         case PIPE_FORMAT_B10G10R10A2_UINT:
 505         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 506                 return V_028C70_COLOR_2_10_10_10;
 507
 508         case PIPE_FORMAT_Z24X8_UNORM:
 509         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 510                 return V_028C70_COLOR_8_24;
 511
 512         case PIPE_FORMAT_X8Z24_UNORM:
 513         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 514                 return V_028C70_COLOR_24_8;
 515
 516         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 517                 return V_028C70_COLOR_X24_8_32_FLOAT;
 518
 519         case PIPE_FORMAT_R32_UINT:
 520         case PIPE_FORMAT_R32_SINT:
 521                 return V_028C70_COLOR_32;
 522
 523         case PIPE_FORMAT_R32_FLOAT:
 524         case PIPE_FORMAT_Z32_FLOAT:
 525                 return V_028C70_COLOR_32_FLOAT;
 526
 527         case PIPE_FORMAT_R16G16_FLOAT:
 528                 return V_028C70_COLOR_16_16_FLOAT;
 529
 530         case PIPE_FORMAT_R16G16_SSCALED:
 531         case PIPE_FORMAT_R16G16_UNORM:
 532         case PIPE_FORMAT_R16G16_UINT:
 533         case PIPE_FORMAT_R16G16_SINT:
 534                 return V_028C70_COLOR_16_16;
 535
 536         case PIPE_FORMAT_R11G11B10_FLOAT:
 537                 return V_028C70_COLOR_10_11_11_FLOAT;
 538
 539         /* 64-bit buffers. */
 540         case PIPE_FORMAT_R16G16B16_USCALED:
 541         case PIPE_FORMAT_R16G16B16_SSCALED:
 542         case PIPE_FORMAT_R16G16B16A16_UINT:
 543         case PIPE_FORMAT_R16G16B16A16_SINT:
 544         case PIPE_FORMAT_R16G16B16A16_USCALED:
 545         case PIPE_FORMAT_R16G16B16A16_SSCALED:
 546         case PIPE_FORMAT_R16G16B16A16_UNORM:
 547         case PIPE_FORMAT_R16G16B16A16_SNORM:
 548                 return V_028C70_COLOR_16_16_16_16;
 549
 550         case PIPE_FORMAT_R16G16B16_FLOAT:
 551         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 552                 return V_028C70_COLOR_16_16_16_16_FLOAT;
 553
 554         case PIPE_FORMAT_R32G32_FLOAT:
 555                 return V_028C70_COLOR_32_32_FLOAT;
 556
 557         case PIPE_FORMAT_R32G32_USCALED:
 558         case PIPE_FORMAT_R32G32_SSCALED:
 559         case PIPE_FORMAT_R32G32_SINT:
 560         case PIPE_FORMAT_R32G32_UINT:
 561                 return V_028C70_COLOR_32_32;
 562
 563         /* 96-bit buffers. */
 564         case PIPE_FORMAT_R32G32B32_FLOAT:
 565                 return V_028C70_COLOR_32_32_32_FLOAT;
 566
 567         /* 128-bit buffers. */
 568         case PIPE_FORMAT_R32G32B32A32_SNORM:
 569         case PIPE_FORMAT_R32G32B32A32_UNORM:
 570         case PIPE_FORMAT_R32G32B32A32_SSCALED:
 571         case PIPE_FORMAT_R32G32B32A32_USCALED:
 572         case PIPE_FORMAT_R32G32B32A32_SINT:
 573         case PIPE_FORMAT_R32G32B32A32_UINT:
 574                 return V_028C70_COLOR_32_32_32_32;
 575         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 576                 return V_028C70_COLOR_32_32_32_32_FLOAT;
 577
 578         /* YUV buffers. */
 579         case PIPE_FORMAT_UYVY:
 580         case PIPE_FORMAT_YUYV:
 581         default:
 582                 return ~0U; /* Unsupported. */
 583         }
 584 }
 585
 586 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
 587 {
 588         if (R600_BIG_ENDIAN) {
 589                 switch(colorformat) {
 590
 591                 /* 8-bit buffers. */
 592                 case V_028C70_COLOR_8:
 593                         return ENDIAN_NONE;
 594
 595                 /* 16-bit buffers. */
 596                 case V_028C70_COLOR_5_6_5:
 597                 case V_028C70_COLOR_1_5_5_5:
 598                 case V_028C70_COLOR_4_4_4_4:
 599                 case V_028C70_COLOR_16:
 600                 case V_028C70_COLOR_8_8:
 601                         return ENDIAN_8IN16;
 602
 603                 /* 32-bit buffers. */
 604                 case V_028C70_COLOR_8_8_8_8:
 605                 case V_028C70_COLOR_2_10_10_10:
 606                 case V_028C70_COLOR_8_24:
 607                 case V_028C70_COLOR_24_8:
 608                 case V_028C70_COLOR_32_FLOAT:
 609                 case V_028C70_COLOR_16_16_FLOAT:
 610                 case V_028C70_COLOR_16_16:
 611                         return ENDIAN_8IN32;
 612
 613                 /* 64-bit buffers. */
 614                 case V_028C70_COLOR_16_16_16_16:
 615                 case V_028C70_COLOR_16_16_16_16_FLOAT:
 616                         return ENDIAN_8IN16;
 617
 618                 case V_028C70_COLOR_32_32_FLOAT:
 619                 case V_028C70_COLOR_32_32:
 620                 case V_028C70_COLOR_X24_8_32_FLOAT:
 621                         return ENDIAN_8IN32;
 622
 623                 /* 96-bit buffers. */
 624                 case V_028C70_COLOR_32_32_32_FLOAT:
 625                 /* 128-bit buffers. */
 626                 case V_028C70_COLOR_32_32_32_32_FLOAT:
 627                 case V_028C70_COLOR_32_32_32_32:
 628                         return ENDIAN_8IN32;
 629                 default:
 630                         return ENDIAN_NONE; /* Unsupported. */
 631                 }
 632         } else {
 633                 return ENDIAN_NONE;
 634         }
 635 }
 636
 637 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
 638 {
 639         return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
 640 }
 641
 642 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
 643 {
 644         return r600_translate_colorformat(format) != ~0U &&
 645                 r600_translate_colorswap(format) != ~0U;
 646 }
 647
 648 static bool r600_is_zs_format_supported(enum pipe_format format)
 649 {
 650         return r600_translate_dbformat(format) != ~0U;
 651 }
 652
 653 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 654                                       enum pipe_format format,
 655                                       enum pipe_texture_target target,
 656                                       unsigned sample_count,
 657                                       unsigned usage)
 658 {
 659         unsigned retval = 0;
 660
 661         if (target >= PIPE_MAX_TEXTURE_TYPES) {
 662                 R600_ERR("r600: unsupported texture type %d\n", target);
 663                 return FALSE;
 664         }
 665
 666         if (!util_format_is_supported(format, usage))
 667                 return FALSE;
 668
 669         /* Multisample */
 670         if (sample_count > 1)
 671                 return FALSE;
 672
 673         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 674             r600_is_sampler_format_supported(screen, format)) {
 675                 retval |= PIPE_BIND_SAMPLER_VIEW;
 676         }
 677
 678         if ((usage & (PIPE_BIND_RENDER_TARGET |
 679                       PIPE_BIND_DISPLAY_TARGET |
 680                       PIPE_BIND_SCANOUT |
 681                       PIPE_BIND_SHARED)) &&
 682             r600_is_colorbuffer_format_supported(format)) {
 683                 retval |= usage &
 684                           (PIPE_BIND_RENDER_TARGET |
 685                            PIPE_BIND_DISPLAY_TARGET |
 686                            PIPE_BIND_SCANOUT |
 687                            PIPE_BIND_SHARED);
 688         }
 689
 690         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 691             r600_is_zs_format_supported(format)) {
 692                 retval |= PIPE_BIND_DEPTH_STENCIL;
 693         }
 694
 695         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
 696             r600_is_vertex_format_supported(format)) {
 697                 retval |= PIPE_BIND_VERTEX_BUFFER;
 698         }
 699
 700         if (usage & PIPE_BIND_TRANSFER_READ)
 701                 retval |= PIPE_BIND_TRANSFER_READ;
 702         if (usage & PIPE_BIND_TRANSFER_WRITE)
 703                 retval |= PIPE_BIND_TRANSFER_WRITE;
 704
 705         return retval == usage;
 706 }
 707
 708 static void evergreen_set_blend_color(struct pipe_context *ctx,
 709                                         const struct pipe_blend_color *state)
 710 {
 711         struct r600_context *rctx = (struct r600_context *)ctx;
 712         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 713
 714         if (rstate == NULL)
 715                 return;
 716
 717         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 718         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
 719         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
 720         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
 721         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
 722
 723         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 724         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 725         r600_context_pipe_state_set(rctx, rstate);
 726 }
 727
 728 static void *evergreen_create_blend_state(struct pipe_context *ctx,
 729                                         const struct pipe_blend_state *state)
 730 {
 731         struct r600_context *rctx = (struct r600_context *)ctx;
 732         struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
 733         struct r600_pipe_state *rstate;
 734         uint32_t color_control, target_mask;
 735         /* FIXME there is more then 8 framebuffer */
 736         unsigned blend_cntl[8];
 737
 738         if (blend == NULL) {
 739                 return NULL;
 740         }
 741
 742         rstate = &blend->rstate;
 743
 744         rstate->id = R600_PIPE_STATE_BLEND;
 745
 746         target_mask = 0;
 747         color_control = S_028808_MODE(1);
 748         if (state->logicop_enable) {
 749                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 750         } else {
 751                 color_control |= (0xcc << 16);
 752         }
 753         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 754         if (state->independent_blend_enable) {
 755                 for (int i = 0; i < 8; i++) {
 756                         target_mask |= (state->rt[i].colormask << (4 * i));
 757                 }
 758         } else {
 759                 for (int i = 0; i < 8; i++) {
 760                         target_mask |= (state->rt[0].colormask << (4 * i));
 761                 }
 762         }
 763         blend->cb_target_mask = target_mask;
 764
 765         r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 766                                 color_control, NULL, 0);
 767
 768         if (rctx->chip_class != CAYMAN)
 769                 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, ~0, NULL, 0);
 770         else {
 771                 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0, NULL, 0);
 772                 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0, NULL, 0);
 773         }
 774
 775         for (int i = 0; i < 8; i++) {
 776                 /* state->rt entries > 0 only written if independent blending */
 777                 const int j = state->independent_blend_enable ? i : 0;
 778
 779                 unsigned eqRGB = state->rt[j].rgb_func;
 780                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 781                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 782                 unsigned eqA = state->rt[j].alpha_func;
 783                 unsigned srcA = state->rt[j].alpha_src_factor;
 784                 unsigned dstA = state->rt[j].alpha_dst_factor;
 785
 786                 blend_cntl[i] = 0;
 787                 if (!state->rt[j].blend_enable)
 788                         continue;
 789
 790                 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
 791                 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 792                 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 793                 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 794
 795                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 796                         blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
 797                         blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 798                         blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 799                         blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 800                 }
 801         }
 802         for (int i = 0; i < 8; i++) {
 803                 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], NULL, 0);
 804         }
 805
 806         return rstate;
 807 }
 808
 809 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
 810                                    const struct pipe_depth_stencil_alpha_state *state)
 811 {
 812         struct r600_context *rctx = (struct r600_context *)ctx;
 813         struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
 814         unsigned db_depth_control, alpha_test_control, alpha_ref;
 815         unsigned db_render_override, db_render_control;
 816         struct r600_pipe_state *rstate;
 817
 818         if (dsa == NULL) {
 819                 return NULL;
 820         }
 821
 822         dsa->valuemask[0] = state->stencil[0].valuemask;
 823         dsa->valuemask[1] = state->stencil[1].valuemask;
 824         dsa->writemask[0] = state->stencil[0].writemask;
 825         dsa->writemask[1] = state->stencil[1].writemask;
 826
 827         rstate = &dsa->rstate;
 828
 829         rstate->id = R600_PIPE_STATE_DSA;
 830         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 831                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 832                 S_028800_ZFUNC(state->depth.func);
 833
 834         /* stencil */
 835         if (state->stencil[0].enabled) {
 836                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 837                 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
 838                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 839                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 840                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 841
 842                 if (state->stencil[1].enabled) {
 843                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 844                         db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
 845                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 846                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 847                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 848                 }
 849         }
 850
 851         /* alpha */
 852         alpha_test_control = 0;
 853         alpha_ref = 0;
 854         if (state->alpha.enabled) {
 855                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 856                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 857                 alpha_ref = fui(state->alpha.ref_value);
 858         }
 859         dsa->alpha_ref = alpha_ref;
 860
 861         /* misc */
 862         db_render_control = 0;
 863         db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
 864                 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
 865                 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
 866         /* TODO db_render_override depends on query */
 867         r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0);
 868         r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0);
 869         r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
 870         r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, NULL, 0);
 871         r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
 872         /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
 873          * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
 874          * evergreen_pipe_shader_ps().*/
 875         r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
 876         r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, NULL, 0);
 877         r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, NULL, 0);
 878         r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, NULL, 0);
 879         r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, NULL, 0);
 880         r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0);
 881         dsa->db_render_override = db_render_override;
 882
 883         return rstate;
 884 }
 885
 886 static void *evergreen_create_rs_state(struct pipe_context *ctx,
 887                                         const struct pipe_rasterizer_state *state)
 888 {
 889         struct r600_context *rctx = (struct r600_context *)ctx;
 890         struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
 891         struct r600_pipe_state *rstate;
 892         unsigned tmp;
 893         unsigned prov_vtx = 1, polygon_dual_mode;
 894         unsigned clip_rule;
 895         float psize_min, psize_max;
 896
 897         if (rs == NULL) {
 898                 return NULL;
 899         }
 900
 901         polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
 902                                 state->fill_back != PIPE_POLYGON_MODE_FILL);
 903
 904         if (state->flatshade_first)
 905                 prov_vtx = 0;
 906
 907         rstate = &rs->rstate;
 908         rs->flatshade = state->flatshade;
 909         rs->sprite_coord_enable = state->sprite_coord_enable;
 910         rs->two_side = state->light_twoside;
 911         rs->clip_plane_enable = state->clip_plane_enable;
 912         rs->pa_sc_line_stipple = state->line_stipple_enable ?
 913                                 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
 914                                 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 915         rs->pa_su_sc_mode_cntl =
 916                 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 917                 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 918                 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 919                 S_028814_FACE(!state->front_ccw) |
 920                 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 921                 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 922                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 923                 S_028814_POLY_MODE(polygon_dual_mode) |
 924                 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 925                 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
 926         rs->pa_cl_clip_cntl =
 927                 S_028810_PS_UCP_MODE(3) |
 928                 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
 929                 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
 930                 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
 931
 932         clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
 933
 934         /* offset */
 935         rs->offset_units = state->offset_units;
 936         rs->offset_scale = state->offset_scale * 12.0f;
 937
 938         rstate->id = R600_PIPE_STATE_RASTERIZER;
 939         tmp = S_0286D4_FLAT_SHADE_ENA(1);
 940         if (state->sprite_coord_enable) {
 941                 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
 942                         S_0286D4_PNT_SPRITE_OVRD_X(2) |
 943                         S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 944                         S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 945                         S_0286D4_PNT_SPRITE_OVRD_W(1);
 946                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 947                         tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 948                 }
 949         }
 950         r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
 951
 952         r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0);
 953         /* point size 12.4 fixed point */
 954         tmp = (unsigned)(state->point_size * 8.0);
 955         r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
 956
 957         if (state->point_size_per_vertex) {
 958                 psize_min = util_get_min_point_size(state);
 959                 psize_max = 8192;
 960         } else {
 961                 /* Force the point size to be as if the vertex output was disabled. */
 962                 psize_min = state->point_size;
 963                 psize_max = state->point_size;
 964         }
 965         /* Divide by two, because 0.5 = 1 pixel. */
 966         r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
 967                                 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
 968                                 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
 969                                 NULL, 0);
 970
 971         tmp = (unsigned)state->line_width * 8;
 972         r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
 973         r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
 974                                 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
 975                                 NULL, 0);
 976
 977         if (rctx->chip_class == CAYMAN) {
 978                 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
 979                 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
 980                                         S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
 981                                         NULL, 0);
 982                 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
 983                 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
 984                 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
 985                 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
 986
 987
 988         } else {
 989                 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
 990
 991                 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
 992                 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
 993                 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
 994                 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
 995
 996                 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
 997                                         S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
 998                                         NULL, 0);
 999         }
1000         r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
1001         r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
1002         return rstate;
1003 }
1004
1005 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
1006                                         const struct pipe_sampler_state *state)
1007 {
1008         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1009         union util_color uc;
1010         unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
1011
1012         if (rstate == NULL) {
1013                 return NULL;
1014         }
1015
1016         rstate->id = R600_PIPE_STATE_SAMPLER;
1017         util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1018         r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1019                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1020                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1021                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1022                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1023                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1024                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1025                         S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1026                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1027                         S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
1028         r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1029                         S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1030                         S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
1031                         NULL, 0);
1032         r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
1033                                         S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1034                                         (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
1035                                         S_03C008_TYPE(1),
1036                                         NULL, 0);
1037
1038         if (uc.ui) {
1039                 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
1040                 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
1041                 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
1042                 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
1043         }
1044         return rstate;
1045 }
1046
1047 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
1048                                                         struct pipe_resource *texture,
1049                                                         const struct pipe_sampler_view *state)
1050 {
1051         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
1052         struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1053         struct r600_pipe_resource_state *rstate;
1054         struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1055         unsigned format, endian;
1056         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1057         unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1058         unsigned height, depth, width;
1059         unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1060
1061         if (view == NULL)
1062                 return NULL;
1063         rstate = &view->state;
1064
1065         /* initialize base object */
1066         view->base = *state;
1067         view->base.texture = NULL;
1068         pipe_reference(NULL, &texture->reference);
1069         view->base.texture = texture;
1070         view->base.reference.count = 1;
1071         view->base.context = ctx;
1072
1073         swizzle[0] = state->swizzle_r;
1074         swizzle[1] = state->swizzle_g;
1075         swizzle[2] = state->swizzle_b;
1076         swizzle[3] = state->swizzle_a;
1077
1078         format = r600_translate_texformat(ctx->screen, state->format,
1079                                           swizzle,
1080                                           &word4, &yuv_format);
1081         if (format == ~0) {
1082                 format = 0;
1083         }
1084
1085         if (tmp->depth && !tmp->is_flushing_texture) {
1086                 r600_texture_depth_flush(ctx, texture, TRUE);
1087                 tmp = tmp->flushed_depth_texture;
1088         }
1089
1090         endian = r600_colorformat_endian_swap(format);
1091
1092         if (!rscreen->use_surface) {
1093                 height = texture->height0;
1094                 depth = texture->depth0;
1095                 width = texture->width0;
1096                 pitch = align(tmp->pitch_in_blocks[0] *
1097                                 util_format_get_blockwidth(state->format), 8);
1098                 array_mode = tmp->array_mode[0];
1099                 tile_type = tmp->tile_type;
1100                 tile_split = 0;
1101                 macro_aspect = 0;
1102                 bankw = 0;
1103                 bankh = 0;
1104         } else {
1105                 width = tmp->surface.level[0].npix_x;
1106                 height = tmp->surface.level[0].npix_y;
1107                 depth = tmp->surface.level[0].npix_z;
1108                 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1109                 tile_type = tmp->tile_type;
1110
1111                 switch (tmp->surface.level[0].mode) {
1112                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1113                         array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1114                         break;
1115                 case RADEON_SURF_MODE_2D:
1116                         array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1117                         break;
1118                 case RADEON_SURF_MODE_1D:
1119                         array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1120                         break;
1121                 case RADEON_SURF_MODE_LINEAR:
1122                 default:
1123                         array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1124                         break;
1125                 }
1126                 tile_split = tmp->surface.tile_split;
1127                 macro_aspect = tmp->surface.mtilea;
1128                 bankw = tmp->surface.bankw;
1129                 bankh = tmp->surface.bankh;
1130                 tile_split = eg_tile_split(tile_split);
1131                 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1132                 bankw = eg_bank_wh(bankw);
1133                 bankh = eg_bank_wh(bankh);
1134         }
1135         /* 128 bit formats require tile type = 1 */
1136         if (rscreen->chip_class == CAYMAN) {
1137                 if (util_format_get_blocksize(state->format) >= 16)
1138                         tile_type = 1;
1139         }
1140         nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1141
1142         if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1143                 height = 1;
1144                 depth = texture->array_size;
1145         } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1146                 depth = texture->array_size;
1147         }
1148
1149         rstate->bo[0] = &tmp->resource;
1150         rstate->bo[1] = &tmp->resource;
1151         rstate->bo_usage[0] = RADEON_USAGE_READ;
1152         rstate->bo_usage[1] = RADEON_USAGE_READ;
1153
1154         rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1155                           S_030000_PITCH((pitch / 8) - 1) |
1156                           S_030000_TEX_WIDTH(width - 1));
1157         if (rscreen->chip_class == CAYMAN)
1158                 rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1159         else
1160                 rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1161         rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
1162                           S_030004_TEX_DEPTH(depth - 1) |
1163                           S_030004_ARRAY_MODE(array_mode));
1164         rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1165         if (state->u.tex.last_level) {
1166                 rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1167         } else {
1168                 rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1169         }
1170         rstate->val[4] = (word4 |
1171                           S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1172                           S_030010_ENDIAN_SWAP(endian) |
1173                           S_030010_BASE_LEVEL(state->u.tex.first_level));
1174         rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1175                           S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1176                           S_030014_LAST_ARRAY(state->u.tex.last_layer));
1177         /* aniso max 16 samples */
1178         rstate->val[6] = (S_030018_MAX_ANISO(4)) |
1179                          (S_030018_TILE_SPLIT(tile_split));
1180         rstate->val[7] = S_03001C_DATA_FORMAT(format) |
1181                          S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1182                          S_03001C_BANK_WIDTH(bankw) |
1183                          S_03001C_BANK_HEIGHT(bankh) |
1184                          S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1185                          S_03001C_NUM_BANKS(nbanks);
1186
1187         return &view->base;
1188 }
1189
1190 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1191                                         struct pipe_sampler_view **views)
1192 {
1193         struct r600_context *rctx = (struct r600_context *)ctx;
1194         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1195
1196         for (int i = 0; i < count; i++) {
1197                 if (resource[i]) {
1198                         evergreen_context_pipe_state_set_vs_resource(rctx, &resource[i]->state,
1199                                                                      i + R600_MAX_CONST_BUFFERS);
1200                 }
1201         }
1202 }
1203
1204 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1205                                         struct pipe_sampler_view **views)
1206 {
1207         struct r600_context *rctx = (struct r600_context *)ctx;
1208         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1209         int i;
1210         int has_depth = 0;
1211
1212         for (i = 0; i < count; i++) {
1213                 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1214                         if (resource[i]) {
1215                                 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1216                                         has_depth = 1;
1217                                 evergreen_context_pipe_state_set_ps_resource(rctx, &resource[i]->state,
1218                                                                              i + R600_MAX_CONST_BUFFERS);
1219                         } else
1220                                 evergreen_context_pipe_state_set_ps_resource(rctx, NULL,
1221                                                                              i + R600_MAX_CONST_BUFFERS);
1222
1223                         pipe_sampler_view_reference(
1224                                 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1225                                 views[i]);
1226                 } else {
1227                         if (resource[i]) {
1228                                 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1229                                         has_depth = 1;
1230                         }
1231                 }
1232         }
1233         for (i = count; i < NUM_TEX_UNITS; i++) {
1234                 if (rctx->ps_samplers.views[i]) {
1235                         evergreen_context_pipe_state_set_ps_resource(rctx, NULL,
1236                                                                      i + R600_MAX_CONST_BUFFERS);
1237                         pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1238                 }
1239         }
1240         rctx->have_depth_texture = has_depth;
1241         rctx->ps_samplers.n_views = count;
1242 }
1243
1244 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1245 {
1246         struct r600_context *rctx = (struct r600_context *)ctx;
1247         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1248
1249         if (count)
1250                 r600_inval_texture_cache(rctx);
1251
1252         memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1253         rctx->ps_samplers.n_samplers = count;
1254
1255         for (int i = 0; i < count; i++) {
1256                 evergreen_context_pipe_state_set_ps_sampler(rctx, rstates[i], i);
1257         }
1258 }
1259
1260 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1261 {
1262         struct r600_context *rctx = (struct r600_context *)ctx;
1263         struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1264
1265         if (count)
1266                 r600_inval_texture_cache(rctx);
1267
1268         for (int i = 0; i < count; i++) {
1269                 evergreen_context_pipe_state_set_vs_sampler(rctx, rstates[i], i);
1270         }
1271 }
1272
1273 static void evergreen_set_clip_state(struct pipe_context *ctx,
1274                                 const struct pipe_clip_state *state)
1275 {
1276         struct r600_context *rctx = (struct r600_context *)ctx;
1277         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1278         struct pipe_resource *cbuf;
1279
1280         if (rstate == NULL)
1281                 return;
1282
1283         rctx->clip = *state;
1284         rstate->id = R600_PIPE_STATE_CLIP;
1285         for (int i = 0; i < 6; i++) {
1286                 r600_pipe_state_add_reg(rstate,
1287                                         R_0285BC_PA_CL_UCP0_X + i * 16,
1288                                         fui(state->ucp[i][0]), NULL, 0);
1289                 r600_pipe_state_add_reg(rstate,
1290                                         R_0285C0_PA_CL_UCP0_Y + i * 16,
1291                                         fui(state->ucp[i][1]) , NULL, 0);
1292                 r600_pipe_state_add_reg(rstate,
1293                                         R_0285C4_PA_CL_UCP0_Z + i * 16,
1294                                         fui(state->ucp[i][2]), NULL, 0);
1295                 r600_pipe_state_add_reg(rstate,
1296                                         R_0285C8_PA_CL_UCP0_W + i * 16,
1297                                         fui(state->ucp[i][3]), NULL, 0);
1298         }
1299
1300         free(rctx->states[R600_PIPE_STATE_CLIP]);
1301         rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1302         r600_context_pipe_state_set(rctx, rstate);
1303
1304         cbuf = pipe_user_buffer_create(ctx->screen,
1305                                    state->ucp,
1306                                    4*4*8, /* 8*4 floats */
1307                                    PIPE_BIND_CONSTANT_BUFFER);
1308         r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1309         pipe_resource_reference(&cbuf, NULL);
1310 }
1311
1312 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1313                                          const struct pipe_poly_stipple *state)
1314 {
1315 }
1316
1317 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1318 {
1319 }
1320
1321 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1322                                         const struct pipe_scissor_state *state)
1323 {
1324         struct r600_context *rctx = (struct r600_context *)ctx;
1325         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1326         uint32_t tl, br;
1327
1328         if (rstate == NULL)
1329                 return;
1330
1331         rstate->id = R600_PIPE_STATE_SCISSOR;
1332         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1333         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1334         r600_pipe_state_add_reg(rstate,
1335                                 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1336                                 NULL, 0);
1337         r600_pipe_state_add_reg(rstate,
1338                                 R_028214_PA_SC_CLIPRECT_0_BR, br,
1339                                 NULL, 0);
1340         r600_pipe_state_add_reg(rstate,
1341                                 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1342                                 NULL, 0);
1343         r600_pipe_state_add_reg(rstate,
1344                                 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1345                                 NULL, 0);
1346         r600_pipe_state_add_reg(rstate,
1347                                 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1348                                 NULL, 0);
1349         r600_pipe_state_add_reg(rstate,
1350                                 R_028224_PA_SC_CLIPRECT_2_BR, br,
1351                                 NULL, 0);
1352         r600_pipe_state_add_reg(rstate,
1353                                 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1354                                 NULL, 0);
1355         r600_pipe_state_add_reg(rstate,
1356                                 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1357                                 NULL, 0);
1358
1359         free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1360         rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1361         r600_context_pipe_state_set(rctx, rstate);
1362 }
1363
1364 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1365                                         const struct pipe_viewport_state *state)
1366 {
1367         struct r600_context *rctx = (struct r600_context *)ctx;
1368         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1369
1370         if (rstate == NULL)
1371                 return;
1372
1373         rctx->viewport = *state;
1374         rstate->id = R600_PIPE_STATE_VIEWPORT;
1375         r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0);
1376         r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0);
1377         r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1378         r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1379         r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1380         r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1381         r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1382         r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1383         r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0);
1384
1385         free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1386         rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1387         r600_context_pipe_state_set(rctx, rstate);
1388 }
1389
1390 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1391                          const struct pipe_framebuffer_state *state, int cb)
1392 {
1393         struct r600_screen *rscreen = rctx->screen;
1394         struct r600_resource_texture *rtex;
1395         struct r600_surface *surf;
1396         unsigned level = state->cbufs[cb]->u.tex.level;
1397         unsigned pitch, slice;
1398         unsigned color_info, color_attrib;
1399         unsigned format, swap, ntype, endian;
1400         uint64_t offset;
1401         unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1402         const struct util_format_description *desc;
1403         int i;
1404         unsigned blend_clamp = 0, blend_bypass = 0;
1405
1406         surf = (struct r600_surface *)state->cbufs[cb];
1407         rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1408
1409         if (rtex->depth)
1410                 rctx->have_depth_fb = TRUE;
1411
1412         if (rtex->depth && !rtex->is_flushing_texture) {
1413                 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1414                 rtex = rtex->flushed_depth_texture;
1415         }
1416
1417         /* XXX quite sure for dx10+ hw don't need any offset hacks */
1418         if (!rscreen->use_surface) {
1419                 offset = r600_texture_get_offset(rtex,
1420                                 level, state->cbufs[cb]->u.tex.first_layer);
1421                 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1422                 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1423                 if (slice) {
1424                         slice = slice - 1;
1425                 }
1426                 color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1427                 tile_split = 0;
1428                 macro_aspect = 0;
1429                 bankw = 0;
1430                 bankh = 0;
1431                 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1432                         tile_type = rtex->tile_type;
1433                 } else {
1434                         /* workaround for linear buffers */
1435                         tile_type = 1;
1436                 }
1437         } else {
1438                 offset = rtex->surface.level[level].offset;
1439                 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1440                         offset += rtex->surface.level[level].slice_size *
1441                                   state->cbufs[cb]->u.tex.first_layer;
1442                 }
1443                 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1444                 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1445                 if (slice) {
1446                         slice = slice - 1;
1447                 }
1448                 color_info = 0;
1449                 switch (rtex->surface.level[level].mode) {
1450                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1451                         color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1452                         tile_type = 1;
1453                         break;
1454                 case RADEON_SURF_MODE_1D:
1455                         color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1456                         tile_type = rtex->tile_type;
1457                         break;
1458                 case RADEON_SURF_MODE_2D:
1459                         color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1460                         tile_type = rtex->tile_type;
1461                         break;
1462                 case RADEON_SURF_MODE_LINEAR:
1463                 default:
1464                         color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1465                         tile_type = 1;
1466                         break;
1467                 }
1468                 tile_split = rtex->surface.tile_split;
1469                 macro_aspect = rtex->surface.mtilea;
1470                 bankw = rtex->surface.bankw;
1471                 bankh = rtex->surface.bankh;
1472                 tile_split = eg_tile_split(tile_split);
1473                 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1474                 bankw = eg_bank_wh(bankw);
1475                 bankh = eg_bank_wh(bankh);
1476         }
1477         /* 128 bit formats require tile type = 1 */
1478         if (rscreen->chip_class == CAYMAN) {
1479                 if (util_format_get_blocksize(surf->base.format) >= 16)
1480                         tile_type = 1;
1481         }
1482         nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1483         desc = util_format_description(surf->base.format);
1484         for (i = 0; i < 4; i++) {
1485                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1486                         break;
1487                 }
1488         }
1489
1490         color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1491                         S_028C74_NUM_BANKS(nbanks) |
1492                         S_028C74_BANK_WIDTH(bankw) |
1493                         S_028C74_BANK_HEIGHT(bankh) |
1494                         S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1495                         S_028C74_NON_DISP_TILING_ORDER(tile_type);
1496
1497         ntype = V_028C70_NUMBER_UNORM;
1498         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1499                 ntype = V_028C70_NUMBER_SRGB;
1500         else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1501                 if (desc->channel[i].normalized)
1502                         ntype = V_028C70_NUMBER_SNORM;
1503                 else if (desc->channel[i].pure_integer)
1504                         ntype = V_028C70_NUMBER_SINT;
1505         } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1506                 if (desc->channel[i].normalized)
1507                         ntype = V_028C70_NUMBER_UNORM;
1508                 else if (desc->channel[i].pure_integer)
1509                         ntype = V_028C70_NUMBER_UINT;
1510         }
1511
1512         format = r600_translate_colorformat(surf->base.format);
1513         swap = r600_translate_colorswap(surf->base.format);
1514         if (rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1515                 endian = ENDIAN_NONE;
1516         } else {
1517                 endian = r600_colorformat_endian_swap(format);
1518         }
1519
1520         /* blend clamp should be set for all NORM/SRGB types */
1521         if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1522             ntype == V_028C70_NUMBER_SRGB)
1523                 blend_clamp = 1;
1524
1525         /* set blend bypass according to docs if SINT/UINT or
1526            8/24 COLOR variants */
1527         if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1528             format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1529             format == V_028C70_COLOR_X24_8_32_FLOAT) {
1530                 blend_clamp = 0;
1531                 blend_bypass = 1;
1532         }
1533
1534         color_info |= S_028C70_FORMAT(format) |
1535                 S_028C70_COMP_SWAP(swap) |
1536                 S_028C70_BLEND_CLAMP(blend_clamp) |
1537                 S_028C70_BLEND_BYPASS(blend_bypass) |
1538                 S_028C70_NUMBER_TYPE(ntype) |
1539                 S_028C70_ENDIAN(endian);
1540
1541         /* EXPORT_NORM is an optimzation that can be enabled for better
1542          * performance in certain cases.
1543          * EXPORT_NORM can be enabled if:
1544          * - 11-bit or smaller UNORM/SNORM/SRGB
1545          * - 16-bit or smaller FLOAT
1546          */
1547         /* FIXME: This should probably be the same for all CBs if we want
1548          * useful alpha tests. */
1549         if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1550             ((desc->channel[i].size < 12 &&
1551               desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1552               ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1553              (desc->channel[i].size < 17 &&
1554               desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1555                 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1556                 rctx->export_16bpc = true;
1557         } else {
1558                 rctx->export_16bpc = false;
1559         }
1560         rctx->alpha_ref_dirty = true;
1561
1562
1563         offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1564         offset >>= 8;
1565
1566         /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1567         r600_pipe_state_add_reg(rstate,
1568                                 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1569                                 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1570         r600_pipe_state_add_reg(rstate,
1571                                 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1572                                 0x0, NULL, 0);
1573         r600_pipe_state_add_reg(rstate,
1574                                 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1575                                 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1576         r600_pipe_state_add_reg(rstate,
1577                                 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1578                                 S_028C64_PITCH_TILE_MAX(pitch),
1579                                 NULL, 0);
1580         r600_pipe_state_add_reg(rstate,
1581                                 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1582                                 S_028C68_SLICE_TILE_MAX(slice),
1583                                 NULL, 0);
1584         if (!rscreen->use_surface) {
1585                 r600_pipe_state_add_reg(rstate,
1586                                         R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1587                                         0x00000000, NULL, 0);
1588         } else {
1589                 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1590                         r600_pipe_state_add_reg(rstate,
1591                                                 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1592                                                 0x00000000, NULL, 0);
1593                 } else {
1594                         r600_pipe_state_add_reg(rstate,
1595                                                 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1596                                                 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1597                                                 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1598                                                 NULL, 0);
1599                 }
1600         }
1601         r600_pipe_state_add_reg(rstate,
1602                                 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1603                                 color_attrib,
1604                                 &rtex->resource, RADEON_USAGE_READWRITE);
1605 }
1606
1607 static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1608                          const struct pipe_framebuffer_state *state)
1609 {
1610         struct r600_screen *rscreen = rctx->screen;
1611         struct r600_resource_texture *rtex;
1612         struct r600_surface *surf;
1613         uint64_t offset;
1614         unsigned level, first_layer, pitch, slice, format, array_mode;
1615         unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1616
1617         if (state->zsbuf == NULL)
1618                 return;
1619
1620         surf = (struct r600_surface *)state->zsbuf;
1621         level = surf->base.u.tex.level;
1622         rtex = (struct r600_resource_texture*)surf->base.texture;
1623         first_layer = surf->base.u.tex.first_layer;
1624         format = r600_translate_dbformat(rtex->real_format);
1625
1626         offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1627         /* XXX remove this once tiling is properly supported */
1628         if (!rscreen->use_surface) {
1629                 /* XXX remove this once tiling is properly supported */
1630                 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1631                                 V_028C70_ARRAY_1D_TILED_THIN1;
1632
1633                 offset += r600_texture_get_offset(rtex, level, first_layer);
1634                 pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1635                 slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1636                 if (slice) {
1637                         slice = slice - 1;
1638                 }
1639                 tile_split = 0;
1640                 macro_aspect = 0;
1641                 bankw = 0;
1642                 bankh = 0;
1643         } else {
1644                 offset += rtex->surface.level[level].offset;
1645                 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1646                 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1647                 if (slice) {
1648                         slice = slice - 1;
1649                 }
1650                 switch (rtex->surface.level[level].mode) {
1651                 case RADEON_SURF_MODE_2D:
1652                         array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1653                         break;
1654                 case RADEON_SURF_MODE_1D:
1655                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1656                 case RADEON_SURF_MODE_LINEAR:
1657                 default:
1658                         array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1659                         break;
1660                 }
1661                 tile_split = rtex->surface.tile_split;
1662                 macro_aspect = rtex->surface.mtilea;
1663                 bankw = rtex->surface.bankw;
1664                 bankh = rtex->surface.bankh;
1665                 tile_split = eg_tile_split(tile_split);
1666                 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1667                 bankw = eg_bank_wh(bankw);
1668                 bankh = eg_bank_wh(bankh);
1669         }
1670         nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1671         offset >>= 8;
1672
1673         z_info = S_028040_ARRAY_MODE(array_mode) |
1674                  S_028040_FORMAT(format) |
1675                  S_028040_TILE_SPLIT(tile_split)|
1676                  S_028040_NUM_BANKS(nbanks) |
1677                  S_028040_BANK_WIDTH(bankw) |
1678                  S_028040_BANK_HEIGHT(bankh) |
1679                  S_028040_MACRO_TILE_ASPECT(macro_aspect);
1680
1681         r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1682                                 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1683         r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1684                                 offset, &rtex->resource, RADEON_USAGE_READWRITE);
1685         if (!rscreen->use_surface) {
1686                 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1687                                         0x00000000, NULL, 0);
1688         } else {
1689                 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1690                                         S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1691                                         S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1692                                         NULL, 0);
1693         }
1694
1695         if (rtex->stencil) {
1696                 uint64_t stencil_offset =
1697                         r600_texture_get_offset(rtex->stencil, level, first_layer);
1698                 unsigned stile_split;
1699
1700                 stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1701                 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1702                 stencil_offset >>= 8;
1703
1704                 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1705                                         stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1706                 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1707                                         stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1708                 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1709                                         1 | S_028044_TILE_SPLIT(stile_split),
1710                                         &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1711         } else {
1712                 if (rscreen->use_surface && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1713                         uint64_t stencil_offset = rtex->surface.stencil_offset;
1714                         unsigned stile_split = rtex->surface.stencil_tile_split;
1715
1716                         stile_split = eg_tile_split(stile_split);
1717                         stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1718                         stencil_offset += rtex->surface.level[level].offset / 4;
1719                         stencil_offset >>= 8;
1720
1721                         r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1722                                                 stencil_offset, &rtex->resource,
1723                                                 RADEON_USAGE_READWRITE);
1724                         r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1725                                                 stencil_offset, &rtex->resource,
1726                                                 RADEON_USAGE_READWRITE);
1727                         r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1728                                                 1 | S_028044_TILE_SPLIT(stile_split),
1729                                                 &rtex->resource,
1730                                                 RADEON_USAGE_READWRITE);
1731                 } else {
1732                         r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1733                                                 offset, &rtex->resource,
1734                                                 RADEON_USAGE_READWRITE);
1735                         r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1736                                                 offset, &rtex->resource,
1737                                                 RADEON_USAGE_READWRITE);
1738                         r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1739                                                 0, NULL, RADEON_USAGE_READWRITE);
1740                 }
1741         }
1742
1743         r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, z_info,
1744                                 &rtex->resource, RADEON_USAGE_READWRITE);
1745         r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1746                                 S_028058_PITCH_TILE_MAX(pitch),
1747                                 NULL, 0);
1748         r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1749                                 S_02805C_SLICE_TILE_MAX(slice),
1750                                 NULL, 0);
1751 }
1752
1753 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1754                                         const struct pipe_framebuffer_state *state)
1755 {
1756         struct r600_context *rctx = (struct r600_context *)ctx;
1757         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1758         uint32_t shader_mask, tl, br;
1759         int tl_x, tl_y, br_x, br_y;
1760
1761         if (rstate == NULL)
1762                 return;
1763
1764         r600_flush_framebuffer(rctx, false);
1765
1766         /* unreference old buffer and reference new one */
1767         rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1768
1769         util_copy_framebuffer_state(&rctx->framebuffer, state);
1770
1771         /* build states */
1772         rctx->have_depth_fb = 0;
1773         rctx->nr_cbufs = state->nr_cbufs;
1774         for (int i = 0; i < state->nr_cbufs; i++) {
1775                 evergreen_cb(rctx, rstate, state, i);
1776         }
1777         if (state->zsbuf) {
1778                 evergreen_db(rctx, rstate, state);
1779         }
1780
1781         shader_mask = 0;
1782         for (int i = 0; i < state->nr_cbufs; i++) {
1783                 shader_mask |= 0xf << (i * 4);
1784         }
1785         tl_x = 0;
1786         tl_y = 0;
1787         br_x = state->width;
1788         br_y = state->height;
1789         /* EG hw workaround */
1790         if (br_x == 0)
1791                 tl_x = 1;
1792         if (br_y == 0)
1793                 tl_y = 1;
1794         /* cayman hw workaround */
1795         if (rctx->chip_class == CAYMAN) {
1796                 if (br_x == 1 && br_y == 1)
1797                         br_x = 2;
1798         }
1799         tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1800         br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1801
1802         r600_pipe_state_add_reg(rstate,
1803                                 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1804                                 NULL, 0);
1805         r600_pipe_state_add_reg(rstate,
1806                                 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1807                                 NULL, 0);
1808         r600_pipe_state_add_reg(rstate,
1809                                 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1810                                 NULL, 0);
1811         r600_pipe_state_add_reg(rstate,
1812                                 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1813                                 NULL, 0);
1814         r600_pipe_state_add_reg(rstate,
1815                                 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1816                                 NULL, 0);
1817         r600_pipe_state_add_reg(rstate,
1818                                 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1819                                 NULL, 0);
1820         r600_pipe_state_add_reg(rstate,
1821                                 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1822                                 NULL, 0);
1823         r600_pipe_state_add_reg(rstate,
1824                                 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1825                                 NULL, 0);
1826         r600_pipe_state_add_reg(rstate,
1827                                 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1828                                 NULL, 0);
1829         r600_pipe_state_add_reg(rstate,
1830                                 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1831                                 NULL, 0);
1832         r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1833                                 shader_mask, NULL, 0);
1834
1835
1836         if (rctx->chip_class == CAYMAN) {
1837                 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1838                                         0x00000000, NULL, 0);
1839         } else {
1840                 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1841                                         0x00000000, NULL, 0);
1842                 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0,
1843                                         0x00000000, NULL, 0);
1844         }
1845
1846         free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1847         rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1848         r600_context_pipe_state_set(rctx, rstate);
1849
1850         if (state->zsbuf) {
1851                 evergreen_polygon_offset_update(rctx);
1852         }
1853 }
1854
1855 void evergreen_init_state_functions(struct r600_context *rctx)
1856 {
1857         rctx->context.create_blend_state = evergreen_create_blend_state;
1858         rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1859         rctx->context.create_fs_state = r600_create_shader_state;
1860         rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1861         rctx->context.create_sampler_state = evergreen_create_sampler_state;
1862         rctx->context.create_sampler_view = evergreen_create_sampler_view;
1863         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1864         rctx->context.create_vs_state = r600_create_shader_state;
1865         rctx->context.bind_blend_state = r600_bind_blend_state;
1866         rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1867         rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1868         rctx->context.bind_fs_state = r600_bind_ps_shader;
1869         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1870         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1871         rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1872         rctx->context.bind_vs_state = r600_bind_vs_shader;
1873         rctx->context.delete_blend_state = r600_delete_state;
1874         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1875         rctx->context.delete_fs_state = r600_delete_ps_shader;
1876         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1877         rctx->context.delete_sampler_state = r600_delete_state;
1878         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1879         rctx->context.delete_vs_state = r600_delete_vs_shader;
1880         rctx->context.set_blend_color = evergreen_set_blend_color;
1881         rctx->context.set_clip_state = evergreen_set_clip_state;
1882         rctx->context.set_constant_buffer = r600_set_constant_buffer;
1883         rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1884         rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1885         rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1886         rctx->context.set_sample_mask = evergreen_set_sample_mask;
1887         rctx->context.set_scissor_state = evergreen_set_scissor_state;
1888         rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1889         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1890         rctx->context.set_index_buffer = r600_set_index_buffer;
1891         rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1892         rctx->context.set_viewport_state = evergreen_set_viewport_state;
1893         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1894         rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1895         rctx->context.texture_barrier = r600_texture_barrier;
1896         rctx->context.create_stream_output_target = r600_create_so_target;
1897         rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1898         rctx->context.set_stream_output_targets = r600_set_so_targets;
1899 }
1900
1901 static void cayman_init_config(struct r600_context *rctx)
1902 {
1903         struct r600_pipe_state *rstate = &rctx->config;
1904         unsigned tmp;
1905
1906         tmp = 0x00000000;
1907         tmp |= S_008C00_EXPORT_SRC_C(1);
1908         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
1909
1910         /* always set the temp clauses */
1911         r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), NULL, 0);
1912         r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, NULL, 0);
1913         r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, NULL, 0);
1914         r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), NULL, 0);
1915
1916         r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
1917
1918         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
1919         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
1920         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
1921         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
1922         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
1923         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
1924         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
1925         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
1926         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
1927         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
1928         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
1929         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
1930         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
1931         r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
1932         r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
1933         r600_pipe_state_add_reg(rstate, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), NULL, 0);
1934         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
1935         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
1936         r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
1937
1938         r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, NULL, 0);
1939         r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, NULL, 0);
1940         r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, NULL, 0);
1941         r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, NULL, 0);
1942         r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, NULL, 0);
1943         r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, NULL, 0);
1944         r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, NULL, 0);
1945         r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, NULL, 0);
1946         r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, NULL, 0);
1947         r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, NULL, 0);
1948         r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, NULL, 0);
1949         r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, NULL, 0);
1950         r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, NULL, 0);
1951         r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, NULL, 0);
1952         r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, NULL, 0);
1953         r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, NULL, 0);
1954         r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, NULL, 0);
1955         r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, NULL, 0);
1956         r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, NULL, 0);
1957         r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, NULL, 0);
1958         r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, NULL, 0);
1959         r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, NULL, 0);
1960         r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, NULL, 0);
1961         r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, NULL, 0);
1962         r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, NULL, 0);
1963         r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, NULL, 0);
1964         r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, NULL, 0);
1965         r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, NULL, 0);
1966         r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, NULL, 0);
1967         r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, NULL, 0);
1968         r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, NULL, 0);
1969         r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, NULL, 0);
1970
1971         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
1972
1973         r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, NULL, 0);
1974         r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, NULL, 0);
1975
1976         r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, NULL, 0);
1977         r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, NULL, 0);
1978
1979         r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, NULL, 0);
1980         r600_context_pipe_state_set(rctx, rstate);
1981 }
1982
1983 void evergreen_init_config(struct r600_context *rctx)
1984 {
1985         struct r600_pipe_state *rstate = &rctx->config;
1986         int ps_prio;
1987         int vs_prio;
1988         int gs_prio;
1989         int es_prio;
1990         int hs_prio, cs_prio, ls_prio;
1991         int num_ps_gprs;
1992         int num_vs_gprs;
1993         int num_gs_gprs;
1994         int num_es_gprs;
1995         int num_hs_gprs;
1996         int num_ls_gprs;
1997         int num_temp_gprs;
1998         int num_ps_threads;
1999         int num_vs_threads;
2000         int num_gs_threads;
2001         int num_es_threads;
2002         int num_hs_threads;
2003         int num_ls_threads;
2004         int num_ps_stack_entries;
2005         int num_vs_stack_entries;
2006         int num_gs_stack_entries;
2007         int num_es_stack_entries;
2008         int num_hs_stack_entries;
2009         int num_ls_stack_entries;
2010         enum radeon_family family;
2011         unsigned tmp;
2012
2013         family = rctx->family;
2014
2015         if (rctx->chip_class == CAYMAN) {
2016                 cayman_init_config(rctx);
2017                 return;
2018         }
2019
2020         ps_prio = 0;
2021         vs_prio = 1;
2022         gs_prio = 2;
2023         es_prio = 3;
2024         hs_prio = 0;
2025         ls_prio = 0;
2026         cs_prio = 0;
2027
2028         switch (family) {
2029         case CHIP_CEDAR:
2030         default:
2031                 num_ps_gprs = 93;
2032                 num_vs_gprs = 46;
2033                 num_temp_gprs = 4;
2034                 num_gs_gprs = 31;
2035                 num_es_gprs = 31;
2036                 num_hs_gprs = 23;
2037                 num_ls_gprs = 23;
2038                 num_ps_threads = 96;
2039                 num_vs_threads = 16;
2040                 num_gs_threads = 16;
2041                 num_es_threads = 16;
2042                 num_hs_threads = 16;
2043                 num_ls_threads = 16;
2044                 num_ps_stack_entries = 42;
2045                 num_vs_stack_entries = 42;
2046                 num_gs_stack_entries = 42;
2047                 num_es_stack_entries = 42;
2048                 num_hs_stack_entries = 42;
2049                 num_ls_stack_entries = 42;
2050                 break;
2051         case CHIP_REDWOOD:
2052                 num_ps_gprs = 93;
2053                 num_vs_gprs = 46;
2054                 num_temp_gprs = 4;
2055                 num_gs_gprs = 31;
2056                 num_es_gprs = 31;
2057                 num_hs_gprs = 23;
2058                 num_ls_gprs = 23;
2059                 num_ps_threads = 128;
2060                 num_vs_threads = 20;
2061                 num_gs_threads = 20;
2062                 num_es_threads = 20;
2063                 num_hs_threads = 20;
2064                 num_ls_threads = 20;
2065                 num_ps_stack_entries = 42;
2066                 num_vs_stack_entries = 42;
2067                 num_gs_stack_entries = 42;
2068                 num_es_stack_entries = 42;
2069                 num_hs_stack_entries = 42;
2070                 num_ls_stack_entries = 42;
2071                 break;
2072         case CHIP_JUNIPER:
2073                 num_ps_gprs = 93;
2074                 num_vs_gprs = 46;
2075                 num_temp_gprs = 4;
2076                 num_gs_gprs = 31;
2077                 num_es_gprs = 31;
2078                 num_hs_gprs = 23;
2079                 num_ls_gprs = 23;
2080                 num_ps_threads = 128;
2081                 num_vs_threads = 20;
2082                 num_gs_threads = 20;
2083                 num_es_threads = 20;
2084                 num_hs_threads = 20;
2085                 num_ls_threads = 20;
2086                 num_ps_stack_entries = 85;
2087                 num_vs_stack_entries = 85;
2088                 num_gs_stack_entries = 85;
2089                 num_es_stack_entries = 85;
2090                 num_hs_stack_entries = 85;
2091                 num_ls_stack_entries = 85;
2092                 break;
2093         case CHIP_CYPRESS:
2094         case CHIP_HEMLOCK:
2095                 num_ps_gprs = 93;
2096                 num_vs_gprs = 46;
2097                 num_temp_gprs = 4;
2098                 num_gs_gprs = 31;
2099                 num_es_gprs = 31;
2100                 num_hs_gprs = 23;
2101                 num_ls_gprs = 23;
2102                 num_ps_threads = 128;
2103                 num_vs_threads = 20;
2104                 num_gs_threads = 20;
2105                 num_es_threads = 20;
2106                 num_hs_threads = 20;
2107                 num_ls_threads = 20;
2108                 num_ps_stack_entries = 85;
2109                 num_vs_stack_entries = 85;
2110                 num_gs_stack_entries = 85;
2111                 num_es_stack_entries = 85;
2112                 num_hs_stack_entries = 85;
2113                 num_ls_stack_entries = 85;
2114                 break;
2115         case CHIP_PALM:
2116                 num_ps_gprs = 93;
2117                 num_vs_gprs = 46;
2118                 num_temp_gprs = 4;
2119                 num_gs_gprs = 31;
2120                 num_es_gprs = 31;
2121                 num_hs_gprs = 23;
2122                 num_ls_gprs = 23;
2123                 num_ps_threads = 96;
2124                 num_vs_threads = 16;
2125                 num_gs_threads = 16;
2126                 num_es_threads = 16;
2127                 num_hs_threads = 16;
2128                 num_ls_threads = 16;
2129                 num_ps_stack_entries = 42;
2130                 num_vs_stack_entries = 42;
2131                 num_gs_stack_entries = 42;
2132                 num_es_stack_entries = 42;
2133                 num_hs_stack_entries = 42;
2134                 num_ls_stack_entries = 42;
2135                 break;
2136         case CHIP_SUMO:
2137                 num_ps_gprs = 93;
2138                 num_vs_gprs = 46;
2139                 num_temp_gprs = 4;
2140                 num_gs_gprs = 31;
2141                 num_es_gprs = 31;
2142                 num_hs_gprs = 23;
2143                 num_ls_gprs = 23;
2144                 num_ps_threads = 96;
2145                 num_vs_threads = 25;
2146                 num_gs_threads = 25;
2147                 num_es_threads = 25;
2148                 num_hs_threads = 25;
2149                 num_ls_threads = 25;
2150                 num_ps_stack_entries = 42;
2151                 num_vs_stack_entries = 42;
2152                 num_gs_stack_entries = 42;
2153                 num_es_stack_entries = 42;
2154                 num_hs_stack_entries = 42;
2155                 num_ls_stack_entries = 42;
2156                 break;
2157         case CHIP_SUMO2:
2158                 num_ps_gprs = 93;
2159                 num_vs_gprs = 46;
2160                 num_temp_gprs = 4;
2161                 num_gs_gprs = 31;
2162                 num_es_gprs = 31;
2163                 num_hs_gprs = 23;
2164                 num_ls_gprs = 23;
2165                 num_ps_threads = 96;
2166                 num_vs_threads = 25;
2167                 num_gs_threads = 25;
2168                 num_es_threads = 25;
2169                 num_hs_threads = 25;
2170                 num_ls_threads = 25;
2171                 num_ps_stack_entries = 85;
2172                 num_vs_stack_entries = 85;
2173                 num_gs_stack_entries = 85;
2174                 num_es_stack_entries = 85;
2175                 num_hs_stack_entries = 85;
2176                 num_ls_stack_entries = 85;
2177                 break;
2178         case CHIP_BARTS:
2179                 num_ps_gprs = 93;
2180                 num_vs_gprs = 46;
2181                 num_temp_gprs = 4;
2182                 num_gs_gprs = 31;
2183                 num_es_gprs = 31;
2184                 num_hs_gprs = 23;
2185                 num_ls_gprs = 23;
2186                 num_ps_threads = 128;
2187                 num_vs_threads = 20;
2188                 num_gs_threads = 20;
2189                 num_es_threads = 20;
2190                 num_hs_threads = 20;
2191                 num_ls_threads = 20;
2192                 num_ps_stack_entries = 85;
2193                 num_vs_stack_entries = 85;
2194                 num_gs_stack_entries = 85;
2195                 num_es_stack_entries = 85;
2196                 num_hs_stack_entries = 85;
2197                 num_ls_stack_entries = 85;
2198                 break;
2199         case CHIP_TURKS:
2200                 num_ps_gprs = 93;
2201                 num_vs_gprs = 46;
2202                 num_temp_gprs = 4;
2203                 num_gs_gprs = 31;
2204                 num_es_gprs = 31;
2205                 num_hs_gprs = 23;
2206                 num_ls_gprs = 23;
2207                 num_ps_threads = 128;
2208                 num_vs_threads = 20;
2209                 num_gs_threads = 20;
2210                 num_es_threads = 20;
2211                 num_hs_threads = 20;
2212                 num_ls_threads = 20;
2213                 num_ps_stack_entries = 42;
2214                 num_vs_stack_entries = 42;
2215                 num_gs_stack_entries = 42;
2216                 num_es_stack_entries = 42;
2217                 num_hs_stack_entries = 42;
2218                 num_ls_stack_entries = 42;
2219                 break;
2220         case CHIP_CAICOS:
2221                 num_ps_gprs = 93;
2222                 num_vs_gprs = 46;
2223                 num_temp_gprs = 4;
2224                 num_gs_gprs = 31;
2225                 num_es_gprs = 31;
2226                 num_hs_gprs = 23;
2227                 num_ls_gprs = 23;
2228                 num_ps_threads = 128;
2229                 num_vs_threads = 10;
2230                 num_gs_threads = 10;
2231                 num_es_threads = 10;
2232                 num_hs_threads = 10;
2233                 num_ls_threads = 10;
2234                 num_ps_stack_entries = 42;
2235                 num_vs_stack_entries = 42;
2236                 num_gs_stack_entries = 42;
2237                 num_es_stack_entries = 42;
2238                 num_hs_stack_entries = 42;
2239                 num_ls_stack_entries = 42;
2240                 break;
2241         }
2242
2243         tmp = 0x00000000;
2244         switch (family) {
2245         case CHIP_CEDAR:
2246         case CHIP_PALM:
2247         case CHIP_SUMO:
2248         case CHIP_SUMO2:
2249         case CHIP_CAICOS:
2250                 break;
2251         default:
2252                 tmp |= S_008C00_VC_ENABLE(1);
2253                 break;
2254         }
2255         tmp |= S_008C00_EXPORT_SRC_C(1);
2256         tmp |= S_008C00_CS_PRIO(cs_prio);
2257         tmp |= S_008C00_LS_PRIO(ls_prio);
2258         tmp |= S_008C00_HS_PRIO(hs_prio);
2259         tmp |= S_008C00_PS_PRIO(ps_prio);
2260         tmp |= S_008C00_VS_PRIO(vs_prio);
2261         tmp |= S_008C00_GS_PRIO(gs_prio);
2262         tmp |= S_008C00_ES_PRIO(es_prio);
2263         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
2264
2265         /* enable dynamic GPR resource management */
2266         if (rctx->screen->info.drm_minor >= 7) {
2267                 /* always set temp clauses */
2268                 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
2269                                         S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), NULL, 0);
2270                 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, NULL, 0);
2271                 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, NULL, 0);
2272                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), NULL, 0);
2273                 r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2274                                         S_028838_PS_GPRS(0x1e) |
2275                                         S_028838_VS_GPRS(0x1e) |
2276                                         S_028838_GS_GPRS(0x1e) |
2277                                         S_028838_ES_GPRS(0x1e) |
2278                                         S_028838_HS_GPRS(0x1e) |
2279                                         S_028838_LS_GPRS(0x1e), NULL, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2280         } else {
2281                 tmp = 0;
2282                 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2283                 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2284                 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2285                 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0);
2286
2287                 tmp = 0;
2288                 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2289                 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2290                 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, NULL, 0);
2291
2292                 tmp = 0;
2293                 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2294                 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2295                 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, NULL, 0);
2296         }
2297
2298         tmp = 0;
2299         tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
2300         tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2301         tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2302         tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2303         r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, NULL, 0);
2304
2305         tmp = 0;
2306         tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
2307         tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2308         r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, NULL, 0);
2309
2310         tmp = 0;
2311         tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2312         tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2313         r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, NULL, 0);
2314
2315         tmp = 0;
2316         tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2317         tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2318         r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, NULL, 0);
2319
2320         tmp = 0;
2321         tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2322         tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2323         r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, NULL, 0);
2324
2325         tmp = 0;
2326         tmp |= S_008E2C_NUM_PS_LDS(0x1000);
2327         tmp |= S_008E2C_NUM_LS_LDS(0x1000);
2328         r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, NULL, 0);
2329
2330         r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, NULL, 0);
2331         r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), NULL, 0);
2332
2333 #if 0
2334         r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, NULL, 0);
2335
2336         r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, NULL, 0);
2337 #endif
2338         r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
2339
2340         r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, NULL, 0);
2341         r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, NULL, 0);
2342         r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2343         r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2344         r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2345         r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
2346
2347         r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, NULL, 0);
2348         r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, NULL, 0);
2349         r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, NULL, 0);
2350         r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, NULL, 0);
2351
2352         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
2353         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
2354         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
2355         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
2356         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
2357         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
2358         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
2359         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
2360         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
2361         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
2362         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
2363         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
2364         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
2365         r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
2366         r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
2367         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
2368         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
2369         r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
2370
2371         r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, NULL, 0);
2372         r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, NULL, 0);
2373         r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, NULL, 0);
2374         r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, NULL, 0);
2375         r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, NULL, 0);
2376         r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, NULL, 0);
2377         r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, NULL, 0);
2378         r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, NULL, 0);
2379         r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, NULL, 0);
2380         r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, NULL, 0);
2381         r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, NULL, 0);
2382         r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, NULL, 0);
2383         r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, NULL, 0);
2384         r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, NULL, 0);
2385         r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, NULL, 0);
2386         r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, NULL, 0);
2387         r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, NULL, 0);
2388         r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, NULL, 0);
2389         r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, NULL, 0);
2390         r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, NULL, 0);
2391         r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, NULL, 0);
2392         r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, NULL, 0);
2393         r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, NULL, 0);
2394         r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, NULL, 0);
2395         r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, NULL, 0);
2396         r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, NULL, 0);
2397         r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, NULL, 0);
2398         r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, NULL, 0);
2399         r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, NULL, 0);
2400         r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, NULL, 0);
2401         r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, NULL, 0);
2402         r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, NULL, 0);
2403
2404         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
2405
2406         r600_context_pipe_state_set(rctx, rstate);
2407 }
2408
2409 void evergreen_polygon_offset_update(struct r600_context *rctx)
2410 {
2411         struct r600_pipe_state state;
2412
2413         state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2414         state.nregs = 0;
2415         if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2416                 float offset_units = rctx->rasterizer->offset_units;
2417                 unsigned offset_db_fmt_cntl = 0, depth;
2418
2419                 switch (rctx->framebuffer.zsbuf->texture->format) {
2420                 case PIPE_FORMAT_Z24X8_UNORM:
2421                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2422                         depth = -24;
2423                         offset_units *= 2.0f;
2424                         break;
2425                 case PIPE_FORMAT_Z32_FLOAT:
2426                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2427                         depth = -23;
2428                         offset_units *= 1.0f;
2429                         offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2430                         break;
2431                 case PIPE_FORMAT_Z16_UNORM:
2432                         depth = -16;
2433                         offset_units *= 4.0f;
2434                         break;
2435                 default:
2436                         return;
2437                 }
2438                 /* FIXME some of those reg can be computed with cso */
2439                 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2440                 r600_pipe_state_add_reg(&state,
2441                                 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2442                                 fui(rctx->rasterizer->offset_scale), NULL, 0);
2443                 r600_pipe_state_add_reg(&state,
2444                                 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2445                                 fui(offset_units), NULL, 0);
2446                 r600_pipe_state_add_reg(&state,
2447                                 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2448                                 fui(rctx->rasterizer->offset_scale), NULL, 0);
2449                 r600_pipe_state_add_reg(&state,
2450                                 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2451                                 fui(offset_units), NULL, 0);
2452                 r600_pipe_state_add_reg(&state,
2453                                 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2454                                 offset_db_fmt_cntl, NULL, 0);
2455                 r600_context_pipe_state_set(rctx, &state);
2456         }
2457 }
2458
2459 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2460 {
2461         struct r600_context *rctx = (struct r600_context *)ctx;
2462         struct r600_pipe_state *rstate = &shader->rstate;
2463         struct r600_shader *rshader = &shader->shader;
2464         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2465         int pos_index = -1, face_index = -1;
2466         int ninterp = 0;
2467         boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2468         unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2469
2470         rstate->nregs = 0;
2471
2472         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2473         for (i = 0; i < rshader->ninput; i++) {
2474                 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2475                    POSITION goes via GPRs from the SC so isn't counted */
2476                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2477                         pos_index = i;
2478                 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2479                         face_index = i;
2480                 else {
2481                         ninterp++;
2482                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2483                                 have_linear = TRUE;
2484                         if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2485                                 have_perspective = TRUE;
2486                         if (rshader->input[i].centroid)
2487                                 have_centroid = TRUE;
2488                 }
2489
2490                 sid = rshader->input[i].spi_sid;
2491
2492                 if (sid) {
2493
2494                         tmp = S_028644_SEMANTIC(sid);
2495
2496                         if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2497                                 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2498                                 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2499                                         rctx->rasterizer && rctx->rasterizer->flatshade)) {
2500                                 tmp |= S_028644_FLAT_SHADE(1);
2501                         }
2502
2503                         if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2504                                         (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2505                                 tmp |= S_028644_PT_SPRITE_TEX(1);
2506                         }
2507
2508                         r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2509                                         tmp, NULL, 0);
2510
2511                         idx++;
2512                 }
2513         }
2514
2515         for (i = 0; i < rshader->noutput; i++) {
2516                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2517                         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2518                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2519                         db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2520         }
2521         if (rshader->uses_kill)
2522                 db_shader_control |= S_02880C_KILL_ENABLE(1);
2523
2524         exports_ps = 0;
2525         num_cout = 0;
2526         for (i = 0; i < rshader->noutput; i++) {
2527                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2528                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2529                         exports_ps |= 1;
2530                 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2531                         if (rshader->fs_write_all)
2532                                 num_cout = rshader->nr_cbufs;
2533                         else
2534                                 num_cout++;
2535                 }
2536         }
2537         exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2538         if (!exports_ps) {
2539                 /* always at least export 1 component per pixel */
2540                 exports_ps = 2;
2541         }
2542
2543         if (ninterp == 0) {
2544                 ninterp = 1;
2545                 have_perspective = TRUE;
2546         }
2547
2548         if (!have_perspective && !have_linear)
2549                 have_perspective = TRUE;
2550
2551         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2552                               S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2553                               S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2554         spi_input_z = 0;
2555         if (pos_index != -1) {
2556                 spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
2557                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2558                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2559                 spi_input_z |= 1;
2560         }
2561
2562         spi_ps_in_control_1 = 0;
2563         if (face_index != -1) {
2564                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2565                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2566         }
2567
2568         spi_baryc_cntl = 0;
2569         if (have_perspective)
2570                 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2571                                   S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2572         if (have_linear)
2573                 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2574                                   S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2575
2576         r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2577                                 spi_ps_in_control_0, NULL, 0);
2578         r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2579                                 spi_ps_in_control_1, NULL, 0);
2580         r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2581                                 0, NULL, 0);
2582         r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
2583         r600_pipe_state_add_reg(rstate,
2584                                 R_0286E0_SPI_BARYC_CNTL,
2585                                 spi_baryc_cntl,
2586                                 NULL, 0);
2587
2588         r600_pipe_state_add_reg(rstate,
2589                                 R_028840_SQ_PGM_START_PS,
2590                                 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2591                                 shader->bo, RADEON_USAGE_READ);
2592         r600_pipe_state_add_reg(rstate,
2593                                 R_028844_SQ_PGM_RESOURCES_PS,
2594                                 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2595                                 S_028844_PRIME_CACHE_ON_DRAW(1) |
2596                                 S_028844_STACK_SIZE(rshader->bc.nstack),
2597                                 NULL, 0);
2598         r600_pipe_state_add_reg(rstate,
2599                                 R_028848_SQ_PGM_RESOURCES_2_PS,
2600                                 S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2601                                 NULL, 0);
2602         r600_pipe_state_add_reg(rstate,
2603                                 R_02884C_SQ_PGM_EXPORTS_PS,
2604                                 exports_ps, NULL, 0);
2605         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2606                                 db_shader_control,
2607                                 NULL, 0);
2608         r600_pipe_state_add_reg(rstate,
2609                                 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
2610                                 NULL, 0);
2611
2612         shader->sprite_coord_enable = rctx->sprite_coord_enable;
2613         if (rctx->rasterizer)
2614                 shader->flatshade = rctx->rasterizer->flatshade;
2615 }
2616
2617 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2618 {
2619         struct r600_context *rctx = (struct r600_context *)ctx;
2620         struct r600_pipe_state *rstate = &shader->rstate;
2621         struct r600_shader *rshader = &shader->shader;
2622         unsigned spi_vs_out_id[10] = {};
2623         unsigned i, tmp, nparams = 0;
2624
2625         /* clear previous register */
2626         rstate->nregs = 0;
2627
2628         for (i = 0; i < rshader->noutput; i++) {
2629                 if (rshader->output[i].spi_sid) {
2630                         tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2631                         spi_vs_out_id[nparams / 4] |= tmp;
2632                         nparams++;
2633                 }
2634         }
2635
2636         for (i = 0; i < 10; i++) {
2637                 r600_pipe_state_add_reg(rstate,
2638                                         R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2639                                         spi_vs_out_id[i], NULL, 0);
2640         }
2641
2642         /* Certain attributes (position, psize, etc.) don't count as params.
2643          * VS is required to export at least one param and r600_shader_from_tgsi()
2644          * takes care of adding a dummy export.
2645          */
2646         if (nparams < 1)
2647                 nparams = 1;
2648
2649         r600_pipe_state_add_reg(rstate,
2650                         R_0286C4_SPI_VS_OUT_CONFIG,
2651                         S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2652                         NULL, 0);
2653         r600_pipe_state_add_reg(rstate,
2654                         R_028860_SQ_PGM_RESOURCES_VS,
2655                         S_028860_NUM_GPRS(rshader->bc.ngpr) |
2656                         S_028860_STACK_SIZE(rshader->bc.nstack),
2657                         NULL, 0);
2658         r600_pipe_state_add_reg(rstate,
2659                                 R_028864_SQ_PGM_RESOURCES_2_VS,
2660                                 S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO),
2661                                 NULL, 0);
2662         r600_pipe_state_add_reg(rstate,
2663                         R_02885C_SQ_PGM_START_VS,
2664                         r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2665                         shader->bo, RADEON_USAGE_READ);
2666
2667         r600_pipe_state_add_reg(rstate,
2668                                 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2669                                 NULL, 0);
2670
2671         shader->pa_cl_vs_out_cntl =
2672                 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2673                 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2674                 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2675                 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2676 }
2677
2678 void evergreen_fetch_shader(struct pipe_context *ctx,
2679                             struct r600_vertex_element *ve)
2680 {
2681         struct r600_context *rctx = (struct r600_context *)ctx;
2682         struct r600_pipe_state *rstate = &ve->rstate;
2683         rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2684         rstate->nregs = 0;
2685         r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
2686                                 0x00000000, NULL, 0);
2687         r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2688                                 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2689                                 ve->fetch_shader, RADEON_USAGE_READ);
2690 }
2691
2692 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2693 {
2694         struct pipe_depth_stencil_alpha_state dsa;
2695         struct r600_pipe_state *rstate;
2696
2697         memset(&dsa, 0, sizeof(dsa));
2698
2699         rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2700         r600_pipe_state_add_reg(rstate,
2701                                 R_028000_DB_RENDER_CONTROL,
2702                                 S_028000_DEPTH_COPY_ENABLE(1) |
2703                                 S_028000_STENCIL_COPY_ENABLE(1) |
2704                                 S_028000_COPY_CENTROID(1),
2705                                 NULL, 0);
2706         return rstate;
2707 }
2708
2709 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
2710                                          struct r600_pipe_resource_state *rstate)
2711 {
2712         rstate->id = R600_PIPE_STATE_RESOURCE;
2713
2714         rstate->val[0] = 0;
2715         rstate->bo[0] = NULL;
2716         rstate->val[1] = 0;
2717         rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2718         rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2719           S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2720           S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2721           S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2722         rstate->val[4] = 0;
2723         rstate->val[5] = 0;
2724         rstate->val[6] = 0;
2725         rstate->val[7] = 0xc0000000;
2726 }
2727
2728
2729 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
2730                                         struct r600_pipe_resource_state *rstate,
2731                                         struct r600_resource *rbuffer,
2732                                         unsigned offset, unsigned stride,
2733                                         enum radeon_bo_usage usage)
2734 {
2735         uint64_t va;
2736
2737         va = r600_resource_va(ctx->screen, (void *)rbuffer);
2738         rstate->bo[0] = rbuffer;
2739         rstate->bo_usage[0] = usage;
2740         rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
2741         rstate->val[1] = rbuffer->buf->size - offset - 1;
2742         rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2743                          S_030008_STRIDE(stride) |
2744                          (((va + offset) >> 32UL) & 0xFF);
2745 }