2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Joakim Sindholt <opensource@zhasha.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #include "r300_surface.h"
26 /* Provides pipe_context's "surface_fill". Commonly used for clearing
28 static void r300_surface_fill(struct pipe_context* pipe,
29 struct pipe_surface* dest,
30 unsigned x, unsigned y,
31 unsigned w, unsigned h,
34 struct r300_context* r300 = r300_context(pipe);
36 struct r300_capabilities* caps = ((struct r300_screen*)pipe->screen)->caps;
37 struct r300_texture* tex = (struct r300_texture*)dest->texture;
40 r = (float)((color >> 16) & 0xff) / 255.0f;
41 g = (float)((color >> 8) & 0xff) / 255.0f;
42 b = (float)((color >> 0) & 0xff) / 255.0f;
43 debug_printf("r300: Filling surface %p at (%d,%d),"
44 " dimensions %dx%d (stride %d), color 0x%x\n",
45 dest, x, y, w, h, dest->stride, color);
49 debug_printf("r300: Falling back on surface clear...");
50 void* map = pipe->screen->surface_map(pipe->screen, dest,
51 PIPE_BUFFER_USAGE_CPU_WRITE);
52 pipe_fill_rect(map, &dest->block, &dest->stride, x, y, w, h, color);
53 pipe->screen->surface_unmap(pipe->screen, dest);
57 BEGIN_CS(168 + (caps->is_r500 ? 22 : 14) + (caps->has_tcl ? 4 : 2));
59 OUT_CS_REG(R300_TX_INVALTAGS, 0x0);
62 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
64 OUT_CS_REG(R300_SE_VTE_CNTL, R300_VPORT_X_SCALE_ENA |
65 R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
66 R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
67 R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT);
69 OUT_CS_REG(R300_VAP_VTX_SIZE, 0x8);
70 /* Max and min vertex index clamp. */
71 OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, 0xFFFFFF);
72 OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX, 0x0);
74 OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP);
75 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x0);
76 /* XXX magic number not in r300_reg */
77 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
78 OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0);
79 OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
84 /* XXX is this too long? */
85 OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xFFFF);
86 OUT_CS_REG(R300_GB_ENABLE, R300_GB_POINT_STUFF_ENABLE |
87 R300_GB_LINE_STUFF_ENABLE | R300_GB_TRIANGLE_STUFF_ENABLE);
88 /* XXX more magic numbers */
89 OUT_CS_REG(R300_GB_MSPOS0, 0x66666666);
90 OUT_CS_REG(R300_GB_MSPOS1, 0x66666666);
91 /* XXX why doesn't classic Mesa write the number of pipes, too? */
92 OUT_CS_REG(R300_GB_TILE_CONFIG, R300_GB_TILE_ENABLE |
93 R300_GB_TILE_SIZE_16);
94 OUT_CS_REG(R300_GB_SELECT, R300_GB_FOG_SELECT_1_1_W);
95 OUT_CS_REG(R300_GB_AA_CONFIG, 0x0);
96 /* XXX point tex stuffing */
97 OUT_CS_REG_SEQ(R300_GA_POINT_S0, 1);
99 OUT_CS_REG_SEQ(R300_GA_POINT_S1, 1);
101 OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 |
102 (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT));
103 /* XXX should this be related to the actual point size? */
104 OUT_CS_REG(R300_GA_POINT_MINMAX, 0x6 |
105 (0x1800 << R300_GA_POINT_MINMAX_MAX_SHIFT));
106 /* XXX this big chunk should be refactored into rs_state */
107 OUT_CS_REG(R300_GA_LINE_CNTL, 0x00030006);
108 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, 0x3BAAAAAB);
109 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, 0x00000000);
110 OUT_CS_REG(R300_GA_LINE_S0, 0x00000000);
111 OUT_CS_REG(R300_GA_LINE_S1, 0x3F800000);
112 OUT_CS_REG(R300_GA_ENHANCE, 0x00000002);
113 OUT_CS_REG(R300_GA_COLOR_CONTROL, 0x0003AAAA);
114 OUT_CS_REG(R300_GA_SOLID_RG, 0x00000000);
115 OUT_CS_REG(R300_GA_SOLID_BA, 0x00000000);
116 OUT_CS_REG(R300_GA_POLY_MODE, 0x00000000);
117 OUT_CS_REG(R300_GA_ROUND_MODE, 0x00000001);
118 OUT_CS_REG(R300_GA_OFFSET, 0x00000000);
119 OUT_CS_REG(R300_GA_FOG_SCALE, 0x3DBF1412);
120 OUT_CS_REG(R300_GA_FOG_OFFSET, 0x00000000);
121 OUT_CS_REG(R300_SU_TEX_WRAP, 0x00000000);
122 OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_SCALE, 0x00000000);
123 OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_OFFSET, 0x00000000);
124 OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_SCALE, 0x00000000);
125 OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_OFFSET, 0x00000000);
126 OUT_CS_REG(R300_SU_POLY_OFFSET_ENABLE, 0x00000000);
127 OUT_CS_REG(R300_SU_CULL_MODE, 0x00000000);
128 OUT_CS_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
129 OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000);
130 OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C);
131 OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
132 OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF);
133 OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000002);
134 OUT_CS_REG(R300_FG_FOG_COLOR_R, 0x00000000);
135 OUT_CS_REG(R300_FG_FOG_COLOR_G, 0x00000000);
136 OUT_CS_REG(R300_FG_FOG_COLOR_B, 0x00000000);
137 OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
138 OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
139 OUT_CS_REG(R300_RB3D_CCTL, 0x00000000);
140 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
142 /* XXX: Oh the wonderful unknown.
143 * Not writing these 8 regs seems to make no difference at all and seeing
144 * as how they're not documented, we should leave them out for now.
145 OUT_CS_REG_SEQ(0x4E54, 8);
146 for (i = 0; i < 8; i++) {
149 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
150 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000);
151 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF);
152 OUT_CS_REG(R300_ZB_FORMAT, 0x00000002);
153 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003);
154 OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000);
155 OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0x00000000);
156 /* XXX Moar unknown that should probably be left out.
157 OUT_CS_REG(0x4F30, 0x00000000);
158 OUT_CS_REG(0x4F34, 0x00000000); */
159 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000);
160 OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000);
163 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
164 (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
165 ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) |
166 R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
168 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
169 (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
170 ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) |
171 R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
173 OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000000);
174 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xF688F688);
175 OUT_CS_REG(R300_VAP_VTX_STATE_CNTL, 0x1);
176 OUT_CS_REG(R300_VAP_VSM_VTX_ASSM, 0x405);
177 OUT_CS_REG(R300_SE_VTE_CNTL, 0x0000043F);
178 OUT_CS_REG(R300_VAP_VTX_SIZE, 0x00000008);
179 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
180 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0, 0x00000003);
181 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x00000000);
182 OUT_CS_REG(R300_TX_ENABLE, 0x0);
183 /* XXX viewport setup */
184 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
186 OUT_CS_32F((float)x);
188 OUT_CS_32F((float)y);
193 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE |
194 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
197 OUT_CS_REG(R300_GA_POINT_SIZE,
198 ((h * 6) & R300_POINTSIZE_Y_MASK) |
199 ((w * 6) << R300_POINTSIZE_X_SHIFT));
203 /* XXX We seem to be in disagreement about how many of these we have
204 * RS:RS_IP_[0-15] [R/W] 32 bits Access: 8/16/32 MMReg:0x4074-0x40b0
205 * Now that's from the docs. I don't care what the mesa driver says */
206 OUT_CS_REG_SEQ(R500_RS_IP_0, 16);
207 for (i = 0; i < 16; i++) {
208 OUT_CS((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
209 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
210 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
211 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
213 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
214 OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
216 OUT_CS_REG(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
218 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
219 for (i = 0; i < 8; i++) {
220 OUT_CS(R300_RS_SEL_T(R300_RS_SEL_K0) |
221 R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1));
223 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
224 OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
225 /* XXX Shouldn't this be 0? */
227 OUT_CS_REG(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
231 /* Fragment shader setup */
233 r500_emit_fragment_shader(r300, &r500_passthrough_fragment_shader);
235 r300_emit_fragment_shader(r300, &r300_passthrough_fragment_shader);
238 BEGIN_CS(2 + (caps->has_tcl ? 23 : 2));
239 /* XXX these magic numbers should be explained when
240 * this becomes a cached state object */
242 OUT_CS_REG(R300_VAP_CNTL, 0xA |
243 (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
244 (0xB << R300_VF_MAX_VTX_NUM_SHIFT) |
245 (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
246 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000);
247 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000);
248 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001);
250 /* XXX translate these back into normal instructions */
251 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1);
252 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0);
253 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 8);
263 OUT_CS_REG(R300_VAP_CNTL, 0xA |
264 (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
265 (0x5 << R300_VF_MAX_VTX_NUM_SHIFT) |
266 (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
271 r300_emit_blend_state(r300, &blend_clear_state);
272 r300_emit_blend_color_state(r300, &blend_color_clear_state);
273 r300_emit_dsa_state(r300, &dsa_clear_state);
277 /* Flush colorbuffer and blend caches. */
278 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
279 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D |
280 R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL);
281 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
282 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
283 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
285 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
286 OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
287 /* XXX (dest->stride >> 2) should be the buffer width in pixels however,
288 * this little calculation is only good as long as the buffer is 32bpp */
289 OUT_CS_REG(R300_RB3D_COLORPITCH0, (dest->stride >> 2) |
290 R300_COLOR_FORMAT_ARGB8888);
291 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
293 OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
294 OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
295 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
298 /* XXX this should be the depth value to clear to */
306 /* XXX figure out why this is 0xA and not 0x2 */
307 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
308 /* XXX OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
309 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
310 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); */
311 OUT_CS_REG(R300_SC_SCREENDOOR, 0x00000000);
313 OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF);
318 r300->dirty_state = R300_NEW_KITCHEN_SINK;
321 void r300_init_surface_functions(struct r300_context* r300)
323 r300->context.surface_fill = r300_surface_fill;