2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23 #include "r300_surface.h"
25 /* Provides pipe_context's "surface_fill". Commonly used for clearing
27 static void r300_surface_fill(struct pipe_context* pipe,
28 struct pipe_surface* dest,
29 unsigned x, unsigned y,
30 unsigned w, unsigned h,
33 struct r300_context* r300 = r300_context(pipe);
35 struct r300_capabilities* caps = ((struct r300_screen*)pipe->screen)->caps;
38 r = (float)((color >> 16) & 0xff) / 255.0f;
39 g = (float)((color >> 8) & 0xff) / 255.0f;
40 b = (float)((color >> 0) & 0xff) / 255.0f;
41 debug_printf("r300: Filling surface %p at (%d,%d),"
42 " dimensions %dx%d, color 0x%x\n",
43 dest, x, y, w, h, color);
47 debug_printf("r300: Falling back on surface clear...");
48 void* map = pipe->screen->surface_map(pipe->screen, dest,
49 PIPE_BUFFER_USAGE_CPU_WRITE);
50 pipe_fill_rect(map, &dest->block, &dest->stride, x, y, w, h, color);
51 pipe->screen->surface_unmap(pipe->screen, dest);
55 BEGIN_CS((caps->is_r500) ? 300 : 322);
57 OUT_CS_REG(R300_TX_INVALTAGS, 0x0);
60 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
62 OUT_CS_REG(R300_SE_VTE_CNTL, R300_VPORT_X_SCALE_ENA |
63 R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
64 R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
65 R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT);
67 OUT_CS_REG(R300_VAP_VTX_SIZE, 0x8);
68 /* Max and min vertex index clamp. */
69 OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, 0xFFFFFF);
70 OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX, 0x0);
72 OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP);
73 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x0);
74 /* XXX magic number not in r300_reg */
75 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
76 OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0);
77 OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
82 /* XXX is this too long? */
83 OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xFFFF);
84 OUT_CS_REG(R300_GB_ENABLE, R300_GB_POINT_STUFF_ENABLE |
85 R300_GB_LINE_STUFF_ENABLE | R300_GB_TRIANGLE_STUFF_ENABLE);
86 /* XXX more magic numbers */
87 OUT_CS_REG(R300_GB_MSPOS0, 0x66666666);
88 OUT_CS_REG(R300_GB_MSPOS1, 0x66666666);
89 /* XXX why doesn't classic Mesa write the number of pipes, too? */
90 OUT_CS_REG(R300_GB_TILE_CONFIG, R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16);
91 OUT_CS_REG(R300_GB_SELECT, R300_GB_FOG_SELECT_1_1_W);
92 OUT_CS_REG(R300_GB_AA_CONFIG, 0x0);
93 /* XXX point tex stuffing */
94 OUT_CS_REG_SEQ(R300_GA_POINT_S0, 1);
96 OUT_CS_REG_SEQ(R300_GA_POINT_S1, 1);
98 OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 |
99 (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT));
100 /* XXX should this be related to the actual point size? */
101 OUT_CS_REG(R300_GA_POINT_MINMAX, 0x6 |
102 (0x1800 << R300_GA_POINT_MINMAX_MAX_SHIFT));
103 /* XXX this big chunk should be refactored into rs_state */
104 OUT_CS_REG(R300_GA_LINE_CNTL, 0x00030006);
105 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, 0x3BAAAAAB);
106 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, 0x00000000);
107 OUT_CS_REG(R300_GA_LINE_S0, 0x00000000);
108 OUT_CS_REG(R300_GA_LINE_S1, 0x3F800000);
109 OUT_CS_REG(R300_GA_ENHANCE, 0x00000002);
110 OUT_CS_REG(R300_GA_COLOR_CONTROL, 0x0003AAAA);
111 OUT_CS_REG(R300_GA_SOLID_RG, 0x00000000);
112 OUT_CS_REG(R300_GA_SOLID_BA, 0x00000000);
113 OUT_CS_REG(R300_GA_POLY_MODE, 0x00000000);
114 OUT_CS_REG(R300_GA_ROUND_MODE, 0x00000001);
115 OUT_CS_REG(R300_GA_OFFSET, 0x00000000);
116 OUT_CS_REG(R300_GA_FOG_SCALE, 0x3DBF1412);
117 OUT_CS_REG(R300_GA_FOG_OFFSET, 0x00000000);
118 OUT_CS_REG(R300_SU_TEX_WRAP, 0x00000000);
119 OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_SCALE, 0x00000000);
120 OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_OFFSET, 0x00000000);
121 OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_SCALE, 0x00000000);
122 OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_OFFSET, 0x00000000);
123 OUT_CS_REG(R300_SU_POLY_OFFSET_ENABLE, 0x00000000);
124 OUT_CS_REG(R300_SU_CULL_MODE, 0x00000000);
125 OUT_CS_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
126 OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000);
127 OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C);
128 OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
129 OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF);
130 OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000002);
131 OUT_CS_REG(R300_FG_FOG_COLOR_R, 0x00000000);
132 OUT_CS_REG(R300_FG_FOG_COLOR_G, 0x00000000);
133 OUT_CS_REG(R300_FG_FOG_COLOR_B, 0x00000000);
134 OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
135 OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
136 OUT_CS_REG(R300_RB3D_CCTL, 0x00000000);
137 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
139 /* XXX: Oh the wonderful unknown */
140 OUT_CS_REG_SEQ(0x4E54, 8);
141 for (i = 0; i < 8; i++)
143 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
144 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000);
145 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF);
146 OUT_CS_REG(R300_ZB_FORMAT, 0x00000002);
147 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003);
148 OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000);
149 OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0x00000000);
150 OUT_CS_REG(0x4F30, 0x00000000);
151 OUT_CS_REG(0x4F34, 0x00000000);
152 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000);
153 OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000);
155 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x21030003);
156 OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000000);
157 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xF688F688);
158 OUT_CS_REG(R300_VAP_VTX_STATE_CNTL, 0x1);
159 OUT_CS_REG(R300_VAP_VSM_VTX_ASSM, 0x405);
160 OUT_CS_REG(R300_SE_VTE_CNTL, 0x0000043F);
161 OUT_CS_REG(R300_VAP_VTX_SIZE, 0x00000008);
162 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
163 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0, 0x00000003);
164 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x00000000);
165 OUT_CS_REG(R300_TX_ENABLE, 0x0);
166 /* XXX viewport setup */
167 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
169 OUT_CS_32F((float)x);
171 OUT_CS_32F((float)y);
175 OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0001C000);
176 OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) |
177 ((w * 6) << R300_POINTSIZE_X_SHIFT));
179 /* XXX RS block and fp setup */
181 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
182 for (i = 0; i < 8; i++) {
183 /* I like the operator macros more than the shift macros... */
184 OUT_CS((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
185 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
186 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
187 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
190 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
191 OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
193 OUT_CS_REG(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
195 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
196 OUT_CS_REG(R500_US_PIXSIZE, 0x00000000);
197 OUT_CS_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) |
198 R500_US_CODE_END_ADDR(1));
199 OUT_CS_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) |
200 R500_US_CODE_RANGE_SIZE(1));
201 OUT_CS_REG(R500_US_CODE_OFFSET, R500_US_CODE_OFFSET_ADDR(0));
203 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
204 0 | R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
205 OUT_CS_REG(R500_GA_US_VECTOR_DATA,
206 R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST |
207 R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B |
208 R500_INST_ALPHA_OMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP);
209 OUT_CS_REG(R500_GA_US_VECTOR_DATA,
210 R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST |
211 R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST);
212 OUT_CS_REG(R500_GA_US_VECTOR_DATA,
213 R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST |
214 R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST);
215 OUT_CS_REG(R500_GA_US_VECTOR_DATA,
216 R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R |
217 R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B |
218 R500_ALU_RGB_SEL_B_SRC0 | R500_ALU_RGB_R_SWIZ_B_R |
219 R500_ALU_RGB_B_SWIZ_B_G | R500_ALU_RGB_G_SWIZ_B_B);
220 OUT_CS_REG(R500_GA_US_VECTOR_DATA,
221 R500_ALPHA_OP_CMP | R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_A);
222 OUT_CS_REG(R500_GA_US_VECTOR_DATA,
223 R500_ALU_RGBA_OP_CMP | R500_ALU_RGBA_R_SWIZ_0 |
224 R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 |
225 R500_ALU_RGBA_A_SWIZ_0);
227 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
228 for (i = 0; i < 8; i++) {
229 OUT_CS(R300_RS_SEL_T(R300_RS_SEL_K0) |
230 R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1));
233 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
234 OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
236 OUT_CS_REG(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
238 /* XXX magic numbers */
239 OUT_CS_REG(R300_US_CONFIG, 0);
240 OUT_CS_REG(R300_US_PIXSIZE, 2);
241 OUT_CS_REG(R300_US_CODE_OFFSET, 0x0);
242 OUT_CS_REG(R300_US_CODE_ADDR_0, 0x0);
243 OUT_CS_REG(R300_US_CODE_ADDR_1, 0x0);
244 OUT_CS_REG(R300_US_CODE_ADDR_2, 0x0);
245 OUT_CS_REG(R300_US_CODE_ADDR_3, 0x400000);
246 OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x50A80);
247 OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x1C000000);
248 OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x40889);
249 OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1000000);
250 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
251 OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_C3_SEL_A);
252 OUT_CS(R300_US_OUT_FMT_UNUSED);
253 OUT_CS(R300_US_OUT_FMT_UNUSED);
254 OUT_CS(R300_US_OUT_FMT_UNUSED);
255 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0);
257 /* XXX these magic numbers should be explained when
258 * this becomes a cached state object */
259 OUT_CS_REG(R300_VAP_CNTL, 0xA | (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
260 (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
261 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000);
262 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000);
263 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001);
265 /* XXX translate these back into normal instructions */
266 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1);
267 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0);
268 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF00203);
269 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10001);
270 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248001);
271 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0);
272 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF02203);
273 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10021);
274 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248021);
275 OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0);
277 r300_emit_blend_state(r300, &blend_clear_state);
278 r300_emit_blend_color_state(r300, &blend_color_clear_state);
279 r300_emit_dsa_state(r300, &dsa_clear_state);
282 /* Flush colorbuffer and blend caches. */
283 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
284 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D |
285 R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL);
286 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
287 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
288 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
290 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
291 OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
292 /* XXX this should not be so rigid */
293 OUT_CS_REG(R300_RB3D_COLORPITCH0, (w / 4) | R300_COLOR_TILE_ENABLE |
294 R300_COLOR_FORMAT_ARGB8888);
295 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
297 OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
298 OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
299 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
302 /* XXX this should be the depth value to clear to */
310 /* XXX figure out why this is 0xA and not 0x2 */
311 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
312 /* XXX OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
313 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
314 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); */
320 r300->dirty_state = R300_NEW_KITCHEN_SINK;
323 void r300_init_surface_functions(struct r300_context* r300)
325 r300->context.surface_fill = r300_surface_fill;