src/gallium/drivers/r300/r300_state_derived.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2009 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #include "draw/draw_context.h"
  25
  26 #include "util/u_math.h"
  27 #include "util/u_memory.h"
  28 #include "util/u_pack_color.h"
  29
  30 #include "r300_context.h"
  31 #include "r300_fs.h"
  32 #include "r300_screen.h"
  33 #include "r300_shader_semantics.h"
  34 #include "r300_state_inlines.h"
  35 #include "r300_texture.h"
  36 #include "r300_vs.h"
  37
  38 /* r300_state_derived: Various bits of state which are dependent upon
  39  * currently bound CSO data. */
  40
  41 enum r300_rs_swizzle {
  42     SWIZ_XYZW = 0,
  43     SWIZ_X001,
  44     SWIZ_XY01,
  45     SWIZ_0001,
  46 };
  47
  48 enum r300_rs_col_write_type {
  49     WRITE_COLOR = 0,
  50     WRITE_FACE
  51 };
  52
  53 static void r300_draw_emit_attrib(struct r300_context* r300,
  54                                   enum attrib_emit emit,
  55                                   enum interp_mode interp,
  56                                   int index)
  57 {
  58     struct r300_vertex_shader* vs = r300->vs_state.state;
  59     struct tgsi_shader_info* info = &vs->info;
  60     int output;
  61
  62     output = draw_find_shader_output(r300->draw,
  63                                      info->output_semantic_name[index],
  64                                      info->output_semantic_index[index]);
  65     draw_emit_vertex_attr(&r300->vertex_info, emit, interp, output);
  66 }
  67
  68 static void r300_draw_emit_all_attribs(struct r300_context* r300)
  69 {
  70     struct r300_vertex_shader* vs = r300->vs_state.state;
  71     struct r300_shader_semantics* vs_outputs = &vs->outputs;
  72     int i, gen_count;
  73
  74     /* Position. */
  75     if (vs_outputs->pos != ATTR_UNUSED) {
  76         r300_draw_emit_attrib(r300, EMIT_4F, INTERP_PERSPECTIVE,
  77                               vs_outputs->pos);
  78     } else {
  79         assert(0);
  80     }
  81
  82     /* Point size. */
  83     if (vs_outputs->psize != ATTR_UNUSED) {
  84         r300_draw_emit_attrib(r300, EMIT_1F_PSIZE, INTERP_POS,
  85                               vs_outputs->psize);
  86     }
  87
  88     /* Colors. */
  89     for (i = 0; i < ATTR_COLOR_COUNT; i++) {
  90         if (vs_outputs->color[i] != ATTR_UNUSED) {
  91             r300_draw_emit_attrib(r300, EMIT_4F, INTERP_LINEAR,
  92                                   vs_outputs->color[i]);
  93         }
  94     }
  95
  96     /* Back-face colors. */
  97     for (i = 0; i < ATTR_COLOR_COUNT; i++) {
  98         if (vs_outputs->bcolor[i] != ATTR_UNUSED) {
  99             r300_draw_emit_attrib(r300, EMIT_4F, INTERP_LINEAR,
 100                                   vs_outputs->bcolor[i]);
 101         }
 102     }
 103
 104     /* Texture coordinates. */
 105     /* Only 8 generic vertex attributes can be used. If there are more,
 106      * they won't be rasterized. */
 107     gen_count = 0;
 108     for (i = 0; i < ATTR_GENERIC_COUNT && gen_count < 8; i++) {
 109         if (vs_outputs->generic[i] != ATTR_UNUSED &&
 110             !(r300->sprite_coord_enable & (1 << i))) {
 111             r300_draw_emit_attrib(r300, EMIT_4F, INTERP_PERSPECTIVE,
 112                                   vs_outputs->generic[i]);
 113             gen_count++;
 114         }
 115     }
 116
 117     /* Fog coordinates. */
 118     if (gen_count < 8 && vs_outputs->fog != ATTR_UNUSED) {
 119         r300_draw_emit_attrib(r300, EMIT_4F, INTERP_PERSPECTIVE,
 120                               vs_outputs->fog);
 121         gen_count++;
 122     }
 123
 124     /* WPOS. */
 125     if (r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED && gen_count < 8) {
 126         DBG(r300, DBG_SWTCL, "draw_emit_attrib: WPOS, index: %i\n",
 127             vs_outputs->wpos);
 128         r300_draw_emit_attrib(r300, EMIT_4F, INTERP_PERSPECTIVE,
 129                               vs_outputs->wpos);
 130     }
 131 }
 132
 133 /* Update the PSC tables for SW TCL, using Draw. */
 134 static void r300_swtcl_vertex_psc(struct r300_context *r300)
 135 {
 136     struct r300_vertex_stream_state *vstream = r300->vertex_stream_state.state;
 137     struct vertex_info *vinfo = &r300->vertex_info;
 138     uint16_t type, swizzle;
 139     enum pipe_format format;
 140     unsigned i, attrib_count;
 141     int* vs_output_tab = r300->stream_loc_notcl;
 142
 143     memset(vstream, 0, sizeof(struct r300_vertex_stream_state));
 144
 145     /* For each Draw attribute, route it to the fragment shader according
 146      * to the vs_output_tab. */
 147     attrib_count = vinfo->num_attribs;
 148     DBG(r300, DBG_SWTCL, "r300: attrib count: %d\n", attrib_count);
 149     for (i = 0; i < attrib_count; i++) {
 150         if (vs_output_tab[i] == -1) {
 151             assert(0);
 152             abort();
 153         }
 154
 155         format = draw_translate_vinfo_format(vinfo->attrib[i].emit);
 156
 157         DBG(r300, DBG_SWTCL,
 158             "r300: swtcl_vertex_psc [%i] <- %s\n",
 159             vs_output_tab[i], util_format_short_name(format));
 160
 161         /* Obtain the type of data in this attribute. */
 162         type = r300_translate_vertex_data_type(format);
 163         if (type == R300_INVALID_FORMAT) {
 164             fprintf(stderr, "r300: Bad vertex format %s.\n",
 165                     util_format_short_name(format));
 166             assert(0);
 167             abort();
 168         }
 169
 170         type |= vs_output_tab[i] << R300_DST_VEC_LOC_SHIFT;
 171
 172         /* Obtain the swizzle for this attribute. Note that the default
 173          * swizzle in the hardware is not XYZW! */
 174         swizzle = r300_translate_vertex_data_swizzle(format);
 175
 176         /* Add the attribute to the PSC table. */
 177         if (i & 1) {
 178             vstream->vap_prog_stream_cntl[i >> 1] |= type << 16;
 179             vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16;
 180         } else {
 181             vstream->vap_prog_stream_cntl[i >> 1] |= type;
 182             vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle;
 183         }
 184     }
 185
 186     /* Set the last vector in the PSC. */
 187     if (i) {
 188         i -= 1;
 189     }
 190     vstream->vap_prog_stream_cntl[i >> 1] |=
 191         (R300_LAST_VEC << (i & 1 ? 16 : 0));
 192
 193     vstream->count = (i >> 1) + 1;
 194     r300_mark_atom_dirty(r300, &r300->vertex_stream_state);
 195     r300->vertex_stream_state.size = (1 + vstream->count) * 2;
 196 }
 197
 198 static void r300_rs_col(struct r300_rs_block* rs, int id, int ptr,
 199                         enum r300_rs_swizzle swiz)
 200 {
 201     rs->ip[id] |= R300_RS_COL_PTR(ptr);
 202     if (swiz == SWIZ_0001) {
 203         rs->ip[id] |= R300_RS_COL_FMT(R300_RS_COL_FMT_0001);
 204     } else {
 205         rs->ip[id] |= R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA);
 206     }
 207     rs->inst[id] |= R300_RS_INST_COL_ID(id);
 208 }
 209
 210 static void r300_rs_col_write(struct r300_rs_block* rs, int id, int fp_offset,
 211                               enum r300_rs_col_write_type type)
 212 {
 213     assert(type == WRITE_COLOR);
 214     rs->inst[id] |= R300_RS_INST_COL_CN_WRITE |
 215                     R300_RS_INST_COL_ADDR(fp_offset);
 216 }
 217
 218 static void r300_rs_tex(struct r300_rs_block* rs, int id, int ptr,
 219                         enum r300_rs_swizzle swiz)
 220 {
 221     if (swiz == SWIZ_X001) {
 222         rs->ip[id] |= R300_RS_TEX_PTR(ptr) |
 223                       R300_RS_SEL_S(R300_RS_SEL_C0) |
 224                       R300_RS_SEL_T(R300_RS_SEL_K0) |
 225                       R300_RS_SEL_R(R300_RS_SEL_K0) |
 226                       R300_RS_SEL_Q(R300_RS_SEL_K1);
 227     } else if (swiz == SWIZ_XY01) {
 228         rs->ip[id] |= R300_RS_TEX_PTR(ptr) |
 229                       R300_RS_SEL_S(R300_RS_SEL_C0) |
 230                       R300_RS_SEL_T(R300_RS_SEL_C1) |
 231                       R300_RS_SEL_R(R300_RS_SEL_K0) |
 232                       R300_RS_SEL_Q(R300_RS_SEL_K1);
 233     } else {
 234         rs->ip[id] |= R300_RS_TEX_PTR(ptr) |
 235                       R300_RS_SEL_S(R300_RS_SEL_C0) |
 236                       R300_RS_SEL_T(R300_RS_SEL_C1) |
 237                       R300_RS_SEL_R(R300_RS_SEL_C2) |
 238                       R300_RS_SEL_Q(R300_RS_SEL_C3);
 239     }
 240     rs->inst[id] |= R300_RS_INST_TEX_ID(id);
 241 }
 242
 243 static void r300_rs_tex_write(struct r300_rs_block* rs, int id, int fp_offset)
 244 {
 245     rs->inst[id] |= R300_RS_INST_TEX_CN_WRITE |
 246                     R300_RS_INST_TEX_ADDR(fp_offset);
 247 }
 248
 249 static void r500_rs_col(struct r300_rs_block* rs, int id, int ptr,
 250                         enum r300_rs_swizzle swiz)
 251 {
 252     rs->ip[id] |= R500_RS_COL_PTR(ptr);
 253     if (swiz == SWIZ_0001) {
 254         rs->ip[id] |= R500_RS_COL_FMT(R300_RS_COL_FMT_0001);
 255     } else {
 256         rs->ip[id] |= R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA);
 257     }
 258     rs->inst[id] |= R500_RS_INST_COL_ID(id);
 259 }
 260
 261 static void r500_rs_col_write(struct r300_rs_block* rs, int id, int fp_offset,
 262                               enum r300_rs_col_write_type type)
 263 {
 264     if (type == WRITE_FACE)
 265         rs->inst[id] |= R500_RS_INST_COL_CN_WRITE_BACKFACE |
 266                         R500_RS_INST_COL_ADDR(fp_offset);
 267     else
 268         rs->inst[id] |= R500_RS_INST_COL_CN_WRITE |
 269                         R500_RS_INST_COL_ADDR(fp_offset);
 270
 271 }
 272
 273 static void r500_rs_tex(struct r300_rs_block* rs, int id, int ptr,
 274                         enum r300_rs_swizzle swiz)
 275 {
 276     if (swiz == SWIZ_X001) {
 277         rs->ip[id] |= R500_RS_SEL_S(ptr) |
 278                       R500_RS_SEL_T(R500_RS_IP_PTR_K0) |
 279                       R500_RS_SEL_R(R500_RS_IP_PTR_K0) |
 280                       R500_RS_SEL_Q(R500_RS_IP_PTR_K1);
 281     } else if (swiz == SWIZ_XY01) {
 282         rs->ip[id] |= R500_RS_SEL_S(ptr) |
 283                       R500_RS_SEL_T(ptr + 1) |
 284                       R500_RS_SEL_R(R500_RS_IP_PTR_K0) |
 285                       R500_RS_SEL_Q(R500_RS_IP_PTR_K1);
 286     } else {
 287         rs->ip[id] |= R500_RS_SEL_S(ptr) |
 288                       R500_RS_SEL_T(ptr + 1) |
 289                       R500_RS_SEL_R(ptr + 2) |
 290                       R500_RS_SEL_Q(ptr + 3);
 291     }
 292     rs->inst[id] |= R500_RS_INST_TEX_ID(id);
 293 }
 294
 295 static void r500_rs_tex_write(struct r300_rs_block* rs, int id, int fp_offset)
 296 {
 297     rs->inst[id] |= R500_RS_INST_TEX_CN_WRITE |
 298                     R500_RS_INST_TEX_ADDR(fp_offset);
 299 }
 300
 301 /* Set up the RS block.
 302  *
 303  * This is the part of the chipset that is responsible for linking vertex
 304  * and fragment shaders and stuffed texture coordinates.
 305  *
 306  * The rasterizer reads data from VAP, which produces vertex shader outputs,
 307  * and GA, which produces stuffed texture coordinates. VAP outputs have
 308  * precedence over GA. All outputs must be rasterized otherwise it locks up.
 309  * If there are more outputs rasterized than is set in VAP/GA, it locks up
 310  * too. The funky part is that this info has been pretty much obtained by trial
 311  * and error. */
 312 static void r300_update_rs_block(struct r300_context *r300)
 313 {
 314     struct r300_vertex_shader *vs = r300->vs_state.state;
 315     struct r300_shader_semantics *vs_outputs = &vs->outputs;
 316     struct r300_shader_semantics *fs_inputs = &r300_fs(r300)->shader->inputs;
 317     struct r300_rs_block rs = {0};
 318     int i, col_count = 0, tex_count = 0, fp_offset = 0, count, loc = 0, tex_ptr = 0;
 319     void (*rX00_rs_col)(struct r300_rs_block*, int, int, enum r300_rs_swizzle);
 320     void (*rX00_rs_col_write)(struct r300_rs_block*, int, int, enum r300_rs_col_write_type);
 321     void (*rX00_rs_tex)(struct r300_rs_block*, int, int, enum r300_rs_swizzle);
 322     void (*rX00_rs_tex_write)(struct r300_rs_block*, int, int);
 323     boolean any_bcolor_used = vs_outputs->bcolor[0] != ATTR_UNUSED ||
 324                               vs_outputs->bcolor[1] != ATTR_UNUSED;
 325     int *stream_loc_notcl = r300->stream_loc_notcl;
 326     uint32_t stuffing_enable = 0;
 327
 328     if (r300->screen->caps.is_r500) {
 329         rX00_rs_col       = r500_rs_col;
 330         rX00_rs_col_write = r500_rs_col_write;
 331         rX00_rs_tex       = r500_rs_tex;
 332         rX00_rs_tex_write = r500_rs_tex_write;
 333     } else {
 334         rX00_rs_col       = r300_rs_col;
 335         rX00_rs_col_write = r300_rs_col_write;
 336         rX00_rs_tex       = r300_rs_tex;
 337         rX00_rs_tex_write = r300_rs_tex_write;
 338     }
 339
 340     /* 0x5555 copied from classic, which means:
 341      * Select user color 0 for COLOR0 up to COLOR7.
 342      * What the hell does that mean? */
 343     rs.vap_vtx_state_cntl = 0x5555;
 344
 345     /* The position is always present in VAP. */
 346     rs.vap_vsm_vtx_assm |= R300_INPUT_CNTL_POS;
 347     rs.vap_out_vtx_fmt[0] |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT;
 348     stream_loc_notcl[loc++] = 0;
 349
 350     /* Set up the point size in VAP. */
 351     if (vs_outputs->psize != ATTR_UNUSED) {
 352         rs.vap_out_vtx_fmt[0] |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT;
 353         stream_loc_notcl[loc++] = 1;
 354     }
 355
 356     /* Set up and rasterize colors. */
 357     for (i = 0; i < ATTR_COLOR_COUNT; i++) {
 358         if (vs_outputs->color[i] != ATTR_UNUSED || any_bcolor_used ||
 359             vs_outputs->color[1] != ATTR_UNUSED) {
 360             /* Set up the color in VAP. */
 361             rs.vap_vsm_vtx_assm |= R300_INPUT_CNTL_COLOR;
 362             rs.vap_out_vtx_fmt[0] |=
 363                     R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT << i;
 364             stream_loc_notcl[loc++] = 2 + i;
 365
 366             /* Rasterize it. */
 367             rX00_rs_col(&rs, col_count, col_count, SWIZ_XYZW);
 368
 369             /* Write it to the FS input register if it's needed by the FS. */
 370             if (fs_inputs->color[i] != ATTR_UNUSED) {
 371                 rX00_rs_col_write(&rs, col_count, fp_offset, WRITE_COLOR);
 372                 fp_offset++;
 373
 374                 DBG(r300, DBG_RS,
 375                     "r300: Rasterized color %i written to FS.\n", i);
 376             } else {
 377                 DBG(r300, DBG_RS, "r300: Rasterized color %i unused.\n", i);
 378             }
 379             col_count++;
 380         } else {
 381             /* Skip the FS input register, leave it uninitialized. */
 382             /* If we try to set it to (0,0,0,1), it will lock up. */
 383             if (fs_inputs->color[i] != ATTR_UNUSED) {
 384                 fp_offset++;
 385
 386                 DBG(r300, DBG_RS, "r300: FS input color %i unassigned%s.\n",
 387                     i);
 388             }
 389         }
 390     }
 391
 392     /* Set up back-face colors. The rasterizer will do the color selection
 393      * automatically. */
 394     if (any_bcolor_used) {
 395         if (r300->two_sided_color) {
 396             /* Rasterize as back-face colors. */
 397             for (i = 0; i < ATTR_COLOR_COUNT; i++) {
 398                 rs.vap_vsm_vtx_assm |= R300_INPUT_CNTL_COLOR;
 399                 rs.vap_out_vtx_fmt[0] |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT << (2+i);
 400                 stream_loc_notcl[loc++] = 4 + i;
 401             }
 402         } else {
 403             /* Rasterize two fake texcoords to prevent from the two-sided color
 404              * selection. */
 405             /* XXX Consider recompiling the vertex shader to save 2 RS units. */
 406             for (i = 0; i < 2; i++) {
 407                 rs.vap_vsm_vtx_assm |= (R300_INPUT_CNTL_TC0 << tex_count);
 408                 rs.vap_out_vtx_fmt[1] |= (4 << (3 * tex_count));
 409                 stream_loc_notcl[loc++] = 6 + tex_count;
 410
 411                 /* Rasterize it. */
 412                 rX00_rs_tex(&rs, tex_count, tex_ptr, SWIZ_XYZW);
 413                 tex_count++;
 414                 tex_ptr += 4;
 415             }
 416         }
 417     }
 418
 419     /* gl_FrontFacing.
 420      * Note that we can use either the two-sided color selection based on
 421      * the front and back vertex shader colors, or gl_FrontFacing,
 422      * but not both! It locks up otherwise.
 423      *
 424      * In Direct3D 9, the two-sided color selection can be used
 425      * with shaders 2.0 only, while gl_FrontFacing can be used
 426      * with shaders 3.0 only. The hardware apparently hasn't been designed
 427      * to support both at the same time. */
 428     if (r300->screen->caps.is_r500 && fs_inputs->face != ATTR_UNUSED &&
 429         !(any_bcolor_used && r300->two_sided_color)) {
 430         rX00_rs_col(&rs, col_count, col_count, SWIZ_XYZW);
 431         rX00_rs_col_write(&rs, col_count, fp_offset, WRITE_FACE);
 432         fp_offset++;
 433         col_count++;
 434         DBG(r300, DBG_RS, "r300: Rasterized FACE written to FS.\n");
 435     } else if (fs_inputs->face != ATTR_UNUSED) {
 436         fprintf(stderr, "r300: ERROR: FS input FACE unassigned.\n");
 437     }
 438
 439     /* Rasterize texture coordinates. */
 440     for (i = 0; i < ATTR_GENERIC_COUNT && tex_count < 8; i++) {
 441         boolean sprite_coord = false;
 442
 443         if (fs_inputs->generic[i] != ATTR_UNUSED) {
 444             sprite_coord = !!(r300->sprite_coord_enable & (1 << i));
 445         }
 446
 447         if (vs_outputs->generic[i] != ATTR_UNUSED || sprite_coord) {
 448             if (!sprite_coord) {
 449                 /* Set up the texture coordinates in VAP. */
 450                 rs.vap_vsm_vtx_assm |= (R300_INPUT_CNTL_TC0 << tex_count);
 451                 rs.vap_out_vtx_fmt[1] |= (4 << (3 * tex_count));
 452                 stream_loc_notcl[loc++] = 6 + tex_count;
 453             } else
 454                 stuffing_enable |=
 455                     R300_GB_TEX_ST << (R300_GB_TEX0_SOURCE_SHIFT + (tex_count*2));
 456
 457             /* Rasterize it. */
 458             rX00_rs_tex(&rs, tex_count, tex_ptr,
 459                         sprite_coord ? SWIZ_XY01 : SWIZ_XYZW);
 460
 461             /* Write it to the FS input register if it's needed by the FS. */
 462             if (fs_inputs->generic[i] != ATTR_UNUSED) {
 463                 rX00_rs_tex_write(&rs, tex_count, fp_offset);
 464                 fp_offset++;
 465
 466                 DBG(r300, DBG_RS,
 467                     "r300: Rasterized generic %i written to FS%s in texcoord %d.\n",
 468                     i, sprite_coord ? " (sprite coord)" : "", tex_count);
 469             } else {
 470                 DBG(r300, DBG_RS,
 471                     "r300: Rasterized generic %i unused%s.\n",
 472                     i, sprite_coord ? " (sprite coord)" : "");
 473             }
 474             tex_count++;
 475             tex_ptr += sprite_coord ? 2 : 4;
 476         } else {
 477             /* Skip the FS input register, leave it uninitialized. */
 478             /* If we try to set it to (0,0,0,1), it will lock up. */
 479             if (fs_inputs->generic[i] != ATTR_UNUSED) {
 480                 fp_offset++;
 481
 482                 DBG(r300, DBG_RS, "r300: FS input generic %i unassigned%s.\n",
 483                     i, sprite_coord ? " (sprite coord)" : "");
 484             }
 485         }
 486     }
 487
 488     for (; i < ATTR_GENERIC_COUNT; i++) {
 489         if (fs_inputs->generic[i] != ATTR_UNUSED) {
 490             fprintf(stderr, "r300: ERROR: FS input generic %i unassigned, "
 491                     "not enough hardware slots (it's not a bug, do not "
 492                     "report it).\n", i);
 493         }
 494     }
 495
 496     /* Rasterize fog coordinates. */
 497     if (vs_outputs->fog != ATTR_UNUSED && tex_count < 8) {
 498         /* Set up the fog coordinates in VAP. */
 499         rs.vap_vsm_vtx_assm |= (R300_INPUT_CNTL_TC0 << tex_count);
 500         rs.vap_out_vtx_fmt[1] |= (4 << (3 * tex_count));
 501         stream_loc_notcl[loc++] = 6 + tex_count;
 502
 503         /* Rasterize it. */
 504         rX00_rs_tex(&rs, tex_count, tex_ptr, SWIZ_X001);
 505
 506         /* Write it to the FS input register if it's needed by the FS. */
 507         if (fs_inputs->fog != ATTR_UNUSED) {
 508             rX00_rs_tex_write(&rs, tex_count, fp_offset);
 509             fp_offset++;
 510
 511             DBG(r300, DBG_RS, "r300: Rasterized fog written to FS.\n");
 512         } else {
 513             DBG(r300, DBG_RS, "r300: Rasterized fog unused.\n");
 514         }
 515         tex_count++;
 516         tex_ptr += 4;
 517     } else {
 518         /* Skip the FS input register, leave it uninitialized. */
 519         /* If we try to set it to (0,0,0,1), it will lock up. */
 520         if (fs_inputs->fog != ATTR_UNUSED) {
 521             fp_offset++;
 522
 523             if (tex_count < 8) {
 524                 DBG(r300, DBG_RS, "r300: FS input fog unassigned.\n");
 525             } else {
 526                 fprintf(stderr, "r300: ERROR: FS input fog unassigned, "
 527                         "not enough hardware slots. (it's not a bug, "
 528                         "do not report it)\n");
 529             }
 530         }
 531     }
 532
 533     /* Rasterize WPOS. */
 534     /* Don't set it in VAP if the FS doesn't need it. */
 535     if (fs_inputs->wpos != ATTR_UNUSED && tex_count < 8) {
 536         /* Set up the WPOS coordinates in VAP. */
 537         rs.vap_vsm_vtx_assm |= (R300_INPUT_CNTL_TC0 << tex_count);
 538         rs.vap_out_vtx_fmt[1] |= (4 << (3 * tex_count));
 539         stream_loc_notcl[loc++] = 6 + tex_count;
 540
 541         /* Rasterize it. */
 542         rX00_rs_tex(&rs, tex_count, tex_ptr, SWIZ_XYZW);
 543
 544         /* Write it to the FS input register. */
 545         rX00_rs_tex_write(&rs, tex_count, fp_offset);
 546
 547         DBG(r300, DBG_RS, "r300: Rasterized WPOS written to FS.\n");
 548
 549         fp_offset++;
 550         tex_count++;
 551         tex_ptr += 4;
 552     } else {
 553         if (fs_inputs->wpos != ATTR_UNUSED && tex_count >= 8) {
 554             fprintf(stderr, "r300: ERROR: FS input WPOS unassigned, "
 555                     "not enough hardware slots. (it's not a bug, do not "
 556                     "report it)\n");
 557         }
 558     }
 559
 560     /* Invalidate the rest of the no-TCL (GA) stream locations. */
 561     for (; loc < 16;) {
 562         stream_loc_notcl[loc++] = -1;
 563     }
 564
 565     /* Rasterize at least one color, or bad things happen. */
 566     if (col_count == 0 && tex_count == 0) {
 567         rX00_rs_col(&rs, 0, 0, SWIZ_0001);
 568         col_count++;
 569
 570         DBG(r300, DBG_RS, "r300: Rasterized color 0 to prevent lockups.\n");
 571     }
 572
 573     DBG(r300, DBG_RS, "r300: --- Rasterizer status ---: colors: %i, "
 574         "generics: %i.\n", col_count, tex_count);
 575
 576     rs.count = MIN2(tex_ptr, 32) | (col_count << R300_IC_COUNT_SHIFT) |
 577         R300_HIRES_EN;
 578
 579     count = MAX3(col_count, tex_count, 1);
 580     rs.inst_count = count - 1;
 581
 582     /* set the GB enable flags */
 583     if (r300->sprite_coord_enable)
 584         stuffing_enable |= R300_GB_POINT_STUFF_ENABLE;
 585
 586     rs.gb_enable = stuffing_enable;
 587
 588     /* Now, after all that, see if we actually need to update the state. */
 589     if (memcmp(r300->rs_block_state.state, &rs, sizeof(struct r300_rs_block))) {
 590         memcpy(r300->rs_block_state.state, &rs, sizeof(struct r300_rs_block));
 591         r300->rs_block_state.size = 13 + count*2;
 592     }
 593 }
 594
 595 static void rgba_to_bgra(float color[4])
 596 {
 597     float x = color[0];
 598     color[0] = color[2];
 599     color[2] = x;
 600 }
 601
 602 static uint32_t r300_get_border_color(enum pipe_format format,
 603                                       const float border[4],
 604                                       boolean is_r500)
 605 {
 606     const struct util_format_description *desc;
 607     float border_swizzled[4] = {0};
 608     unsigned i;
 609     union util_color uc = {0};
 610
 611     desc = util_format_description(format);
 612
 613     /* Do depth formats first. */
 614     if (util_format_is_depth_or_stencil(format)) {
 615         switch (format) {
 616         case PIPE_FORMAT_Z16_UNORM:
 617             return util_pack_z(PIPE_FORMAT_Z16_UNORM, border[0]);
 618         case PIPE_FORMAT_X8Z24_UNORM:
 619         case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 620             if (is_r500) {
 621                 return util_pack_z(PIPE_FORMAT_X8Z24_UNORM, border[0]);
 622             } else {
 623                 return util_pack_z(PIPE_FORMAT_Z16_UNORM, border[0]) << 16;
 624             }
 625         default:
 626             assert(0);
 627             return 0;
 628         }
 629     }
 630
 631     /* Apply inverse swizzle of the format. */
 632     for (i = 0; i < 4; i++) {
 633         switch (desc->swizzle[i]) {
 634         case UTIL_FORMAT_SWIZZLE_X:
 635             border_swizzled[0] = border[i];
 636             break;
 637         case UTIL_FORMAT_SWIZZLE_Y:
 638             border_swizzled[1] = border[i];
 639             break;
 640         case UTIL_FORMAT_SWIZZLE_Z:
 641             border_swizzled[2] = border[i];
 642             break;
 643         case UTIL_FORMAT_SWIZZLE_W:
 644             border_swizzled[3] = border[i];
 645             break;
 646         }
 647     }
 648
 649     /* Compressed formats. */
 650     if (util_format_is_compressed(format)) {
 651         switch (format) {
 652         case PIPE_FORMAT_RGTC1_SNORM:
 653         case PIPE_FORMAT_LATC1_SNORM:
 654             border_swizzled[0] = border_swizzled[0] < 0 ?
 655                                  border_swizzled[0]*0.5+1 :
 656                                  border_swizzled[0]*0.5;
 657             /* Pass through. */
 658
 659         case PIPE_FORMAT_RGTC1_UNORM:
 660         case PIPE_FORMAT_LATC1_UNORM:
 661             /* Add 1/32 to round the border color instead of truncating. */
 662             /* The Y component is used for the border color. */
 663             border_swizzled[1] = border_swizzled[0] + 1.0f/32;
 664             util_pack_color(border_swizzled, PIPE_FORMAT_B4G4R4A4_UNORM, &uc);
 665             return uc.ui;
 666         case PIPE_FORMAT_RGTC2_SNORM:
 667         case PIPE_FORMAT_LATC2_SNORM:
 668             util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_SNORM, &uc);
 669             return uc.ui;
 670         case PIPE_FORMAT_RGTC2_UNORM:
 671         case PIPE_FORMAT_LATC2_UNORM:
 672             util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
 673             return uc.ui;
 674         default:
 675             util_pack_color(border_swizzled, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
 676             return uc.ui;
 677         }
 678     }
 679
 680     switch (desc->channel[0].size) {
 681         case 2:
 682             rgba_to_bgra(border_swizzled);
 683             util_pack_color(border_swizzled, PIPE_FORMAT_B2G3R3_UNORM, &uc);
 684             break;
 685
 686         case 4:
 687             rgba_to_bgra(border_swizzled);
 688             util_pack_color(border_swizzled, PIPE_FORMAT_B4G4R4A4_UNORM, &uc);
 689             break;
 690
 691         case 5:
 692             rgba_to_bgra(border_swizzled);
 693             if (desc->channel[1].size == 5) {
 694                 util_pack_color(border_swizzled, PIPE_FORMAT_B5G5R5A1_UNORM, &uc);
 695             } else if (desc->channel[1].size == 6) {
 696                 util_pack_color(border_swizzled, PIPE_FORMAT_B5G6R5_UNORM, &uc);
 697             } else {
 698                 assert(0);
 699             }
 700             break;
 701
 702         default:
 703         case 8:
 704             if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED)
 705                util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_SNORM, &uc);
 706             else
 707                util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
 708             break;
 709
 710         case 10:
 711             util_pack_color(border_swizzled, PIPE_FORMAT_R10G10B10A2_UNORM, &uc);
 712             break;
 713
 714         case 16:
 715             if (desc->nr_channels <= 2) {
 716                 if (desc->channel[0].type == UTIL_FORMAT_TYPE_FLOAT) {
 717                     util_pack_color(border_swizzled, PIPE_FORMAT_R16G16_FLOAT, &uc);
 718                 } else if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
 719                     util_pack_color(border_swizzled, PIPE_FORMAT_R16G16_SNORM, &uc);
 720                 } else {
 721                     util_pack_color(border_swizzled, PIPE_FORMAT_R16G16_UNORM, &uc);
 722                 }
 723             } else {
 724                 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
 725                     util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_SNORM, &uc);
 726                 } else {
 727                     util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
 728                 }
 729             }
 730             break;
 731
 732         case 32:
 733             if (desc->nr_channels == 1) {
 734                 util_pack_color(border_swizzled, PIPE_FORMAT_R32_FLOAT, &uc);
 735             } else {
 736                 util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
 737             }
 738             break;
 739     }
 740
 741     return uc.ui;
 742 }
 743
 744 static void r300_merge_textures_and_samplers(struct r300_context* r300)
 745 {
 746     struct r300_textures_state *state =
 747         (struct r300_textures_state*)r300->textures_state.state;
 748     struct r300_texture_sampler_state *texstate;
 749     struct r300_sampler_state *sampler;
 750     struct r300_sampler_view *view;
 751     struct r300_resource *tex;
 752     unsigned base_level, min_level, level_count, i, j, size;
 753     unsigned count = MIN2(state->sampler_view_count,
 754                           state->sampler_state_count);
 755     boolean has_us_format = r300->screen->caps.has_us_format;
 756
 757     /* The KIL opcode fix, see below. */
 758     if (!count && !r300->screen->caps.is_r500)
 759         count = 1;
 760
 761     state->tx_enable = 0;
 762     state->count = 0;
 763     size = 2;
 764
 765     for (i = 0; i < count; i++) {
 766         if (state->sampler_views[i] && state->sampler_states[i]) {
 767             state->tx_enable |= 1 << i;
 768
 769             view = state->sampler_views[i];
 770             tex = r300_resource(view->base.texture);
 771             sampler = state->sampler_states[i];
 772
 773             texstate = &state->regs[i];
 774             texstate->format = view->format;
 775             texstate->filter0 = sampler->filter0;
 776             texstate->filter1 = sampler->filter1;
 777
 778             /* Set the border color. */
 779             texstate->border_color =
 780                 r300_get_border_color(view->base.format,
 781                                       sampler->state.border_color,
 782                                       r300->screen->caps.is_r500);
 783
 784             /* determine min/max levels */
 785             base_level = view->base.u.tex.first_level;
 786             min_level = sampler->min_lod;
 787             level_count = MIN3(sampler->max_lod,
 788                                tex->b.b.b.last_level - base_level,
 789                                view->base.u.tex.last_level - base_level);
 790
 791             if (base_level + min_level) {
 792                 unsigned offset;
 793
 794                 if (tex->tex.is_npot) {
 795                     /* Even though we do not implement mipmapping for NPOT
 796                      * textures, we should at least honor the minimum level
 797                      * which is allowed to be displayed. We do this by setting up
 798                      * an i-th mipmap level as the zero level. */
 799                     base_level += min_level;
 800                 }
 801                 offset = tex->tex_offset +
 802                          tex->tex.offset_in_bytes[base_level];
 803
 804                 r300_texture_setup_format_state(r300->screen, tex,
 805                                                 base_level,
 806                                                 &texstate->format);
 807                 texstate->format.tile_config |= offset & 0xffffffe0;
 808                 assert((offset & 0x1f) == 0);
 809             } else {
 810                 texstate->format.tile_config |= tex->tex_offset & 0xffffffe0;
 811                 assert((tex->tex_offset & 0x1f) == 0);
 812             }
 813
 814             /* Assign a texture cache region. */
 815             texstate->format.format1 |= view->texcache_region;
 816
 817             /* Depth textures are kinda special. */
 818             if (util_format_is_depth_or_stencil(tex->b.b.b.format)) {
 819                 unsigned char depth_swizzle[4];
 820
 821                 if (!r300->screen->caps.is_r500 &&
 822                     util_format_get_blocksizebits(tex->b.b.b.format) == 32) {
 823                     /* X24x8 is sampled as Y16X16 on r3xx-r4xx.
 824                      * The depth here is at the Y component. */
 825                     for (j = 0; j < 4; j++)
 826                         depth_swizzle[j] = UTIL_FORMAT_SWIZZLE_Y;
 827                 } else {
 828                     for (j = 0; j < 4; j++)
 829                         depth_swizzle[j] = UTIL_FORMAT_SWIZZLE_X;
 830                 }
 831
 832                 /* If compare mode is disabled, sampler view swizzles
 833                  * are stored in the format.
 834                  * Otherwise, the swizzles must be applied after the compare
 835                  * mode in the fragment shader. */
 836                 if (sampler->state.compare_mode == PIPE_TEX_COMPARE_NONE) {
 837                     texstate->format.format1 |=
 838                         r300_get_swizzle_combined(depth_swizzle,
 839                                                   view->swizzle, FALSE);
 840                 } else {
 841                     texstate->format.format1 |=
 842                         r300_get_swizzle_combined(depth_swizzle, 0, FALSE);
 843                 }
 844             }
 845
 846             if (r300->screen->caps.dxtc_swizzle &&
 847                 util_format_is_compressed(tex->b.b.b.format)) {
 848                 texstate->filter1 |= R400_DXTC_SWIZZLE_ENABLE;
 849             }
 850
 851             /* to emulate 1D textures through 2D ones correctly */
 852             if (tex->b.b.b.target == PIPE_TEXTURE_1D) {
 853                 texstate->filter0 &= ~R300_TX_WRAP_T_MASK;
 854                 texstate->filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
 855             }
 856
 857             /* The hardware doesn't like CLAMP and CLAMP_TO_BORDER
 858              * for the 3rd coordinate if the texture isn't 3D. */
 859             if (tex->b.b.b.target != PIPE_TEXTURE_3D) {
 860                 texstate->filter0 &= ~R300_TX_WRAP_R_MASK;
 861             }
 862
 863             if (tex->tex.is_npot) {
 864                 /* NPOT textures don't support mip filter, unfortunately.
 865                  * This prevents incorrect rendering. */
 866                 texstate->filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK;
 867
 868                 /* Mask out the mirrored flag. */
 869                 if (texstate->filter0 & R300_TX_WRAP_S(R300_TX_MIRRORED)) {
 870                     texstate->filter0 &= ~R300_TX_WRAP_S(R300_TX_MIRRORED);
 871                 }
 872                 if (texstate->filter0 & R300_TX_WRAP_T(R300_TX_MIRRORED)) {
 873                     texstate->filter0 &= ~R300_TX_WRAP_T(R300_TX_MIRRORED);
 874                 }
 875
 876                 /* Change repeat to clamp-to-edge.
 877                  * (the repeat bit has a value of 0, no masking needed). */
 878                 if ((texstate->filter0 & R300_TX_WRAP_S_MASK) ==
 879                     R300_TX_WRAP_S(R300_TX_REPEAT)) {
 880                     texstate->filter0 |= R300_TX_WRAP_S(R300_TX_CLAMP_TO_EDGE);
 881                 }
 882                 if ((texstate->filter0 & R300_TX_WRAP_T_MASK) ==
 883                     R300_TX_WRAP_T(R300_TX_REPEAT)) {
 884                     texstate->filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
 885                 }
 886             } else {
 887                 /* the MAX_MIP level is the largest (finest) one */
 888                 texstate->format.format0 |= R300_TX_NUM_LEVELS(level_count);
 889                 texstate->filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
 890             }
 891
 892             /* Float textures only support nearest and mip-nearest filtering. */
 893             if (util_format_is_float(tex->b.b.b.format)) {
 894                 /* No MAG linear filtering. */
 895                 if ((texstate->filter0 & R300_TX_MAG_FILTER_MASK) ==
 896                     R300_TX_MAG_FILTER_LINEAR) {
 897                     texstate->filter0 &= ~R300_TX_MAG_FILTER_MASK;
 898                     texstate->filter0 |= R300_TX_MAG_FILTER_NEAREST;
 899                 }
 900                 /* No MIN linear filtering. */
 901                 if ((texstate->filter0 & R300_TX_MIN_FILTER_MASK) ==
 902                     R300_TX_MIN_FILTER_LINEAR) {
 903                     texstate->filter0 &= ~R300_TX_MIN_FILTER_MASK;
 904                     texstate->filter0 |= R300_TX_MIN_FILTER_NEAREST;
 905                 }
 906                 /* No mipmap linear filtering. */
 907                 if ((texstate->filter0 & R300_TX_MIN_FILTER_MIP_MASK) ==
 908                     R300_TX_MIN_FILTER_MIP_LINEAR) {
 909                     texstate->filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK;
 910                     texstate->filter0 |= R300_TX_MIN_FILTER_MIP_NEAREST;
 911                 }
 912                 /* No anisotropic filtering. */
 913                 texstate->filter0 &= ~R300_TX_MAX_ANISO_MASK;
 914                 texstate->filter1 &= ~R500_TX_MAX_ANISO_MASK;
 915                 texstate->filter1 &= ~R500_TX_ANISO_HIGH_QUALITY;
 916             }
 917
 918             texstate->filter0 |= i << 28;
 919
 920             size += 16 + (has_us_format ? 2 : 0);
 921             state->count = i+1;
 922         } else {
 923             /* For the KIL opcode to work on r3xx-r4xx, the texture unit
 924              * assigned to this opcode (it's always the first one) must be
 925              * enabled. Otherwise the opcode doesn't work.
 926              *
 927              * In order to not depend on the fragment shader, we just make
 928              * the first unit enabled all the time. */
 929             if (i == 0 && !r300->screen->caps.is_r500) {
 930                 pipe_sampler_view_reference(
 931                         (struct pipe_sampler_view**)&state->sampler_views[i],
 932                         &r300->texkill_sampler->base);
 933
 934                 state->tx_enable |= 1 << i;
 935
 936                 texstate = &state->regs[i];
 937
 938                 /* Just set some valid state. */
 939                 texstate->format = r300->texkill_sampler->format;
 940                 texstate->filter0 =
 941                         r300_translate_tex_filters(PIPE_TEX_FILTER_NEAREST,
 942                                                    PIPE_TEX_FILTER_NEAREST,
 943                                                    PIPE_TEX_FILTER_NEAREST,
 944                                                    FALSE);
 945                 texstate->filter1 = 0;
 946                 texstate->border_color = 0;
 947
 948                 texstate->filter0 |= i << 28;
 949                 size += 16 + (has_us_format ? 2 : 0);
 950                 state->count = i+1;
 951             }
 952         }
 953     }
 954
 955     r300->textures_state.size = size;
 956
 957     /* Pick a fragment shader based on either the texture compare state
 958      * or the uses_pitch flag or some other external state. */
 959     if (count &&
 960         r300->fs_status == FRAGMENT_SHADER_VALID) {
 961         r300->fs_status = FRAGMENT_SHADER_MAYBE_DIRTY;
 962     }
 963 }
 964
 965 static void r300_decompress_depth_textures(struct r300_context *r300)
 966 {
 967     struct r300_textures_state *state =
 968         (struct r300_textures_state*)r300->textures_state.state;
 969     struct pipe_resource *tex;
 970     unsigned count = MIN2(state->sampler_view_count,
 971                           state->sampler_state_count);
 972     unsigned i;
 973
 974     if (!r300->locked_zbuffer) {
 975         return;
 976     }
 977
 978     for (i = 0; i < count; i++) {
 979         if (state->sampler_views[i] && state->sampler_states[i]) {
 980             tex = state->sampler_views[i]->base.texture;
 981
 982             if (tex == r300->locked_zbuffer->texture) {
 983                 r300_decompress_zmask_locked(r300);
 984                 return;
 985             }
 986         }
 987     }
 988 }
 989
 990 static void r300_validate_fragment_shader(struct r300_context *r300)
 991 {
 992     struct pipe_framebuffer_state *fb = r300->fb_state.state;
 993
 994     if (r300->fs.state && r300->fs_status != FRAGMENT_SHADER_VALID) {
 995         /* Pick the fragment shader based on external states.
 996          * Then mark the state dirty if the fragment shader is either dirty
 997          * or the function r300_pick_fragment_shader changed the shader. */
 998         if (r300_pick_fragment_shader(r300) ||
 999             r300->fs_status == FRAGMENT_SHADER_DIRTY) {
1000             /* Mark the state atom as dirty. */
1001             r300_mark_fs_code_dirty(r300);
1002
1003             /* Does Multiwrite need to be changed? */
1004             if (fb->nr_cbufs > 1) {
1005                 boolean new_multiwrite =
1006                     r300_fragment_shader_writes_all(r300_fs(r300));
1007
1008                 if (r300->fb_multiwrite != new_multiwrite) {
1009                     r300->fb_multiwrite = new_multiwrite;
1010                     r300_mark_fb_state_dirty(r300, R300_CHANGED_MULTIWRITE);
1011                 }
1012             }
1013         }
1014         r300->fs_status = FRAGMENT_SHADER_VALID;
1015     }
1016 }
1017
1018 void r300_update_derived_state(struct r300_context* r300)
1019 {
1020     if (r300->textures_state.dirty) {
1021         r300_decompress_depth_textures(r300);
1022         r300_merge_textures_and_samplers(r300);
1023     }
1024
1025     r300_validate_fragment_shader(r300);
1026
1027     if (r300->rs_block_state.dirty) {
1028         r300_update_rs_block(r300);
1029
1030         if (r300->draw) {
1031             memset(&r300->vertex_info, 0, sizeof(struct vertex_info));
1032             r300_draw_emit_all_attribs(r300);
1033             draw_compute_vertex_size(&r300->vertex_info);
1034             r300_swtcl_vertex_psc(r300);
1035         }
1036     }
1037
1038     r300_update_hyperz_state(r300);
1039 }