src/gallium/drivers/r300/r300_screen.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #include "compiler/nir/nir.h"
  25 #include "util/format/u_format.h"
  26 #include "util/format/u_format_s3tc.h"
  27 #include "util/u_screen.h"
  28 #include "util/u_memory.h"
  29 #include "util/hex.h"
  30 #include "util/os_time.h"
  31 #include "vl/vl_decoder.h"
  32 #include "vl/vl_video_buffer.h"
  33
  34 #include "r300_context.h"
  35 #include "r300_texture.h"
  36 #include "r300_screen_buffer.h"
  37 #include "r300_state_inlines.h"
  38 #include "r300_public.h"
  39 #include "compiler/r300_nir.h"
  40
  41 #include "draw/draw_context.h"
  42
  43 /* Return the identifier behind whom the brave coders responsible for this
  44  * amalgamation of code, sweat, and duct tape, routinely obscure their names.
  45  *
  46  * ...I should have just put "Corbin Simpson", but I'm not that cool.
  47  *
  48  * (Or egotistical. Yet.) */
  49 static const char* r300_get_vendor(struct pipe_screen* pscreen)
  50 {
  51     return "Mesa";
  52 }
  53
  54 static const char* r300_get_device_vendor(struct pipe_screen* pscreen)
  55 {
  56     return "ATI";
  57 }
  58
  59 static const char* chip_families[] = {
  60     "unknown",
  61     "ATI R300",
  62     "ATI R350",
  63     "ATI RV350",
  64     "ATI RV370",
  65     "ATI RV380",
  66     "ATI RS400",
  67     "ATI RC410",
  68     "ATI RS480",
  69     "ATI R420",
  70     "ATI R423",
  71     "ATI R430",
  72     "ATI R480",
  73     "ATI R481",
  74     "ATI RV410",
  75     "ATI RS600",
  76     "ATI RS690",
  77     "ATI RS740",
  78     "ATI RV515",
  79     "ATI R520",
  80     "ATI RV530",
  81     "ATI R580",
  82     "ATI RV560",
  83     "ATI RV570"
  84 };
  85
  86 static const char* r300_get_family_name(struct r300_screen* r300screen)
  87 {
  88     return chip_families[r300screen->caps.family];
  89 }
  90
  91 static const char* r300_get_name(struct pipe_screen* pscreen)
  92 {
  93     struct r300_screen* r300screen = r300_screen(pscreen);
  94
  95     return r300_get_family_name(r300screen);
  96 }
  97
  98 static void r300_disk_cache_create(struct r300_screen* r300screen)
  99 {
 100     struct mesa_sha1 ctx;
 101     unsigned char sha1[20];
 102     char cache_id[20 * 2 + 1];
 103
 104     _mesa_sha1_init(&ctx);
 105     if (!disk_cache_get_function_identifier(r300_disk_cache_create,
 106                                             &ctx))
 107         return;
 108
 109     _mesa_sha1_final(&ctx, sha1);
 110     mesa_bytes_to_hex(cache_id, sha1, 20);
 111
 112     r300screen->disk_shader_cache =
 113                     disk_cache_create(r300_get_family_name(r300screen),
 114                                       cache_id,
 115                                       r300screen->debug);
 116 }
 117
 118 static struct disk_cache* r300_get_disk_shader_cache(struct pipe_screen* pscreen)
 119 {
 120         struct r300_screen* r300screen = r300_screen(pscreen);
 121         return r300screen->disk_shader_cache;
 122 }
 123
 124 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 125 {
 126     struct r300_screen* r300screen = r300_screen(pscreen);
 127     bool is_r500 = r300screen->caps.is_r500;
 128
 129     switch (param) {
 130         /* Supported features (boolean caps). */
 131         case PIPE_CAP_NPOT_TEXTURES:
 132         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 133         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 134         case PIPE_CAP_ANISOTROPIC_FILTER:
 135         case PIPE_CAP_OCCLUSION_QUERY:
 136         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 137         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 138         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 139         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 140         case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
 141         case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 142         case PIPE_CAP_CONDITIONAL_RENDER:
 143         case PIPE_CAP_TEXTURE_BARRIER:
 144         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 145         case PIPE_CAP_CLIP_HALFZ:
 146         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 147         case PIPE_CAP_LEGACY_MATH_RULES:
 148         case PIPE_CAP_TGSI_TEXCOORD:
 149             return 1;
 150
 151         case PIPE_CAP_TEXTURE_TRANSFER_MODES:
 152             return PIPE_TEXTURE_TRANSFER_BLIT;
 153
 154         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 155             return R300_BUFFER_ALIGNMENT;
 156
 157         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 158             return 16;
 159
 160         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 161         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 162             return 120;
 163
 164         /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
 165         case PIPE_CAP_TEXTURE_SWIZZLE:
 166             return r300screen->caps.dxtc_swizzle;
 167
 168         /* We don't support color clamping on r500, so that we can use color
 169          * interpolators for generic varyings. */
 170         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 171             return !is_r500;
 172
 173         /* Supported on r500 only. */
 174         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 175         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 176         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 177         case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 178             return is_r500 ? 1 : 0;
 179
 180         case PIPE_CAP_SHAREABLE_SHADERS:
 181             return 0;
 182
 183         case PIPE_CAP_MAX_GS_INVOCATIONS:
 184             return 32;
 185        case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
 186             return 1 << 27;
 187
 188         /* SWTCL-only features. */
 189         case PIPE_CAP_PRIMITIVE_RESTART:
 190         case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
 191         case PIPE_CAP_USER_VERTEX_BUFFERS:
 192         case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
 193             return !r300screen->caps.has_tcl;
 194
 195         /* HWTCL-only features / limitations. */
 196         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 197         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 198         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 199             return r300screen->caps.has_tcl;
 200
 201         /* Texturing. */
 202         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 203             return is_r500 ? 4096 : 2048;
 204         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 205         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 206             /* 13 == 4096, 12 == 2048 */
 207             return is_r500 ? 13 : 12;
 208
 209         /* Render targets. */
 210         case PIPE_CAP_MAX_RENDER_TARGETS:
 211             return 4;
 212         case PIPE_CAP_ENDIANNESS:
 213             return PIPE_ENDIAN_LITTLE;
 214
 215         case PIPE_CAP_MAX_VIEWPORTS:
 216             return 1;
 217
 218         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 219             return 2048;
 220
 221         case PIPE_CAP_MAX_VARYINGS:
 222             return 10;
 223
 224         case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 225             return 0;
 226
 227         case PIPE_CAP_VENDOR_ID:
 228                 return 0x1002;
 229         case PIPE_CAP_DEVICE_ID:
 230                 return r300screen->info.pci_id;
 231         case PIPE_CAP_ACCELERATED:
 232                 return 1;
 233         case PIPE_CAP_VIDEO_MEMORY:
 234                 return r300screen->info.vram_size_kb >> 10;
 235         case PIPE_CAP_UMA:
 236                 return 0;
 237         case PIPE_CAP_PCI_GROUP:
 238             return r300screen->info.pci.domain;
 239         case PIPE_CAP_PCI_BUS:
 240             return r300screen->info.pci.bus;
 241         case PIPE_CAP_PCI_DEVICE:
 242             return r300screen->info.pci.dev;
 243         case PIPE_CAP_PCI_FUNCTION:
 244             return r300screen->info.pci.func;
 245         default:
 246             return u_pipe_screen_get_param_defaults(pscreen, param);
 247     }
 248 }
 249
 250 static int r300_get_shader_param(struct pipe_screen *pscreen,
 251                                  enum pipe_shader_type shader,
 252                                  enum pipe_shader_cap param)
 253 {
 254    struct r300_screen* r300screen = r300_screen(pscreen);
 255    bool is_r400 = r300screen->caps.is_r400;
 256    bool is_r500 = r300screen->caps.is_r500;
 257
 258    switch (param) {
 259     case PIPE_SHADER_CAP_SUPPORTED_IRS:
 260         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 261     default:
 262         break;
 263     }
 264
 265    switch (shader) {
 266     case PIPE_SHADER_FRAGMENT:
 267         switch (param)
 268         {
 269         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 270             return is_r500 || is_r400 ? 512 : 96;
 271         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 272             return is_r500 || is_r400 ? 512 : 64;
 273         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 274             return is_r500 || is_r400 ? 512 : 32;
 275         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 276             return is_r500 ? 511 : 4;
 277         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 278             return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
 279             /* Fragment shader limits. */
 280         case PIPE_SHADER_CAP_MAX_INPUTS:
 281             /* 2 colors + 8 texcoords are always supported
 282              * (minus fog and wpos).
 283              *
 284              * R500 has the ability to turn 3rd and 4th color into
 285              * additional texcoords but there is no two-sided color
 286              * selection then. However the facing bit can be used instead. */
 287             return 10;
 288         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 289             return 4;
 290         case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
 291             return (is_r500 ? 256 : 32) * sizeof(float[4]);
 292         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 293         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 294             return 1;
 295         case PIPE_SHADER_CAP_MAX_TEMPS:
 296             return is_r500 ? 128 : is_r400 ? 64 : 32;
 297         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 298         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 299            return r300screen->caps.num_tex_units;
 300         case PIPE_SHADER_CAP_CONT_SUPPORTED:
 301         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 302         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 303         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 304         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 305         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 306         case PIPE_SHADER_CAP_SUBROUTINES:
 307         case PIPE_SHADER_CAP_INTEGERS:
 308         case PIPE_SHADER_CAP_INT64_ATOMICS:
 309         case PIPE_SHADER_CAP_FP16:
 310         case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 311         case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
 312         case PIPE_SHADER_CAP_INT16:
 313         case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
 314         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 315         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 316         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 317         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 318             return 0;
 319         default:
 320             break;
 321         }
 322         break;
 323     case PIPE_SHADER_VERTEX:
 324         switch (param)
 325         {
 326         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 327         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 328         case PIPE_SHADER_CAP_SUBROUTINES:
 329             return 0;
 330         default:;
 331         }
 332
 333         if (!r300screen->caps.has_tcl) {
 334             switch (param) {
 335             case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 336             case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 337                 return 0;
 338
 339             /* mesa/st requires that this cap is the same across stages, and the FS
 340              * can't do ints.
 341              */
 342             case PIPE_SHADER_CAP_INTEGERS:
 343                 return 0;
 344
 345             /* Even if gallivm NIR can do this, we call nir_to_tgsi manually and
 346              * TGSI can't.
 347              */
 348             case PIPE_SHADER_CAP_INT16:
 349             case PIPE_SHADER_CAP_FP16:
 350             case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 351             case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
 352                 return 0;
 353
 354             /* While draw could normally handle this for the VS, the NIR lowering
 355              * to regs can't handle our non-native-integers, so we have to lower to
 356              * if ladders.
 357              */
 358             case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 359                 return 0;
 360             default:
 361                 return draw_get_shader_param(shader, param);
 362             }
 363         }
 364
 365         switch (param)
 366         {
 367         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 368         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 369             return is_r500 ? 1024 : 256;
 370         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 371             return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
 372         case PIPE_SHADER_CAP_MAX_INPUTS:
 373             return 16;
 374         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 375             return 10;
 376         case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
 377             return 256 * sizeof(float[4]);
 378         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 379             return 1;
 380         case PIPE_SHADER_CAP_MAX_TEMPS:
 381             return 32;
 382         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 383         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 384             return 1;
 385         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 386         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 387         case PIPE_SHADER_CAP_CONT_SUPPORTED:
 388         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 389         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 390         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 391         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 392         case PIPE_SHADER_CAP_SUBROUTINES:
 393         case PIPE_SHADER_CAP_INTEGERS:
 394         case PIPE_SHADER_CAP_FP16:
 395         case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
 396         case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 397         case PIPE_SHADER_CAP_INT16:
 398         case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
 399         case PIPE_SHADER_CAP_INT64_ATOMICS:
 400         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 401         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 402         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 403         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 404         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 405         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 406             return 0;
 407         default:
 408             break;
 409         }
 410         break;
 411     default:
 412         ; /* nothing */
 413     }
 414     return 0;
 415 }
 416
 417 static float r300_get_paramf(struct pipe_screen* pscreen,
 418                              enum pipe_capf param)
 419 {
 420     struct r300_screen* r300screen = r300_screen(pscreen);
 421
 422     switch (param) {
 423         case PIPE_CAPF_MIN_LINE_WIDTH:
 424         case PIPE_CAPF_MIN_LINE_WIDTH_AA:
 425         case PIPE_CAPF_MIN_POINT_SIZE:
 426         case PIPE_CAPF_MIN_POINT_SIZE_AA:
 427             return 1;
 428         case PIPE_CAPF_POINT_SIZE_GRANULARITY:
 429         case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
 430             return 0.1;
 431         case PIPE_CAPF_MAX_LINE_WIDTH:
 432         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 433         case PIPE_CAPF_MAX_POINT_SIZE:
 434         case PIPE_CAPF_MAX_POINT_SIZE_AA:
 435             /* The maximum dimensions of the colorbuffer are our practical
 436              * rendering limits. 2048 pixels should be enough for anybody. */
 437             if (r300screen->caps.is_r500) {
 438                 return 4096.0f;
 439             } else if (r300screen->caps.is_r400) {
 440                 return 4021.0f;
 441             } else {
 442                 return 2560.0f;
 443             }
 444         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 445             return 16.0f;
 446         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 447             return 16.0f;
 448         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 449         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 450         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 451             return 0.0f;
 452         default:
 453             debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
 454                          param);
 455             return 0.0f;
 456     }
 457 }
 458
 459 static int r300_get_video_param(struct pipe_screen *screen,
 460                                 enum pipe_video_profile profile,
 461                                 enum pipe_video_entrypoint entrypoint,
 462                                 enum pipe_video_cap param)
 463 {
 464    switch (param) {
 465       case PIPE_VIDEO_CAP_SUPPORTED:
 466          return vl_profile_supported(screen, profile, entrypoint);
 467       case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 468          return 0;
 469       case PIPE_VIDEO_CAP_MAX_WIDTH:
 470       case PIPE_VIDEO_CAP_MAX_HEIGHT:
 471          return vl_video_buffer_max_size(screen);
 472       case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 473          return PIPE_FORMAT_NV12;
 474       case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 475          return false;
 476       case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 477          return false;
 478       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 479          return true;
 480       case PIPE_VIDEO_CAP_MAX_LEVEL:
 481          return vl_level_supported(screen, profile);
 482       default:
 483          return 0;
 484    }
 485 }
 486
 487 #define COMMON_NIR_OPTIONS                    \
 488    .fdot_replicates = true,                   \
 489    .fuse_ffma32 = true,                       \
 490    .fuse_ffma64 = true,                       \
 491    .lower_bitops = true,                      \
 492    .lower_extract_byte = true,                \
 493    .lower_extract_word = true,                \
 494    .lower_fceil = true,                       \
 495    .lower_fdiv = true,                        \
 496    .lower_fdph = true,                        \
 497    .lower_ffloor = true,                      \
 498    .lower_flrp32 = true,                      \
 499    .lower_flrp64 = true,                      \
 500    .lower_fmod = true,                        \
 501    .lower_fsign = true,                       \
 502    .lower_fsqrt = true,                       \
 503    .lower_ftrunc = true,                      \
 504    .lower_insert_byte = true,                 \
 505    .lower_insert_word = true,                 \
 506    .lower_rotate = true,                      \
 507    .lower_uniforms_to_ubo = true,             \
 508    .lower_vector_cmp = true,                  \
 509    .no_integers = true,                       \
 510    .use_interpolated_input_intrinsics = true
 511
 512 static const nir_shader_compiler_options r500_vs_compiler_options = {
 513    COMMON_NIR_OPTIONS,
 514    .has_fused_comp_and_csel = true,
 515
 516    /* Have HW loops support and 1024 max instr count, but don't unroll *too*
 517     * hard.
 518     */
 519    .max_unroll_iterations = 29,
 520 };
 521
 522 static const nir_shader_compiler_options r500_fs_compiler_options = {
 523    COMMON_NIR_OPTIONS,
 524    .lower_fpow = true, /* POW is only in the VS */
 525    .has_fused_comp_and_csel = true,
 526
 527    /* Have HW loops support and 512 max instr count, but don't unroll *too*
 528     * hard.
 529     */
 530    .max_unroll_iterations = 32,
 531 };
 532
 533 static const nir_shader_compiler_options r300_vs_compiler_options = {
 534    COMMON_NIR_OPTIONS,
 535    .lower_fsat = true, /* No fsat in pre-r500 VS */
 536    .lower_sincos = true,
 537
 538    /* Note: has HW loops support, but only 256 ALU instructions. */
 539    .max_unroll_iterations = 32,
 540 };
 541
 542 static const nir_shader_compiler_options r300_fs_compiler_options = {
 543    COMMON_NIR_OPTIONS,
 544    .lower_fpow = true, /* POW is only in the VS */
 545    .lower_sincos = true,
 546    .has_fused_comp_and_csel = true,
 547
 548     /* No HW loops support, so set it equal to ALU instr max */
 549    .max_unroll_iterations = 64,
 550 };
 551
 552 static const void *
 553 r300_get_compiler_options(struct pipe_screen *pscreen,
 554                           enum pipe_shader_ir ir,
 555                           enum pipe_shader_type shader)
 556 {
 557    struct r300_screen* r300screen = r300_screen(pscreen);
 558
 559    assert(ir == PIPE_SHADER_IR_NIR);
 560
 561    if (r300screen->caps.is_r500) {
 562       if (shader == PIPE_SHADER_VERTEX)
 563          return &r500_vs_compiler_options;
 564        else
 565          return &r500_fs_compiler_options;
 566    } else {
 567       if (shader == PIPE_SHADER_VERTEX)
 568          return &r300_vs_compiler_options;
 569        else
 570          return &r300_fs_compiler_options;
 571    }
 572 }
 573
 574 /**
 575  * Whether the format matches:
 576  *   PIPE_FORMAT_?10?10?10?2_UNORM
 577  */
 578 static inline bool
 579 util_format_is_rgba1010102_variant(const struct util_format_description *desc)
 580 {
 581    static const unsigned size[4] = {10, 10, 10, 2};
 582    unsigned chan;
 583
 584    if (desc->block.width != 1 ||
 585        desc->block.height != 1 ||
 586        desc->block.bits != 32)
 587       return false;
 588
 589    for (chan = 0; chan < 4; ++chan) {
 590       if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
 591          desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
 592          return false;
 593       if (desc->channel[chan].size != size[chan])
 594          return false;
 595    }
 596
 597    return true;
 598 }
 599
 600 static bool r300_is_blending_supported(struct r300_screen *rscreen,
 601                                        enum pipe_format format)
 602 {
 603     int c;
 604     const struct util_format_description *desc =
 605         util_format_description(format);
 606
 607     if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
 608         return false;
 609
 610     c = util_format_get_first_non_void_channel(format);
 611
 612     /* RGBA16F */
 613     if (rscreen->caps.is_r500 &&
 614         desc->nr_channels == 4 &&
 615         desc->channel[c].size == 16 &&
 616         desc->channel[c].type == UTIL_FORMAT_TYPE_FLOAT)
 617         return true;
 618
 619     if (desc->channel[c].normalized &&
 620         desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED &&
 621         desc->channel[c].size >= 4 &&
 622         desc->channel[c].size <= 10) {
 623         /* RGB10_A2, RGBA8, RGB5_A1, RGBA4, RGB565 */
 624         if (desc->nr_channels >= 3)
 625             return true;
 626
 627         if (format == PIPE_FORMAT_R8G8_UNORM)
 628             return true;
 629
 630         /* R8, I8, L8, A8 */
 631         if (desc->nr_channels == 1)
 632             return true;
 633     }
 634
 635     return false;
 636 }
 637
 638 static bool r300_is_format_supported(struct pipe_screen* screen,
 639                                      enum pipe_format format,
 640                                      enum pipe_texture_target target,
 641                                      unsigned sample_count,
 642                                      unsigned storage_sample_count,
 643                                      unsigned usage)
 644 {
 645     uint32_t retval = 0;
 646     bool is_r500 = r300_screen(screen)->caps.is_r500;
 647     bool is_r400 = r300_screen(screen)->caps.is_r400;
 648     bool is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
 649                            format == PIPE_FORMAT_R10G10B10X2_SNORM ||
 650                            format == PIPE_FORMAT_B10G10R10A2_UNORM ||
 651                            format == PIPE_FORMAT_B10G10R10X2_UNORM ||
 652                            format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
 653     bool is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
 654                     format == PIPE_FORMAT_RGTC1_SNORM ||
 655                     format == PIPE_FORMAT_LATC1_UNORM ||
 656                     format == PIPE_FORMAT_LATC1_SNORM;
 657     bool is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
 658                     format == PIPE_FORMAT_RGTC2_SNORM ||
 659                     format == PIPE_FORMAT_LATC2_UNORM ||
 660                     format == PIPE_FORMAT_LATC2_SNORM;
 661     bool is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
 662                          format == PIPE_FORMAT_R16G16_FLOAT ||
 663                          format == PIPE_FORMAT_R16G16B16_FLOAT ||
 664                          format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
 665                          format == PIPE_FORMAT_R16G16B16X16_FLOAT;
 666     const struct util_format_description *desc;
 667
 668     if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 669         return false;
 670
 671     /* Check multisampling support. */
 672     switch (sample_count) {
 673         case 0:
 674         case 1:
 675             break;
 676         case 2:
 677         case 4:
 678         case 6:
 679             /* No texturing and scanout. */
 680             if (usage & (PIPE_BIND_SAMPLER_VIEW |
 681                          PIPE_BIND_DISPLAY_TARGET |
 682                          PIPE_BIND_SCANOUT)) {
 683                 return false;
 684             }
 685
 686             desc = util_format_description(format);
 687
 688             if (is_r500) {
 689                 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
 690                 if (!util_format_is_depth_or_stencil(format) &&
 691                     !util_format_is_rgba8_variant(desc) &&
 692                     !util_format_is_rgba1010102_variant(desc) &&
 693                     format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
 694                     format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
 695                     return false;
 696                 }
 697             } else {
 698                 /* Only allow depth/stencil, RGBA8. */
 699                 if (!util_format_is_depth_or_stencil(format) &&
 700                     !util_format_is_rgba8_variant(desc)) {
 701                     return false;
 702                 }
 703             }
 704             break;
 705         default:
 706             return false;
 707     }
 708
 709     /* Check sampler format support. */
 710     if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 711         /* these two are broken for an unknown reason */
 712         format != PIPE_FORMAT_R8G8B8X8_SNORM &&
 713         format != PIPE_FORMAT_R16G16B16X16_SNORM &&
 714         /* ATI1N is r5xx-only. */
 715         (is_r500 || !is_ati1n) &&
 716         /* ATI2N is supported on r4xx-r5xx. */
 717         (is_r400 || is_r500 || !is_ati2n) &&
 718         r300_is_sampler_format_supported(format)) {
 719         retval |= PIPE_BIND_SAMPLER_VIEW;
 720     }
 721
 722     /* Check colorbuffer format support. */
 723     if ((usage & (PIPE_BIND_RENDER_TARGET |
 724                   PIPE_BIND_DISPLAY_TARGET |
 725                   PIPE_BIND_SCANOUT |
 726                   PIPE_BIND_SHARED |
 727                   PIPE_BIND_BLENDABLE)) &&
 728         /* 2101010 cannot be rendered to on non-r5xx. */
 729         (!is_color2101010 || is_r500) &&
 730         r300_is_colorbuffer_format_supported(format)) {
 731         retval |= usage &
 732             (PIPE_BIND_RENDER_TARGET |
 733              PIPE_BIND_DISPLAY_TARGET |
 734              PIPE_BIND_SCANOUT |
 735              PIPE_BIND_SHARED);
 736
 737         if (r300_is_blending_supported(r300_screen(screen), format)) {
 738             retval |= usage & PIPE_BIND_BLENDABLE;
 739         }
 740     }
 741
 742     /* Check depth-stencil format support. */
 743     if (usage & PIPE_BIND_DEPTH_STENCIL &&
 744         r300_is_zs_format_supported(format)) {
 745         retval |= PIPE_BIND_DEPTH_STENCIL;
 746     }
 747
 748     /* Check vertex buffer format support. */
 749     if (usage & PIPE_BIND_VERTEX_BUFFER) {
 750         if (r300_screen(screen)->caps.has_tcl) {
 751             /* Half float is supported on >= R400. */
 752             if ((is_r400 || is_r500 || !is_half_float) &&
 753                 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
 754                 retval |= PIPE_BIND_VERTEX_BUFFER;
 755             }
 756         } else {
 757             /* SW TCL */
 758             if (!util_format_is_pure_integer(format)) {
 759                 retval |= PIPE_BIND_VERTEX_BUFFER;
 760             }
 761         }
 762     }
 763
 764     if (usage & PIPE_BIND_INDEX_BUFFER) {
 765        if (format == PIPE_FORMAT_R8_UINT ||
 766            format == PIPE_FORMAT_R16_UINT ||
 767            format == PIPE_FORMAT_R32_UINT)
 768           retval |= PIPE_BIND_INDEX_BUFFER;
 769     }
 770
 771     return retval == usage;
 772 }
 773
 774 static void r300_destroy_screen(struct pipe_screen* pscreen)
 775 {
 776     struct r300_screen* r300screen = r300_screen(pscreen);
 777     struct radeon_winsys *rws = radeon_winsys(pscreen);
 778
 779     if (rws && !rws->unref(rws))
 780       return;
 781
 782     mtx_destroy(&r300screen->cmask_mutex);
 783     slab_destroy_parent(&r300screen->pool_transfers);
 784
 785     disk_cache_destroy(r300screen->disk_shader_cache);
 786
 787     if (rws)
 788       rws->destroy(rws);
 789
 790     FREE(r300screen);
 791 }
 792
 793 static void r300_fence_reference(struct pipe_screen *screen,
 794                                  struct pipe_fence_handle **ptr,
 795                                  struct pipe_fence_handle *fence)
 796 {
 797     struct radeon_winsys *rws = r300_screen(screen)->rws;
 798
 799     rws->fence_reference(ptr, fence);
 800 }
 801
 802 static bool r300_fence_finish(struct pipe_screen *screen,
 803                               struct pipe_context *ctx,
 804                               struct pipe_fence_handle *fence,
 805                               uint64_t timeout)
 806 {
 807     struct radeon_winsys *rws = r300_screen(screen)->rws;
 808
 809     return rws->fence_wait(rws, fence, timeout);
 810 }
 811
 812 static int r300_screen_get_fd(struct pipe_screen *screen)
 813 {
 814     struct radeon_winsys *rws = r300_screen(screen)->rws;
 815
 816     return rws->get_fd(rws);
 817 }
 818
 819 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws,
 820                                        const struct pipe_screen_config *config)
 821 {
 822     struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
 823
 824     if (!r300screen) {
 825         FREE(r300screen);
 826         return NULL;
 827     }
 828
 829     rws->query_info(rws, &r300screen->info);
 830
 831     r300_init_debug(r300screen);
 832     r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
 833
 834     if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
 835         r300screen->caps.zmask_ram = 0;
 836     if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
 837         r300screen->caps.hiz_ram = 0;
 838     if (SCREEN_DBG_ON(r300screen, DBG_NO_TCL))
 839         r300screen->caps.has_tcl = false;
 840
 841     r300screen->rws = rws;
 842     r300screen->screen.destroy = r300_destroy_screen;
 843     r300screen->screen.get_name = r300_get_name;
 844     r300screen->screen.get_vendor = r300_get_vendor;
 845     r300screen->screen.get_compiler_options = r300_get_compiler_options;
 846     r300screen->screen.finalize_nir = r300_finalize_nir;
 847     r300screen->screen.get_device_vendor = r300_get_device_vendor;
 848     r300screen->screen.get_disk_shader_cache = r300_get_disk_shader_cache;
 849     r300screen->screen.get_screen_fd = r300_screen_get_fd;
 850     r300screen->screen.get_param = r300_get_param;
 851     r300screen->screen.get_shader_param = r300_get_shader_param;
 852     r300screen->screen.get_paramf = r300_get_paramf;
 853     r300screen->screen.get_video_param = r300_get_video_param;
 854     r300screen->screen.is_format_supported = r300_is_format_supported;
 855     r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 856     r300screen->screen.context_create = r300_create_context;
 857     r300screen->screen.fence_reference = r300_fence_reference;
 858     r300screen->screen.fence_finish = r300_fence_finish;
 859
 860     r300_init_screen_resource_functions(r300screen);
 861
 862     r300_disk_cache_create(r300screen);
 863
 864     slab_create_parent(&r300screen->pool_transfers, sizeof(struct pipe_transfer), 64);
 865
 866     (void) mtx_init(&r300screen->cmask_mutex, mtx_plain);
 867
 868     return &r300screen->screen;
 869 }