2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29 #include "util/u_simple_list.h"
31 #include "r300_context.h"
33 #include "r300_emit.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
39 void r300_emit_blend_state(struct r300_context* r300,
40 unsigned size, void* state)
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 struct pipe_framebuffer_state* fb =
44 (struct pipe_framebuffer_state*)r300->fb_state.state;
48 WRITE_CS_TABLE(blend->cb, size);
50 WRITE_CS_TABLE(blend->cb_no_readwrite, size);
54 void r300_emit_blend_color_state(struct r300_context* r300,
55 unsigned size, void* state)
57 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
60 WRITE_CS_TABLE(bc->cb, size);
63 void r300_emit_clip_state(struct r300_context* r300,
64 unsigned size, void* state)
66 struct r300_clip_state* clip = (struct r300_clip_state*)state;
69 WRITE_CS_TABLE(clip->cb, size);
72 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
74 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
75 struct pipe_framebuffer_state* fb =
76 (struct pipe_framebuffer_state*)r300->fb_state.state;
80 WRITE_CS_TABLE(&dsa->cb_begin, size);
82 WRITE_CS_TABLE(dsa->cb_no_readwrite, size);
86 static void get_rc_constant_state(
88 struct r300_context * r300,
89 struct rc_constant * constant)
91 struct r300_textures_state* texstate = r300->textures_state.state;
92 struct r300_texture *tex;
94 assert(constant->Type == RC_CONSTANT_STATE);
96 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
97 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
100 switch (constant->u.State[0]) {
101 /* Factor for converting rectangle coords to
102 * normalized coords. Should only show up on non-r500. */
103 case RC_STATE_R300_TEXRECT_FACTOR:
104 tex = r300_texture(texstate->sampler_views[constant->u.State[1]]->base.texture);
105 vec[0] = 1.0 / tex->desc.width0;
106 vec[1] = 1.0 / tex->desc.height0;
111 case RC_STATE_R300_TEXSCALE_FACTOR:
112 tex = r300_texture(texstate->sampler_views[constant->u.State[1]]->base.texture);
113 /* Add a small number to the texture size to work around rounding errors in hw. */
114 vec[0] = tex->desc.b.b.width0 / (tex->desc.width0 + 0.001f);
115 vec[1] = tex->desc.b.b.height0 / (tex->desc.height0 + 0.001f);
116 vec[2] = tex->desc.b.b.depth0 / (tex->desc.depth0 + 0.001f);
120 case RC_STATE_R300_VIEWPORT_SCALE:
121 vec[0] = r300->viewport.scale[0];
122 vec[1] = r300->viewport.scale[1];
123 vec[2] = r300->viewport.scale[2];
127 case RC_STATE_R300_VIEWPORT_OFFSET:
128 vec[0] = r300->viewport.translate[0];
129 vec[1] = r300->viewport.translate[1];
130 vec[2] = r300->viewport.translate[2];
135 fprintf(stderr, "r300: Implementation error: "
136 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
144 /* Convert a normal single-precision float into the 7.16 format
145 * used by the R300 fragment shader.
147 uint32_t pack_float24(float f)
155 uint32_t float24 = 0;
162 mantissa = frexpf(f, &exponent);
166 float24 |= (1 << 23);
167 mantissa = mantissa * -1.0;
169 /* Handle exponent, bias of 63 */
171 float24 |= (exponent << 16);
172 /* Kill 7 LSB of mantissa */
173 float24 |= (u.u & 0x7FFFFF) >> 7;
178 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
180 struct r300_fragment_shader *fs = r300_fs(r300);
183 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
186 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
188 struct r300_fragment_shader *fs = r300_fs(r300);
189 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
190 unsigned count = fs->shader->externals_count;
198 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
199 if (buf->remap_table){
200 for (i = 0; i < count; i++) {
201 float *data = (float*)&buf->ptr[buf->remap_table[i]*4];
202 for (j = 0; j < 4; j++)
203 OUT_CS(pack_float24(data[j]));
206 for (i = 0; i < count; i++)
207 for (j = 0; j < 4; j++)
208 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
214 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
216 struct r300_fragment_shader *fs = r300_fs(r300);
217 struct rc_constant_list *constants = &fs->shader->code.constants;
219 unsigned count = fs->shader->rc_state_count;
220 unsigned first = fs->shader->externals_count;
221 unsigned end = constants->Count;
229 for(i = first; i < end; ++i) {
230 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
233 get_rc_constant_state(data, r300, &constants->Constants[i]);
235 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
236 for (j = 0; j < 4; j++)
237 OUT_CS(pack_float24(data[j]));
243 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
245 struct r300_fragment_shader *fs = r300_fs(r300);
248 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
251 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
253 struct r300_fragment_shader *fs = r300_fs(r300);
254 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
255 unsigned count = fs->shader->externals_count;
262 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
263 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
264 if (buf->remap_table){
265 for (unsigned i = 0; i < count; i++) {
266 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
267 OUT_CS_TABLE(data, 4);
270 OUT_CS_TABLE(buf->ptr, count * 4);
275 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
277 struct r300_fragment_shader *fs = r300_fs(r300);
278 struct rc_constant_list *constants = &fs->shader->code.constants;
280 unsigned count = fs->shader->rc_state_count;
281 unsigned first = fs->shader->externals_count;
282 unsigned end = constants->Count;
289 for(i = first; i < end; ++i) {
290 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
293 get_rc_constant_state(data, r300, &constants->Constants[i]);
295 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
296 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
297 (i & R500_GA_US_VECTOR_INDEX_MASK));
298 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
299 OUT_CS_TABLE(data, 4);
305 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
307 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
308 struct pipe_framebuffer_state* fb =
309 (struct pipe_framebuffer_state*)r300->fb_state.state;
310 uint32_t height = fb->height;
311 uint32_t width = fb->width;
314 if (r300->cbzb_clear) {
315 struct r300_surface *surf = r300_surface(fb->cbufs[0]);
317 height = surf->cbzb_height;
318 width = surf->cbzb_width;
321 DBG(r300, DBG_SCISSOR,
322 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
323 width, height, r300->cbzb_clear ? "YES" : "NO");
328 * By writing to the SC registers, SC & US assert idle. */
329 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
330 if (r300->screen->caps.is_r500) {
332 OUT_CS(((width - 1) << R300_SCISSORS_X_SHIFT) |
333 ((height - 1) << R300_SCISSORS_Y_SHIFT));
335 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
336 (1440 << R300_SCISSORS_Y_SHIFT));
337 OUT_CS(((width + 1440-1) << R300_SCISSORS_X_SHIFT) |
338 ((height + 1440-1) << R300_SCISSORS_Y_SHIFT));
341 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
342 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
346 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
348 struct r300_aa_state *aa = (struct r300_aa_state*)state;
352 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
355 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 1);
356 OUT_CS_RELOC(aa->dest->cs_buffer, aa->dest->offset, 0, aa->dest->domain);
358 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_PITCH, 1);
359 OUT_CS_RELOC(aa->dest->cs_buffer, aa->dest->pitch, 0, aa->dest->domain);
362 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, aa->aaresolve_ctl);
366 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
368 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
369 struct r300_surface* surf;
371 boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
376 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
377 * what we usually want. */
378 if (r300->screen->caps.is_r500) {
379 OUT_CS_REG(R300_RB3D_CCTL,
380 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
382 OUT_CS_REG(R300_RB3D_CCTL, 0);
385 /* Set up colorbuffers. */
386 for (i = 0; i < fb->nr_cbufs; i++) {
387 surf = r300_surface(fb->cbufs[i]);
389 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
390 OUT_CS_RELOC(surf->cs_buffer, surf->offset, 0, surf->domain);
392 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
393 OUT_CS_RELOC(surf->cs_buffer, surf->pitch, 0, surf->domain);
396 /* Set up the ZB part of the CBZB clear. */
397 if (r300->cbzb_clear) {
398 surf = r300_surface(fb->cbufs[0]);
400 OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format);
402 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
403 OUT_CS_RELOC(surf->cs_buffer, surf->cbzb_midpoint_offset, 0, surf->domain);
405 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
406 OUT_CS_RELOC(surf->cs_buffer, surf->cbzb_pitch, 0, surf->domain);
409 "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format,
412 /* Set up a zbuffer. */
413 else if (fb->zsbuf) {
414 surf = r300_surface(fb->zsbuf);
416 OUT_CS_REG(R300_ZB_FORMAT, surf->format);
418 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
419 OUT_CS_RELOC(surf->cs_buffer, surf->offset, 0, surf->domain);
421 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
422 OUT_CS_RELOC(surf->cs_buffer, surf->pitch, 0, surf->domain);
426 struct r300_texture *tex;
427 int level = surf->base.u.tex.level;
428 tex = r300_texture(surf->base.texture);
430 surf_pitch = surf->pitch & R300_DEPTHPITCH_MASK;
432 if (r300->screen->caps.hiz_ram) {
433 if (tex->hiz_mem[level]) {
434 OUT_CS_REG(R300_ZB_HIZ_OFFSET, tex->hiz_mem[level]->ofs << 2);
435 OUT_CS_REG(R300_ZB_HIZ_PITCH, surf_pitch);
437 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
438 OUT_CS_REG(R300_ZB_HIZ_PITCH, 0);
441 /* Z Mask RAM. (compressed zbuffer) */
442 if (tex->zmask_mem[level]) {
443 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, tex->zmask_mem[level]->ofs << 2);
444 OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf_pitch);
446 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
447 OUT_CS_REG(R300_ZB_ZMASK_PITCH, 0);
455 void r300_emit_hyperz_state(struct r300_context *r300,
456 unsigned size, void *state)
458 struct r300_hyperz_state *z = state;
461 WRITE_CS_TABLE(&z->cb_flush_begin, size);
463 WRITE_CS_TABLE(&z->cb_begin, size - 2);
466 void r300_emit_hyperz_end(struct r300_context *r300)
468 struct r300_hyperz_state z =
469 *(struct r300_hyperz_state*)r300->hyperz_state.state;
473 z.zb_depthclearvalue = 0;
474 z.sc_hyperz = R300_SC_HYPERZ_ADJ_2;
475 z.gb_z_peq_config = 0;
477 r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z);
480 void r300_emit_fb_state_pipelined(struct r300_context *r300,
481 unsigned size, void *state)
483 struct pipe_framebuffer_state* fb =
484 (struct pipe_framebuffer_state*)r300->fb_state.state;
490 /* Colorbuffer format in the US block.
491 * (must be written after unpipelined regs) */
492 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
493 for (i = 0; i < fb->nr_cbufs; i++) {
494 OUT_CS(r300_surface(fb->cbufs[i])->format);
497 OUT_CS(R300_US_OUT_FMT_UNUSED);
500 /* Multisampling. Depends on framebuffer sample count.
501 * These are pipelined regs and as such cannot be moved
502 * to the AA state. */
503 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
504 unsigned mspos0 = 0x66666666;
505 unsigned mspos1 = 0x6666666;
507 if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) {
508 /* Subsample placement. These may not be optimal. */
509 switch (fb->cbufs[0]->texture->nr_samples) {
527 debug_printf("r300: Bad number of multisamples!\n");
531 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
538 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
540 struct r300_query *query = r300->query_current;
547 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
548 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
550 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
552 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
554 query->begin_emitted = TRUE;
555 query->flushed = FALSE;
558 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
559 struct r300_query *query)
561 struct r300_capabilities* caps = &r300->screen->caps;
562 struct r300_winsys_cs_buffer *buf = r300->query_current->cs_buffer;
565 assert(caps->num_frag_pipes);
567 BEGIN_CS(6 * caps->num_frag_pipes + 2);
568 /* I'm not so sure I like this switch, but it's hard to be elegant
569 * when there's so many special cases...
571 * So here's the basic idea. For each pipe, enable writes to it only,
572 * then put out the relocation for ZPASS_ADDR, taking into account a
573 * 4-byte offset for each pipe. RV380 and older are special; they have
574 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
575 * so there's a chipset cap for that. */
576 switch (caps->num_frag_pipes) {
579 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
580 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
581 OUT_CS_RELOC(buf, (query->num_results + 3) * 4,
585 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
586 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
587 OUT_CS_RELOC(buf, (query->num_results + 2) * 4,
591 /* As mentioned above, accomodate RV380 and older. */
592 OUT_CS_REG(R300_SU_REG_DEST,
593 1 << (caps->high_second_pipe ? 3 : 1));
594 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
595 OUT_CS_RELOC(buf, (query->num_results + 1) * 4,
599 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
600 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
601 OUT_CS_RELOC(buf, (query->num_results + 0) * 4,
605 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
606 " pixel pipes!\n", caps->num_frag_pipes);
610 /* And, finally, reset it to normal... */
611 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
615 static void rv530_emit_query_end_single_z(struct r300_context *r300,
616 struct r300_query *query)
618 struct r300_winsys_cs_buffer *buf = r300->query_current->cs_buffer;
622 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
623 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
624 OUT_CS_RELOC(buf, query->num_results * 4, 0, query->domain);
625 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
629 static void rv530_emit_query_end_double_z(struct r300_context *r300,
630 struct r300_query *query)
632 struct r300_winsys_cs_buffer *buf = r300->query_current->cs_buffer;
636 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
637 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
638 OUT_CS_RELOC(buf, (query->num_results + 0) * 4, 0, query->domain);
639 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
640 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
641 OUT_CS_RELOC(buf, (query->num_results + 1) * 4, 0, query->domain);
642 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
646 void r300_emit_query_end(struct r300_context* r300)
648 struct r300_capabilities *caps = &r300->screen->caps;
649 struct r300_query *query = r300->query_current;
654 if (query->begin_emitted == FALSE)
657 if (caps->family == CHIP_FAMILY_RV530) {
658 if (caps->num_z_pipes == 2)
659 rv530_emit_query_end_double_z(r300, query);
661 rv530_emit_query_end_single_z(r300, query);
663 r300_emit_query_end_frag_pipes(r300, query);
665 query->begin_emitted = FALSE;
666 query->num_results += query->num_pipes;
668 /* XXX grab all the results and reset the counter. */
669 if (query->num_results >= query->buffer_size / 4 - 4) {
670 query->num_results = (query->buffer_size / 4) / 2;
671 fprintf(stderr, "r300: Rewinding OQBO...\n");
675 void r300_emit_invariant_state(struct r300_context *r300,
676 unsigned size, void *state)
679 WRITE_CS_TABLE(state, size);
682 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
684 struct r300_rs_state* rs = state;
688 OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE);
689 if (rs->polygon_offset_enable) {
690 if (r300->zbuffer_bpp == 16) {
691 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
693 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
699 void r300_emit_rs_block_state(struct r300_context* r300,
700 unsigned size, void* state)
702 struct r300_rs_block* rs = (struct r300_rs_block*)state;
704 /* It's the same for both INST and IP tables */
705 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
708 if (DBG_ON(r300, DBG_RS_BLOCK)) {
709 r500_dump_rs_block(rs);
711 fprintf(stderr, "r300: RS emit:\n");
713 for (i = 0; i < count; i++)
714 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]);
716 for (i = 0; i < count; i++)
717 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]);
719 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n",
720 rs->count, rs->inst_count);
724 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
725 OUT_CS(rs->vap_vtx_state_cntl);
726 OUT_CS(rs->vap_vsm_vtx_assm);
727 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
728 OUT_CS(rs->vap_out_vtx_fmt[0]);
729 OUT_CS(rs->vap_out_vtx_fmt[1]);
730 OUT_CS_REG_SEQ(R300_GB_ENABLE, 1);
731 OUT_CS(rs->gb_enable);
733 if (r300->screen->caps.is_r500) {
734 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
736 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
738 OUT_CS_TABLE(rs->ip, count);
740 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
742 OUT_CS(rs->inst_count);
744 if (r300->screen->caps.is_r500) {
745 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
747 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
749 OUT_CS_TABLE(rs->inst, count);
753 void r300_emit_scissor_state(struct r300_context* r300,
754 unsigned size, void* state)
756 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
760 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
761 if (r300->screen->caps.is_r500) {
762 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
763 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
764 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
765 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
767 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
768 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
769 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
770 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
775 void r300_emit_textures_state(struct r300_context *r300,
776 unsigned size, void *state)
778 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
779 struct r300_texture_sampler_state *texstate;
780 struct r300_texture *tex;
785 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
787 for (i = 0; i < allstate->count; i++) {
788 if ((1 << i) & allstate->tx_enable) {
789 texstate = &allstate->regs[i];
790 tex = r300_texture(allstate->sampler_views[i]->base.texture);
792 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
793 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
794 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
795 texstate->border_color);
797 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
798 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
799 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
801 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
802 OUT_CS_TEX_RELOC(tex, texstate->format.tile_config, tex->domain,
809 void r300_emit_aos(struct r300_context* r300, int offset, boolean indexed)
811 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
812 struct pipe_vertex_element *velem = r300->velems->velem;
813 struct r300_buffer *buf;
815 unsigned *hw_format_size = r300->velems->hw_format_size;
816 unsigned size1, size2, aos_count = r300->velems->count;
817 unsigned packet_size = (aos_count * 3 + 1) / 2;
820 BEGIN_CS(2 + packet_size + aos_count * 2);
821 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
822 OUT_CS(aos_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
824 for (i = 0; i < aos_count - 1; i += 2) {
825 vb1 = &vbuf[velem[i].vertex_buffer_index];
826 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
827 size1 = hw_format_size[i];
828 size2 = hw_format_size[i+1];
830 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
831 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
832 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
833 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
837 vb1 = &vbuf[velem[i].vertex_buffer_index];
838 size1 = hw_format_size[i];
840 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
841 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
844 for (i = 0; i < aos_count; i++) {
845 buf = r300_buffer(vbuf[velem[i].vertex_buffer_index].buffer);
846 OUT_CS_BUF_RELOC_NO_OFFSET(&buf->b.b, buf->domain, 0);
851 void r300_emit_aos_swtcl(struct r300_context *r300, boolean indexed)
855 DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, "
856 "vertex size %d\n", r300->vbo,
857 r300->vertex_info.size);
858 /* Set the pointer to our vertex buffer. The emitted values are this:
859 * PACKET3 [3D_LOAD_VBPNTR]
861 * FORMAT [size | stride << 8]
862 * OFFSET [offset into BO]
863 * VBPNTR [relocated BO]
866 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
867 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
868 OUT_CS(r300->vertex_info.size |
869 (r300->vertex_info.size << 8));
870 OUT_CS(r300->draw_vbo_offset);
871 OUT_CS_BUF_RELOC(r300->vbo, 0, r300_buffer(r300->vbo)->domain, 0);
875 void r300_emit_vertex_stream_state(struct r300_context* r300,
876 unsigned size, void* state)
878 struct r300_vertex_stream_state *streams =
879 (struct r300_vertex_stream_state*)state;
883 if (DBG_ON(r300, DBG_PSC)) {
884 fprintf(stderr, "r300: PSC emit:\n");
886 for (i = 0; i < streams->count; i++) {
887 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i,
888 streams->vap_prog_stream_cntl[i]);
891 for (i = 0; i < streams->count; i++) {
892 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
893 streams->vap_prog_stream_cntl_ext[i]);
898 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
899 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
900 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
901 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
905 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
910 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
914 void r300_emit_vap_invariant_state(struct r300_context *r300,
915 unsigned size, void *state)
918 WRITE_CS_TABLE(state, size);
921 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
923 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
924 struct r300_vertex_program_code* code = &vs->code;
925 struct r300_screen* r300screen = r300->screen;
926 unsigned instruction_count = code->length / 4;
928 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
929 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
930 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
931 unsigned temp_count = MAX2(code->num_temporaries, 1);
933 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
934 vtx_mem_size / output_count, 10);
935 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5);
941 /* R300_VAP_PVS_CODE_CNTL_0
942 * R300_VAP_PVS_CONST_CNTL
943 * R300_VAP_PVS_CODE_CNTL_1
944 * See the r5xx docs for instructions on how to use these. */
945 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) |
946 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
947 R300_PVS_LAST_INST(instruction_count - 1));
948 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, instruction_count - 1);
950 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
951 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
952 OUT_CS_TABLE(code->body.d, code->length);
954 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
955 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
956 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
957 R300_PVS_VF_MAX_VTX_NUM(12) |
958 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
960 /* Emit flow control instructions. */
961 if (code->num_fc_ops) {
963 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
964 if (r300screen->caps.is_r500) {
965 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, code->num_fc_ops * 2);
966 OUT_CS_TABLE(code->fc_op_addrs.r500, code->num_fc_ops * 2);
968 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, code->num_fc_ops);
969 OUT_CS_TABLE(code->fc_op_addrs.r300, code->num_fc_ops);
971 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, code->num_fc_ops);
972 OUT_CS_TABLE(code->fc_loop_index, code->num_fc_ops);
978 void r300_emit_vs_constants(struct r300_context* r300,
979 unsigned size, void *state)
982 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
983 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
984 struct r300_vertex_shader *vs = (struct r300_vertex_shader*)r300->vs_state.state;
986 int imm_first = vs->externals_count;
987 int imm_end = vs->code.constants.Count;
988 int imm_count = vs->immediates_count;
992 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL,
993 R300_PVS_CONST_BASE_OFFSET(buf->buffer_base) |
994 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end - 1, 0)));
995 if (vs->externals_count) {
996 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
997 (r300->screen->caps.is_r500 ?
998 R500_PVS_CONST_START : R300_PVS_CONST_START) + buf->buffer_base);
999 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1000 if (buf->remap_table){
1001 for (i = 0; i < count; i++) {
1002 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
1003 OUT_CS_TABLE(data, 4);
1006 OUT_CS_TABLE(buf->ptr, count * 4);
1010 /* Emit immediates. */
1012 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1013 (r300->screen->caps.is_r500 ?
1014 R500_PVS_CONST_START : R300_PVS_CONST_START) +
1015 buf->buffer_base + imm_first);
1016 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
1017 for (i = imm_first; i < imm_end; i++) {
1018 const float *data = vs->code.constants.Constants[i].u.Immediate;
1019 OUT_CS_TABLE(data, 4);
1025 void r300_emit_viewport_state(struct r300_context* r300,
1026 unsigned size, void* state)
1028 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1032 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1033 OUT_CS_TABLE(&viewport->xscale, 6);
1034 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1038 static void r300_emit_hiz_line_clear(struct r300_context *r300, int start, uint16_t count, uint32_t val)
1042 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2);
1049 static void r300_emit_zmask_line_clear(struct r300_context *r300, int start, uint16_t count, uint32_t val)
1053 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2);
1060 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1062 void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state)
1064 struct pipe_framebuffer_state *fb =
1065 (struct pipe_framebuffer_state*)r300->fb_state.state;
1066 struct r300_hyperz_state *z =
1067 (struct r300_hyperz_state*)r300->hyperz_state.state;
1068 struct r300_screen* r300screen = r300->screen;
1069 uint32_t stride, offset = 0, height, offset_shift;
1070 struct r300_texture* tex;
1073 tex = r300_texture(fb->zsbuf->texture);
1075 offset = tex->hiz_mem[fb->zsbuf->u.tex.level]->ofs;
1076 stride = tex->desc.stride_in_pixels[fb->zsbuf->u.tex.level];
1078 /* convert from pixels to 4x4 blocks */
1079 stride = ALIGN_DIVUP(stride, 4);
1081 stride = ALIGN_DIVUP(stride, r300screen->caps.num_frag_pipes);
1082 /* there are 4 blocks per dwords */
1083 stride = ALIGN_DIVUP(stride, 4);
1085 height = ALIGN_DIVUP(fb->zsbuf->height, 4);
1088 offset_shift += (r300screen->caps.num_frag_pipes / 2);
1090 for (i = 0; i < height; i++) {
1091 offset = i * stride;
1092 offset <<= offset_shift;
1093 r300_emit_hiz_line_clear(r300, offset, stride, 0xffffffff);
1095 z->current_func = -1;
1097 /* Mark the current zbuffer's hiz ram as in use. */
1098 tex->hiz_in_use[fb->zsbuf->u.tex.level] = TRUE;
1101 void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state)
1103 struct pipe_framebuffer_state *fb =
1104 (struct pipe_framebuffer_state*)r300->fb_state.state;
1105 struct r300_screen* r300screen = r300->screen;
1106 uint32_t stride, offset = 0;
1107 struct r300_texture* tex;
1109 int mult, offset_shift;
1111 tex = r300_texture(fb->zsbuf->texture);
1112 stride = tex->desc.stride_in_pixels[fb->zsbuf->u.tex.level];
1114 offset = tex->zmask_mem[fb->zsbuf->u.tex.level]->ofs;
1116 if (r300->z_compression == RV350_Z_COMPRESS_88)
1121 height = ALIGN_DIVUP(fb->zsbuf->height, mult);
1124 offset_shift += (r300screen->caps.num_frag_pipes / 2);
1125 stride = ALIGN_DIVUP(stride, r300screen->caps.num_frag_pipes);
1127 /* okay have width in pixels - divide by block width */
1128 stride = ALIGN_DIVUP(stride, mult);
1129 /* have width in blocks - divide by number of fragment pipes screen width */
1130 /* 16 blocks per dword */
1131 stride = ALIGN_DIVUP(stride, 16);
1133 for (i = 0; i < height; i++) {
1134 offset = i * stride;
1135 offset <<= offset_shift;
1136 r300_emit_zmask_line_clear(r300, offset, stride, 0x0);//0xffffffff);
1139 /* Mark the current zbuffer's zmask as in use. */
1140 tex->zmask_in_use[fb->zsbuf->u.tex.level] = TRUE;
1143 void r300_emit_ztop_state(struct r300_context* r300,
1144 unsigned size, void* state)
1146 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1150 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1154 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1159 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1163 boolean r300_emit_buffer_validate(struct r300_context *r300,
1164 boolean do_validate_vertex_buffers,
1165 struct pipe_resource *index_buffer)
1167 struct pipe_framebuffer_state* fb =
1168 (struct pipe_framebuffer_state*)r300->fb_state.state;
1169 struct r300_textures_state *texstate =
1170 (struct r300_textures_state*)r300->textures_state.state;
1171 struct r300_texture* tex;
1172 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1173 struct pipe_vertex_element *velem = r300->velems->velem;
1174 struct pipe_resource *pbuf;
1177 /* upload buffers first */
1178 if (r300->screen->caps.has_tcl && r300->any_user_vbs) {
1179 r300_upload_user_buffers(r300);
1180 r300->any_user_vbs = false;
1183 /* Clean out BOs. */
1184 r300->rws->cs_reset_buffers(r300->cs);
1186 /* Color buffers... */
1187 for (i = 0; i < fb->nr_cbufs; i++) {
1188 tex = r300_texture(fb->cbufs[i]->texture);
1189 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1190 r300->rws->cs_add_buffer(r300->cs, tex->cs_buffer, 0,
1191 r300_surface(fb->cbufs[i])->domain);
1193 /* ...depth buffer... */
1195 tex = r300_texture(fb->zsbuf->texture);
1196 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1197 r300->rws->cs_add_buffer(r300->cs, tex->cs_buffer, 0,
1198 r300_surface(fb->zsbuf)->domain);
1200 /* ...textures... */
1201 for (i = 0; i < texstate->count; i++) {
1202 if (!(texstate->tx_enable & (1 << i))) {
1206 tex = r300_texture(texstate->sampler_views[i]->base.texture);
1207 r300->rws->cs_add_buffer(r300->cs, tex->cs_buffer, tex->domain, 0);
1209 /* ...occlusion query buffer... */
1210 if (r300->query_current)
1211 r300->rws->cs_add_buffer(r300->cs, r300->query_current->cs_buffer,
1212 0, r300->query_current->domain);
1213 /* ...vertex buffer for SWTCL path... */
1215 r300->rws->cs_add_buffer(r300->cs, r300_buffer(r300->vbo)->cs_buf,
1216 r300_buffer(r300->vbo)->domain, 0);
1217 /* ...vertex buffers for HWTCL path... */
1218 if (do_validate_vertex_buffers) {
1219 for (i = 0; i < r300->velems->count; i++) {
1220 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1222 r300->rws->cs_add_buffer(r300->cs, r300_buffer(pbuf)->cs_buf,
1223 r300_buffer(pbuf)->domain, 0);
1226 /* ...and index buffer for HWTCL path. */
1228 r300->rws->cs_add_buffer(r300->cs, r300_buffer(index_buffer)->cs_buf,
1229 r300_buffer(index_buffer)->domain, 0);
1231 if (!r300->rws->cs_validate(r300->cs)) {
1238 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1240 struct r300_atom* atom;
1241 unsigned dwords = 0;
1243 foreach(atom, &r300->atom_list) {
1245 dwords += atom->size;
1249 /* let's reserve some more, just in case */
1255 unsigned r300_get_num_cs_end_dwords(struct r300_context *r300)
1257 unsigned dwords = 0;
1259 /* Emitted in flush. */
1260 dwords += 26; /* emit_query_end */
1261 dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
1262 if (r300->screen->caps.index_bias_supported)
1268 /* Emit all dirty state. */
1269 void r300_emit_dirty_state(struct r300_context* r300)
1271 struct r300_atom* atom;
1273 foreach(atom, &r300->atom_list) {
1275 atom->emit(r300, atom->size, atom->state);
1276 if (SCREEN_DBG_ON(r300->screen, DBG_STATS)) {
1279 atom->dirty = FALSE;