2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
30 #include "r300_context.h"
33 #include "r300_emit.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
39 void r300_emit_blend_state(struct r300_context* r300,
40 unsigned size, void* state)
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 struct pipe_framebuffer_state* fb =
44 (struct pipe_framebuffer_state*)r300->fb_state.state;
48 if (fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT)
49 WRITE_CS_TABLE(blend->cb_noclamp, size);
51 WRITE_CS_TABLE(blend->cb_clamp, size);
53 WRITE_CS_TABLE(blend->cb_no_readwrite, size);
57 void r300_emit_blend_color_state(struct r300_context* r300,
58 unsigned size, void* state)
60 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
63 WRITE_CS_TABLE(bc->cb, size);
66 void r300_emit_clip_state(struct r300_context* r300,
67 unsigned size, void* state)
69 struct r300_clip_state* clip = (struct r300_clip_state*)state;
72 WRITE_CS_TABLE(clip->cb, size);
75 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
77 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
78 struct pipe_framebuffer_state* fb =
79 (struct pipe_framebuffer_state*)r300->fb_state.state;
83 if (fb->nr_cbufs && fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT)
84 WRITE_CS_TABLE(&dsa->cb_begin_fp16, size);
86 WRITE_CS_TABLE(&dsa->cb_begin, size);
88 if (fb->nr_cbufs && fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT)
89 WRITE_CS_TABLE(dsa->cb_fp16_zb_no_readwrite, size);
91 WRITE_CS_TABLE(dsa->cb_zb_no_readwrite, size);
95 static void get_rc_constant_state(
97 struct r300_context * r300,
98 struct rc_constant * constant)
100 struct r300_textures_state* texstate = r300->textures_state.state;
101 struct r300_resource *tex;
103 assert(constant->Type == RC_CONSTANT_STATE);
105 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
106 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
109 switch (constant->u.State[0]) {
110 /* Factor for converting rectangle coords to
111 * normalized coords. Should only show up on non-r500. */
112 case RC_STATE_R300_TEXRECT_FACTOR:
113 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
114 vec[0] = 1.0 / tex->tex.width0;
115 vec[1] = 1.0 / tex->tex.height0;
120 case RC_STATE_R300_TEXSCALE_FACTOR:
121 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
122 /* Add a small number to the texture size to work around rounding errors in hw. */
123 vec[0] = tex->b.b.width0 / (tex->tex.width0 + 0.001f);
124 vec[1] = tex->b.b.height0 / (tex->tex.height0 + 0.001f);
125 vec[2] = tex->b.b.depth0 / (tex->tex.depth0 + 0.001f);
129 case RC_STATE_R300_VIEWPORT_SCALE:
130 vec[0] = r300->viewport.scale[0];
131 vec[1] = r300->viewport.scale[1];
132 vec[2] = r300->viewport.scale[2];
136 case RC_STATE_R300_VIEWPORT_OFFSET:
137 vec[0] = r300->viewport.translate[0];
138 vec[1] = r300->viewport.translate[1];
139 vec[2] = r300->viewport.translate[2];
144 fprintf(stderr, "r300: Implementation error: "
145 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
153 /* Convert a normal single-precision float into the 7.16 format
154 * used by the R300 fragment shader.
156 uint32_t pack_float24(float f)
164 uint32_t float24 = 0;
171 mantissa = frexpf(f, &exponent);
175 float24 |= (1 << 23);
176 mantissa = mantissa * -1.0;
178 /* Handle exponent, bias of 63 */
180 float24 |= (exponent << 16);
181 /* Kill 7 LSB of mantissa */
182 float24 |= (u.u & 0x7FFFFF) >> 7;
187 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
189 struct r300_fragment_shader *fs = r300_fs(r300);
192 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
195 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
197 struct r300_fragment_shader *fs = r300_fs(r300);
198 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
199 unsigned count = fs->shader->externals_count;
207 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
208 if (buf->remap_table){
209 for (i = 0; i < count; i++) {
210 float *data = (float*)&buf->ptr[buf->remap_table[i]*4];
211 for (j = 0; j < 4; j++)
212 OUT_CS(pack_float24(data[j]));
215 for (i = 0; i < count; i++)
216 for (j = 0; j < 4; j++)
217 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
223 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
225 struct r300_fragment_shader *fs = r300_fs(r300);
226 struct rc_constant_list *constants = &fs->shader->code.constants;
228 unsigned count = fs->shader->rc_state_count;
229 unsigned first = fs->shader->externals_count;
230 unsigned end = constants->Count;
238 for(i = first; i < end; ++i) {
239 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
242 get_rc_constant_state(data, r300, &constants->Constants[i]);
244 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
245 for (j = 0; j < 4; j++)
246 OUT_CS(pack_float24(data[j]));
252 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
254 struct r300_fragment_shader *fs = r300_fs(r300);
257 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
260 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
262 struct r300_fragment_shader *fs = r300_fs(r300);
263 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
264 unsigned count = fs->shader->externals_count;
271 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
272 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
273 if (buf->remap_table){
274 for (unsigned i = 0; i < count; i++) {
275 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
276 OUT_CS_TABLE(data, 4);
279 OUT_CS_TABLE(buf->ptr, count * 4);
284 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
286 struct r300_fragment_shader *fs = r300_fs(r300);
287 struct rc_constant_list *constants = &fs->shader->code.constants;
289 unsigned count = fs->shader->rc_state_count;
290 unsigned first = fs->shader->externals_count;
291 unsigned end = constants->Count;
298 for(i = first; i < end; ++i) {
299 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
302 get_rc_constant_state(data, r300, &constants->Constants[i]);
304 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
305 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
306 (i & R500_GA_US_VECTOR_INDEX_MASK));
307 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
308 OUT_CS_TABLE(data, 4);
314 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
316 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
317 struct pipe_framebuffer_state* fb =
318 (struct pipe_framebuffer_state*)r300->fb_state.state;
319 uint32_t height = fb->height;
320 uint32_t width = fb->width;
323 if (r300->cbzb_clear) {
324 struct r300_surface *surf = r300_surface(fb->cbufs[0]);
326 height = surf->cbzb_height;
327 width = surf->cbzb_width;
330 DBG(r300, DBG_SCISSOR,
331 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
332 width, height, r300->cbzb_clear ? "YES" : "NO");
337 * By writing to the SC registers, SC & US assert idle. */
338 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
339 if (r300->screen->caps.is_r500) {
341 OUT_CS(((width - 1) << R300_SCISSORS_X_SHIFT) |
342 ((height - 1) << R300_SCISSORS_Y_SHIFT));
344 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
345 (1440 << R300_SCISSORS_Y_SHIFT));
346 OUT_CS(((width + 1440-1) << R300_SCISSORS_X_SHIFT) |
347 ((height + 1440-1) << R300_SCISSORS_Y_SHIFT));
350 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
351 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
355 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
357 struct r300_aa_state *aa = (struct r300_aa_state*)state;
361 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
364 OUT_CS_REG(R300_RB3D_AARESOLVE_OFFSET, aa->dest->offset);
365 OUT_CS_RELOC(aa->dest);
366 OUT_CS_REG(R300_RB3D_AARESOLVE_PITCH, aa->dest->pitch);
369 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, aa->aaresolve_ctl);
373 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
375 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
376 struct r300_surface* surf;
378 uint32_t rb3d_cctl = 0;
384 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
385 * what we usually want. */
386 if (r300->screen->caps.is_r500) {
387 rb3d_cctl = R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE;
389 if (fb->nr_cbufs && r300->fb_multiwrite) {
390 rb3d_cctl |= R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs);
393 OUT_CS_REG(R300_RB3D_CCTL, rb3d_cctl);
395 /* Set up colorbuffers. */
396 for (i = 0; i < fb->nr_cbufs; i++) {
397 surf = r300_surface(fb->cbufs[i]);
399 OUT_CS_REG(R300_RB3D_COLOROFFSET0 + (4 * i), surf->offset);
402 OUT_CS_REG(R300_RB3D_COLORPITCH0 + (4 * i), surf->pitch);
406 /* Set up the ZB part of the CBZB clear. */
407 if (r300->cbzb_clear) {
408 surf = r300_surface(fb->cbufs[0]);
410 OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format);
412 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->cbzb_midpoint_offset);
415 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->cbzb_pitch);
419 "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format,
422 /* Set up a zbuffer. */
423 else if (fb->zsbuf) {
424 surf = r300_surface(fb->zsbuf);
426 OUT_CS_REG(R300_ZB_FORMAT, surf->format);
428 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->offset);
431 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->pitch);
434 if (r300->hyperz_enabled) {
436 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
437 OUT_CS_REG(R300_ZB_HIZ_PITCH, surf->pitch_hiz);
438 /* Z Mask RAM. (compressed zbuffer) */
439 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
440 OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf->pitch_zmask);
442 /* Set up a dummy zbuffer. Otherwise occlusion queries won't work.
443 * Use the first colorbuffer, we will disable writes in the DSA state
444 * so as not to corrupt it. */
445 } else if (fb->nr_cbufs) {
446 surf = r300_surface(fb->cbufs[0]);
448 OUT_CS_REG(R300_ZB_FORMAT, R300_DEPTHFORMAT_16BIT_INT_Z);
450 OUT_CS_REG(R300_ZB_DEPTHOFFSET, 0);
453 OUT_CS_REG(R300_ZB_DEPTHPITCH, 4 | R300_DEPTHMICROTILE_TILED_SQUARE);
460 void r300_emit_hyperz_state(struct r300_context *r300,
461 unsigned size, void *state)
463 struct r300_hyperz_state *z = state;
467 WRITE_CS_TABLE(&z->cb_flush_begin, size);
469 WRITE_CS_TABLE(&z->cb_begin, size - 2);
472 void r300_emit_hyperz_end(struct r300_context *r300)
474 struct r300_hyperz_state z =
475 *(struct r300_hyperz_state*)r300->hyperz_state.state;
479 z.zb_depthclearvalue = 0;
480 z.sc_hyperz = R300_SC_HYPERZ_ADJ_2;
481 z.gb_z_peq_config = 0;
483 r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z);
486 void r300_emit_fb_state_pipelined(struct r300_context *r300,
487 unsigned size, void *state)
489 struct pipe_framebuffer_state* fb =
490 (struct pipe_framebuffer_state*)r300->fb_state.state;
491 unsigned i, num_cbufs = fb->nr_cbufs;
492 unsigned mspos0, mspos1;
495 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
496 * marked as UNUSED in the US block. */
497 if (r300->fb_multiwrite) {
498 num_cbufs = MIN2(num_cbufs, 1);
503 /* Colorbuffer format in the US block.
504 * (must be written after unpipelined regs) */
505 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
506 for (i = 0; i < num_cbufs; i++) {
507 OUT_CS(r300_surface(fb->cbufs[i])->format);
510 OUT_CS(R300_US_OUT_FMT_C4_8 |
511 R300_C0_SEL_B | R300_C1_SEL_G |
512 R300_C2_SEL_R | R300_C3_SEL_A);
515 OUT_CS(R300_US_OUT_FMT_UNUSED);
518 /* Multisampling. Depends on framebuffer sample count.
519 * These are pipelined regs and as such cannot be moved
520 * to the AA state. */
524 if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) {
525 /* Subsample placement. These may not be optimal. */
526 switch (fb->cbufs[0]->texture->nr_samples) {
544 debug_printf("r300: Bad number of multisamples!\n");
548 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
554 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
556 struct r300_query *query = r300->query_current;
563 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
564 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
566 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
568 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
570 query->begin_emitted = TRUE;
573 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
574 struct r300_query *query)
576 struct r300_capabilities* caps = &r300->screen->caps;
577 uint32_t gb_pipes = r300->screen->info.r300_num_gb_pipes;
582 BEGIN_CS(6 * gb_pipes + 2);
583 /* I'm not so sure I like this switch, but it's hard to be elegant
584 * when there's so many special cases...
586 * So here's the basic idea. For each pipe, enable writes to it only,
587 * then put out the relocation for ZPASS_ADDR, taking into account a
588 * 4-byte offset for each pipe. RV380 and older are special; they have
589 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
590 * so there's a chipset cap for that. */
594 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
595 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 3) * 4);
596 OUT_CS_RELOC(r300->query_current);
599 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
600 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 2) * 4);
601 OUT_CS_RELOC(r300->query_current);
604 /* As mentioned above, accomodate RV380 and older. */
605 OUT_CS_REG(R300_SU_REG_DEST,
606 1 << (caps->high_second_pipe ? 3 : 1));
607 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
608 OUT_CS_RELOC(r300->query_current);
611 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
612 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
613 OUT_CS_RELOC(r300->query_current);
616 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
617 " pixel pipes!\n", gb_pipes);
621 /* And, finally, reset it to normal... */
622 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
626 static void rv530_emit_query_end_single_z(struct r300_context *r300,
627 struct r300_query *query)
632 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
633 OUT_CS_REG(R300_ZB_ZPASS_ADDR, query->num_results * 4);
634 OUT_CS_RELOC(r300->query_current);
635 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
639 static void rv530_emit_query_end_double_z(struct r300_context *r300,
640 struct r300_query *query)
645 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
646 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
647 OUT_CS_RELOC(r300->query_current);
648 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
649 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
650 OUT_CS_RELOC(r300->query_current);
651 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
655 void r300_emit_query_end(struct r300_context* r300)
657 struct r300_capabilities *caps = &r300->screen->caps;
658 struct r300_query *query = r300->query_current;
663 if (query->begin_emitted == FALSE)
666 if (caps->family == CHIP_FAMILY_RV530) {
667 if (r300->screen->info.r300_num_z_pipes == 2)
668 rv530_emit_query_end_double_z(r300, query);
670 rv530_emit_query_end_single_z(r300, query);
672 r300_emit_query_end_frag_pipes(r300, query);
674 query->begin_emitted = FALSE;
675 query->num_results += query->num_pipes;
677 /* XXX grab all the results and reset the counter. */
678 if (query->num_results >= query->buf->size / 4 - 4) {
679 query->num_results = (query->buf->size / 4) / 2;
680 fprintf(stderr, "r300: Rewinding OQBO...\n");
684 void r300_emit_invariant_state(struct r300_context *r300,
685 unsigned size, void *state)
688 WRITE_CS_TABLE(state, size);
691 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
693 struct r300_rs_state* rs = state;
697 OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE);
698 if (rs->polygon_offset_enable) {
699 if (r300->zbuffer_bpp == 16) {
700 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
702 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
708 void r300_emit_rs_block_state(struct r300_context* r300,
709 unsigned size, void* state)
711 struct r300_rs_block* rs = (struct r300_rs_block*)state;
713 /* It's the same for both INST and IP tables */
714 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
717 if (DBG_ON(r300, DBG_RS_BLOCK)) {
718 r500_dump_rs_block(rs);
720 fprintf(stderr, "r300: RS emit:\n");
722 for (i = 0; i < count; i++)
723 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]);
725 for (i = 0; i < count; i++)
726 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]);
728 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n",
729 rs->count, rs->inst_count);
733 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
734 OUT_CS(rs->vap_vtx_state_cntl);
735 OUT_CS(rs->vap_vsm_vtx_assm);
736 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
737 OUT_CS(rs->vap_out_vtx_fmt[0]);
738 OUT_CS(rs->vap_out_vtx_fmt[1]);
739 OUT_CS_REG_SEQ(R300_GB_ENABLE, 1);
740 OUT_CS(rs->gb_enable);
742 if (r300->screen->caps.is_r500) {
743 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
745 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
747 OUT_CS_TABLE(rs->ip, count);
749 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
751 OUT_CS(rs->inst_count);
753 if (r300->screen->caps.is_r500) {
754 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
756 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
758 OUT_CS_TABLE(rs->inst, count);
762 void r300_emit_scissor_state(struct r300_context* r300,
763 unsigned size, void* state)
765 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
769 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
770 if (r300->screen->caps.is_r500) {
771 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
772 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
773 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
774 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
776 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
777 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
778 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
779 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
784 void r300_emit_textures_state(struct r300_context *r300,
785 unsigned size, void *state)
787 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
788 struct r300_texture_sampler_state *texstate;
789 struct r300_resource *tex;
791 boolean has_us_format = r300->screen->caps.has_us_format;
795 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
797 for (i = 0; i < allstate->count; i++) {
798 if ((1 << i) & allstate->tx_enable) {
799 texstate = &allstate->regs[i];
800 tex = r300_resource(allstate->sampler_views[i]->base.texture);
802 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
803 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
804 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
805 texstate->border_color);
807 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
808 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
809 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
811 OUT_CS_REG(R300_TX_OFFSET_0 + (i * 4), texstate->format.tile_config);
815 OUT_CS_REG(R500_US_FORMAT0_0 + (i * 4),
816 texstate->format.us_format0);
823 void r300_emit_vertex_arrays(struct r300_context* r300, int offset,
824 boolean indexed, int instance_id)
826 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
827 struct pipe_vertex_element *velem = r300->velems->velem;
828 struct r300_resource *buf;
830 unsigned vertex_array_count = r300->velems->count;
831 unsigned packet_size = (vertex_array_count * 3 + 1) / 2;
832 struct pipe_vertex_buffer *vb1, *vb2;
833 unsigned *hw_format_size = r300->velems->format_size;
834 unsigned size1, size2, offset1, offset2, stride1, stride2;
837 BEGIN_CS(2 + packet_size + vertex_array_count * 2);
838 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
839 OUT_CS(vertex_array_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
841 if (instance_id == -1) {
842 /* Non-instanced arrays. This ignores instance_divisor and instance_id. */
843 for (i = 0; i < vertex_array_count - 1; i += 2) {
844 vb1 = &vbuf[velem[i].vertex_buffer_index];
845 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
846 size1 = hw_format_size[i];
847 size2 = hw_format_size[i+1];
849 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
850 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
851 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
852 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
855 if (vertex_array_count & 1) {
856 vb1 = &vbuf[velem[i].vertex_buffer_index];
857 size1 = hw_format_size[i];
859 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
860 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
863 for (i = 0; i < vertex_array_count; i++) {
864 buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer);
868 /* Instanced arrays. */
869 for (i = 0; i < vertex_array_count - 1; i += 2) {
870 vb1 = &vbuf[velem[i].vertex_buffer_index];
871 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
872 size1 = hw_format_size[i];
873 size2 = hw_format_size[i+1];
875 if (velem[i].instance_divisor) {
877 offset1 = vb1->buffer_offset + velem[i].src_offset +
878 (instance_id / velem[i].instance_divisor) * vb1->stride;
880 stride1 = vb1->stride;
881 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride;
883 if (velem[i+1].instance_divisor) {
885 offset2 = vb2->buffer_offset + velem[i+1].src_offset +
886 (instance_id / velem[i+1].instance_divisor) * vb2->stride;
888 stride2 = vb2->stride;
889 offset2 = vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride;
892 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1) |
893 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(stride2));
898 if (vertex_array_count & 1) {
899 vb1 = &vbuf[velem[i].vertex_buffer_index];
900 size1 = hw_format_size[i];
902 if (velem[i].instance_divisor) {
904 offset1 = vb1->buffer_offset + velem[i].src_offset +
905 (instance_id / velem[i].instance_divisor) * vb1->stride;
907 stride1 = vb1->stride;
908 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride;
911 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1));
915 for (i = 0; i < vertex_array_count; i++) {
916 buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer);
923 void r300_emit_vertex_arrays_swtcl(struct r300_context *r300, boolean indexed)
927 DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, "
928 "vertex size %d\n", r300->vbo,
929 r300->vertex_info.size);
930 /* Set the pointer to our vertex buffer. The emitted values are this:
931 * PACKET3 [3D_LOAD_VBPNTR]
933 * FORMAT [size | stride << 8]
934 * OFFSET [offset into BO]
935 * VBPNTR [relocated BO]
938 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
939 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
940 OUT_CS(r300->vertex_info.size |
941 (r300->vertex_info.size << 8));
942 OUT_CS(r300->draw_vbo_offset);
944 OUT_CS_RELOC(r300_resource(r300->vbo));
948 void r300_emit_vertex_stream_state(struct r300_context* r300,
949 unsigned size, void* state)
951 struct r300_vertex_stream_state *streams =
952 (struct r300_vertex_stream_state*)state;
956 if (DBG_ON(r300, DBG_PSC)) {
957 fprintf(stderr, "r300: PSC emit:\n");
959 for (i = 0; i < streams->count; i++) {
960 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i,
961 streams->vap_prog_stream_cntl[i]);
964 for (i = 0; i < streams->count; i++) {
965 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
966 streams->vap_prog_stream_cntl_ext[i]);
971 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
972 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
973 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
974 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
978 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
983 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
987 void r300_emit_vap_invariant_state(struct r300_context *r300,
988 unsigned size, void *state)
991 WRITE_CS_TABLE(state, size);
994 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
996 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
997 struct r300_vertex_program_code* code = &vs->code;
998 struct r300_screen* r300screen = r300->screen;
999 unsigned instruction_count = code->length / 4;
1001 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
1002 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
1003 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
1004 unsigned temp_count = MAX2(code->num_temporaries, 1);
1006 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
1007 vtx_mem_size / output_count, 10);
1008 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5);
1014 /* R300_VAP_PVS_CODE_CNTL_0
1015 * R300_VAP_PVS_CONST_CNTL
1016 * R300_VAP_PVS_CODE_CNTL_1
1017 * See the r5xx docs for instructions on how to use these. */
1018 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) |
1019 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
1020 R300_PVS_LAST_INST(instruction_count - 1));
1021 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, instruction_count - 1);
1023 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
1024 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
1025 OUT_CS_TABLE(code->body.d, code->length);
1027 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
1028 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
1029 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
1030 R300_PVS_VF_MAX_VTX_NUM(12) |
1031 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
1033 /* Emit flow control instructions. Even if there are no fc instructions,
1034 * we still need to write the registers to make sure they are cleared. */
1035 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
1036 if (r300screen->caps.is_r500) {
1037 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, R300_VS_MAX_FC_OPS * 2);
1038 OUT_CS_TABLE(code->fc_op_addrs.r500, R300_VS_MAX_FC_OPS * 2);
1040 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, R300_VS_MAX_FC_OPS);
1041 OUT_CS_TABLE(code->fc_op_addrs.r300, R300_VS_MAX_FC_OPS);
1043 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, R300_VS_MAX_FC_OPS);
1044 OUT_CS_TABLE(code->fc_loop_index, R300_VS_MAX_FC_OPS);
1049 void r300_emit_vs_constants(struct r300_context* r300,
1050 unsigned size, void *state)
1053 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
1054 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
1055 struct r300_vertex_shader *vs = (struct r300_vertex_shader*)r300->vs_state.state;
1057 int imm_first = vs->externals_count;
1058 int imm_end = vs->code.constants.Count;
1059 int imm_count = vs->immediates_count;
1063 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL,
1064 R300_PVS_CONST_BASE_OFFSET(buf->buffer_base) |
1065 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end - 1, 0)));
1066 if (vs->externals_count) {
1067 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1068 (r300->screen->caps.is_r500 ?
1069 R500_PVS_CONST_START : R300_PVS_CONST_START) + buf->buffer_base);
1070 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1071 if (buf->remap_table){
1072 for (i = 0; i < count; i++) {
1073 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
1074 OUT_CS_TABLE(data, 4);
1077 OUT_CS_TABLE(buf->ptr, count * 4);
1081 /* Emit immediates. */
1083 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1084 (r300->screen->caps.is_r500 ?
1085 R500_PVS_CONST_START : R300_PVS_CONST_START) +
1086 buf->buffer_base + imm_first);
1087 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
1088 for (i = imm_first; i < imm_end; i++) {
1089 const float *data = vs->code.constants.Constants[i].u.Immediate;
1090 OUT_CS_TABLE(data, 4);
1096 void r300_emit_viewport_state(struct r300_context* r300,
1097 unsigned size, void* state)
1099 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1103 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1104 OUT_CS_TABLE(&viewport->xscale, 6);
1105 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1109 void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state)
1111 struct pipe_framebuffer_state *fb =
1112 (struct pipe_framebuffer_state*)r300->fb_state.state;
1113 struct r300_resource* tex;
1116 tex = r300_resource(fb->zsbuf->texture);
1119 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2);
1121 OUT_CS(tex->tex.hiz_dwords[fb->zsbuf->u.tex.level]);
1122 OUT_CS(r300->hiz_clear_value);
1125 /* Mark the current zbuffer's hiz ram as in use. */
1126 r300->hiz_in_use = TRUE;
1127 r300->hiz_func = HIZ_FUNC_NONE;
1128 r300_mark_atom_dirty(r300, &r300->hyperz_state);
1131 void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state)
1133 struct pipe_framebuffer_state *fb =
1134 (struct pipe_framebuffer_state*)r300->fb_state.state;
1135 struct r300_resource *tex;
1138 tex = r300_resource(fb->zsbuf->texture);
1141 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2);
1143 OUT_CS(tex->tex.zmask_dwords[fb->zsbuf->u.tex.level]);
1147 /* Mark the current zbuffer's zmask as in use. */
1148 r300->zmask_in_use = TRUE;
1149 r300_mark_atom_dirty(r300, &r300->hyperz_state);
1152 void r300_emit_ztop_state(struct r300_context* r300,
1153 unsigned size, void* state)
1155 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1159 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1163 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1168 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1172 boolean r300_emit_buffer_validate(struct r300_context *r300,
1173 boolean do_validate_vertex_buffers,
1174 struct pipe_resource *index_buffer)
1176 struct pipe_framebuffer_state *fb =
1177 (struct pipe_framebuffer_state*)r300->fb_state.state;
1178 struct r300_textures_state *texstate =
1179 (struct r300_textures_state*)r300->textures_state.state;
1180 struct r300_resource *tex;
1182 boolean flushed = FALSE;
1185 if (r300->fb_state.dirty) {
1186 /* Color buffers... */
1187 for (i = 0; i < fb->nr_cbufs; i++) {
1188 tex = r300_resource(fb->cbufs[i]->texture);
1189 assert(tex && tex->buf && "cbuf is marked, but NULL!");
1190 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf,
1191 RADEON_USAGE_READWRITE,
1192 r300_surface(fb->cbufs[i])->domain);
1194 /* ...depth buffer... */
1196 tex = r300_resource(fb->zsbuf->texture);
1197 assert(tex && tex->buf && "zsbuf is marked, but NULL!");
1198 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf,
1199 RADEON_USAGE_READWRITE,
1200 r300_surface(fb->zsbuf)->domain);
1203 if (r300->textures_state.dirty) {
1204 /* ...textures... */
1205 for (i = 0; i < texstate->count; i++) {
1206 if (!(texstate->tx_enable & (1 << i))) {
1210 tex = r300_resource(texstate->sampler_views[i]->base.texture);
1211 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, RADEON_USAGE_READ,
1215 /* ...occlusion query buffer... */
1216 if (r300->query_current)
1217 r300->rws->cs_add_reloc(r300->cs, r300->query_current->cs_buf,
1218 RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
1219 /* ...vertex buffer for SWTCL path... */
1221 r300->rws->cs_add_reloc(r300->cs, r300_resource(r300->vbo)->cs_buf,
1223 r300_resource(r300->vbo)->domain);
1224 /* ...vertex buffers for HWTCL path... */
1225 if (do_validate_vertex_buffers && r300->vertex_arrays_dirty) {
1226 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1227 struct pipe_vertex_buffer *last = r300->vertex_buffer +
1228 r300->nr_vertex_buffers;
1229 struct pipe_resource *buf;
1231 for (; vbuf != last; vbuf++) {
1236 r300->rws->cs_add_reloc(r300->cs, r300_resource(buf)->cs_buf,
1238 r300_resource(buf)->domain);
1241 /* ...and index buffer for HWTCL path. */
1243 r300->rws->cs_add_reloc(r300->cs, r300_resource(index_buffer)->cs_buf,
1245 r300_resource(index_buffer)->domain);
1247 /* Now do the validation (flush is called inside cs_validate on failure). */
1248 if (!r300->rws->cs_validate(r300->cs)) {
1249 /* Ooops, an infinite loop, give up. */
1260 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1262 struct r300_atom* atom;
1263 unsigned dwords = 0;
1265 foreach_dirty_atom(r300, atom) {
1267 dwords += atom->size;
1271 /* let's reserve some more, just in case */
1277 unsigned r300_get_num_cs_end_dwords(struct r300_context *r300)
1279 unsigned dwords = 0;
1281 /* Emitted in flush. */
1282 dwords += 26; /* emit_query_end */
1283 dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
1284 if (r300->screen->caps.is_r500)
1290 /* Emit all dirty state. */
1291 void r300_emit_dirty_state(struct r300_context* r300)
1293 struct r300_atom *atom;
1295 foreach_dirty_atom(r300, atom) {
1297 atom->emit(r300, atom->size, atom->state);
1298 atom->dirty = FALSE;
1302 r300->first_dirty = NULL;
1303 r300->last_dirty = NULL;