2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
30 #include "r300_context.h"
33 #include "r300_emit.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
39 void r300_emit_blend_state(struct r300_context* r300,
40 unsigned size, void* state)
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 struct pipe_framebuffer_state* fb =
44 (struct pipe_framebuffer_state*)r300->fb_state.state;
48 if (fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT) {
49 WRITE_CS_TABLE(blend->cb_noclamp, size);
51 unsigned swz = r300_surface(fb->cbufs[0])->colormask_swizzle;
52 WRITE_CS_TABLE(blend->cb_clamp[swz], size);
55 WRITE_CS_TABLE(blend->cb_no_readwrite, size);
59 void r300_emit_blend_color_state(struct r300_context* r300,
60 unsigned size, void* state)
62 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
65 WRITE_CS_TABLE(bc->cb, size);
68 void r300_emit_clip_state(struct r300_context* r300,
69 unsigned size, void* state)
71 struct r300_clip_state* clip = (struct r300_clip_state*)state;
74 WRITE_CS_TABLE(clip->cb, size);
77 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
79 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
80 struct pipe_framebuffer_state* fb =
81 (struct pipe_framebuffer_state*)r300->fb_state.state;
82 boolean is_r500 = r300->screen->caps.is_r500;
84 uint32_t alpha_func = dsa->alpha_function;
86 /* Choose the alpha ref value between 8-bit (FG_ALPHA_FUNC.AM_VAL) and
87 * 16-bit (FG_ALPHA_VALUE). */
88 if (is_r500 && (alpha_func & R300_FG_ALPHA_FUNC_ENABLE)) {
89 if (fb->nr_cbufs && fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT) {
90 alpha_func |= R500_FG_ALPHA_FUNC_FP16_ENABLE;
92 alpha_func |= R500_FG_ALPHA_FUNC_8BIT;
96 /* Setup alpha-to-coverage. */
97 if (r300->alpha_to_coverage && r300->msaa_enable) {
98 /* Always set 3/6, it improves precision even for 2x and 4x MSAA. */
99 alpha_func |= R300_FG_ALPHA_FUNC_MASK_ENABLE |
100 R300_FG_ALPHA_FUNC_CFG_3_OF_6;
104 OUT_CS_REG(R300_FG_ALPHA_FUNC, alpha_func);
105 OUT_CS_TABLE(fb->zsbuf ? &dsa->cb_begin : dsa->cb_zb_no_readwrite, size-2);
109 static void get_rc_constant_state(
111 struct r300_context * r300,
112 struct rc_constant * constant)
114 struct r300_textures_state* texstate = r300->textures_state.state;
115 struct r300_resource *tex;
117 assert(constant->Type == RC_CONSTANT_STATE);
119 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
120 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
123 switch (constant->u.State[0]) {
124 /* Factor for converting rectangle coords to
125 * normalized coords. Should only show up on non-r500. */
126 case RC_STATE_R300_TEXRECT_FACTOR:
127 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
128 vec[0] = 1.0 / tex->tex.width0;
129 vec[1] = 1.0 / tex->tex.height0;
134 case RC_STATE_R300_TEXSCALE_FACTOR:
135 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
136 /* Add a small number to the texture size to work around rounding errors in hw. */
137 vec[0] = tex->b.b.width0 / (tex->tex.width0 + 0.001f);
138 vec[1] = tex->b.b.height0 / (tex->tex.height0 + 0.001f);
139 vec[2] = tex->b.b.depth0 / (tex->tex.depth0 + 0.001f);
143 case RC_STATE_R300_VIEWPORT_SCALE:
144 vec[0] = r300->viewport.scale[0];
145 vec[1] = r300->viewport.scale[1];
146 vec[2] = r300->viewport.scale[2];
150 case RC_STATE_R300_VIEWPORT_OFFSET:
151 vec[0] = r300->viewport.translate[0];
152 vec[1] = r300->viewport.translate[1];
153 vec[2] = r300->viewport.translate[2];
158 fprintf(stderr, "r300: Implementation error: "
159 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
167 /* Convert a normal single-precision float into the 7.16 format
168 * used by the R300 fragment shader.
170 uint32_t pack_float24(float f)
178 uint32_t float24 = 0;
185 mantissa = frexpf(f, &exponent);
189 float24 |= (1 << 23);
190 mantissa = mantissa * -1.0;
192 /* Handle exponent, bias of 63 */
194 float24 |= (exponent << 16);
195 /* Kill 7 LSB of mantissa */
196 float24 |= (u.u & 0x7FFFFF) >> 7;
201 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
203 struct r300_fragment_shader *fs = r300_fs(r300);
206 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
209 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
211 struct r300_fragment_shader *fs = r300_fs(r300);
212 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
213 unsigned count = fs->shader->externals_count;
221 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
222 if (buf->remap_table){
223 for (i = 0; i < count; i++) {
224 float *data = (float*)&buf->ptr[buf->remap_table[i]*4];
225 for (j = 0; j < 4; j++)
226 OUT_CS(pack_float24(data[j]));
229 for (i = 0; i < count; i++)
230 for (j = 0; j < 4; j++)
231 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
237 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
239 struct r300_fragment_shader *fs = r300_fs(r300);
240 struct rc_constant_list *constants = &fs->shader->code.constants;
242 unsigned count = fs->shader->rc_state_count;
243 unsigned first = fs->shader->externals_count;
244 unsigned end = constants->Count;
252 for(i = first; i < end; ++i) {
253 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
256 get_rc_constant_state(data, r300, &constants->Constants[i]);
258 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
259 for (j = 0; j < 4; j++)
260 OUT_CS(pack_float24(data[j]));
266 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
268 struct r300_fragment_shader *fs = r300_fs(r300);
271 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
274 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
276 struct r300_fragment_shader *fs = r300_fs(r300);
277 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
278 unsigned count = fs->shader->externals_count;
285 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
286 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
287 if (buf->remap_table){
288 for (unsigned i = 0; i < count; i++) {
289 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
290 OUT_CS_TABLE(data, 4);
293 OUT_CS_TABLE(buf->ptr, count * 4);
298 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
300 struct r300_fragment_shader *fs = r300_fs(r300);
301 struct rc_constant_list *constants = &fs->shader->code.constants;
303 unsigned count = fs->shader->rc_state_count;
304 unsigned first = fs->shader->externals_count;
305 unsigned end = constants->Count;
312 for(i = first; i < end; ++i) {
313 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
316 get_rc_constant_state(data, r300, &constants->Constants[i]);
318 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
319 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
320 (i & R500_GA_US_VECTOR_INDEX_MASK));
321 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
322 OUT_CS_TABLE(data, 4);
328 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
330 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
331 struct pipe_framebuffer_state* fb =
332 (struct pipe_framebuffer_state*)r300->fb_state.state;
333 uint32_t height = fb->height;
334 uint32_t width = fb->width;
337 if (r300->cbzb_clear) {
338 struct r300_surface *surf = r300_surface(fb->cbufs[0]);
340 height = surf->cbzb_height;
341 width = surf->cbzb_width;
344 DBG(r300, DBG_SCISSOR,
345 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
346 width, height, r300->cbzb_clear ? "YES" : "NO");
351 * By writing to the SC registers, SC & US assert idle. */
352 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
353 if (r300->screen->caps.is_r500) {
355 OUT_CS(((width - 1) << R300_SCISSORS_X_SHIFT) |
356 ((height - 1) << R300_SCISSORS_Y_SHIFT));
358 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
359 (1440 << R300_SCISSORS_Y_SHIFT));
360 OUT_CS(((width + 1440-1) << R300_SCISSORS_X_SHIFT) |
361 ((height + 1440-1) << R300_SCISSORS_Y_SHIFT));
364 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
365 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
369 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
371 struct r300_aa_state *aa = (struct r300_aa_state*)state;
375 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
378 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 3);
379 OUT_CS(aa->dest->offset);
380 OUT_CS(aa->dest->pitch & R300_RB3D_AARESOLVE_PITCH_MASK);
381 OUT_CS(R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE |
382 R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE);
383 OUT_CS_RELOC(aa->dest);
385 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0);
391 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
393 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
394 struct r300_surface* surf;
396 uint32_t rb3d_cctl = 0;
402 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
403 * what we usually want. */
404 if (r300->screen->caps.is_r500) {
405 rb3d_cctl = R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE;
407 if (fb->nr_cbufs && r300->fb_multiwrite) {
408 rb3d_cctl |= R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs);
411 OUT_CS_REG(R300_RB3D_CCTL, rb3d_cctl);
413 /* Set up colorbuffers. */
414 for (i = 0; i < fb->nr_cbufs; i++) {
415 surf = r300_surface(fb->cbufs[i]);
417 OUT_CS_REG(R300_RB3D_COLOROFFSET0 + (4 * i), surf->offset);
420 OUT_CS_REG(R300_RB3D_COLORPITCH0 + (4 * i), surf->pitch);
424 /* Set up the ZB part of the CBZB clear. */
425 if (r300->cbzb_clear) {
426 surf = r300_surface(fb->cbufs[0]);
428 OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format);
430 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->cbzb_midpoint_offset);
433 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->cbzb_pitch);
437 "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format,
440 /* Set up a zbuffer. */
441 else if (fb->zsbuf) {
442 surf = r300_surface(fb->zsbuf);
444 OUT_CS_REG(R300_ZB_FORMAT, surf->format);
446 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->offset);
449 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->pitch);
452 if (r300->hyperz_enabled) {
454 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
455 OUT_CS_REG(R300_ZB_HIZ_PITCH, surf->pitch_hiz);
456 /* Z Mask RAM. (compressed zbuffer) */
457 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
458 OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf->pitch_zmask);
465 void r300_emit_hyperz_state(struct r300_context *r300,
466 unsigned size, void *state)
468 struct r300_hyperz_state *z = state;
472 WRITE_CS_TABLE(&z->cb_flush_begin, size);
474 WRITE_CS_TABLE(&z->cb_begin, size - 2);
477 void r300_emit_hyperz_end(struct r300_context *r300)
479 struct r300_hyperz_state z =
480 *(struct r300_hyperz_state*)r300->hyperz_state.state;
484 z.zb_depthclearvalue = 0;
485 z.sc_hyperz = R300_SC_HYPERZ_ADJ_2;
486 z.gb_z_peq_config = 0;
488 r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z);
491 #define R300_NIBBLES(x0, y0, x1, y1, x2, y2, d0y, d0x) \
492 (((x0) & 0xf) | (((y0) & 0xf) << 4) | \
493 (((x1) & 0xf) << 8) | (((y1) & 0xf) << 12) | \
494 (((x2) & 0xf) << 16) | (((y2) & 0xf) << 20) | \
495 (((d0y) & 0xf) << 24) | (((d0x) & 0xf) << 28))
497 static unsigned r300_get_mspos(int index, unsigned *p)
499 unsigned reg, i, distx, disty, dist;
502 /* MSPOS0 contains positions for samples 0,1,2 as (X,Y) pairs of nibbles,
503 * followed by a (Y,X) pair containing the minimum distance from the pixel
505 * X0, Y0, X1, Y1, X2, Y2, D0_Y, D0_X
507 * There is a quirk when setting D0_X. The value represents the distance
508 * from the left edge of the pixel quad to the first sample in subpixels.
509 * All values less than eight should use the actual value, but „7‟ should
510 * be used for the distance „8‟. The hardware will convert 7 into 8 internally.
513 for (i = 0; i < 12; i += 2) {
519 for (i = 1; i < 12; i += 2) {
527 reg = R300_NIBBLES(p[0], p[1], p[2], p[3], p[4], p[5], disty, distx);
529 /* MSPOS1 contains positions for samples 3,4,5 as (X,Y) pairs of nibbles,
530 * followed by the minimum distance from the pixel edge (not sure if X or Y):
531 * X3, Y3, X4, Y4, X5, Y5, D1
534 for (i = 0; i < 12; i++) {
539 reg = R300_NIBBLES(p[6], p[7], p[8], p[9], p[10], p[11], dist, 0);
544 void r300_emit_fb_state_pipelined(struct r300_context *r300,
545 unsigned size, void *state)
547 /* The sample coordinates are in the range [0,11], because
548 * GB_TILE_CONFIG.SUBPIXEL is set to the 1/12 subpixel precision.
550 * Some sample coordinates reach to neighboring pixels and should not be used.
553 * The unused samples must be set to the positions of other valid samples. */
554 static unsigned sample_locs_1x[12] = {
555 6,6, 6,6, 6,6, 6,6, 6,6, 6,6
557 static unsigned sample_locs_2x[12] = {
558 3,9, 9,3, 9,3, 9,3, 9,3, 9,3
560 static unsigned sample_locs_4x[12] = {
561 4,4, 8,8, 2,10, 10,2, 10,2, 10,2
563 static unsigned sample_locs_6x[12] = {
564 3,1, 7,3, 11,5, 1,7, 5,9, 9,10
567 struct pipe_framebuffer_state* fb =
568 (struct pipe_framebuffer_state*)r300->fb_state.state;
569 unsigned i, num_samples, num_cbufs = fb->nr_cbufs;
570 unsigned mspos0, mspos1;
573 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
574 * marked as UNUSED in the US block. */
575 if (r300->fb_multiwrite) {
576 num_cbufs = MIN2(num_cbufs, 1);
581 /* Colorbuffer format in the US block.
582 * (must be written after unpipelined regs) */
583 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
584 for (i = 0; i < num_cbufs; i++) {
585 OUT_CS(r300_surface(fb->cbufs[i])->format);
588 OUT_CS(R300_US_OUT_FMT_C4_8 |
589 R300_C0_SEL_B | R300_C1_SEL_G |
590 R300_C2_SEL_R | R300_C3_SEL_A);
593 OUT_CS(R300_US_OUT_FMT_UNUSED);
596 /* Multisampling. Depends on framebuffer sample count.
597 * These are pipelined regs and as such cannot be moved
600 num_samples = r300->msaa_enable ? r300->num_samples : 1;
602 /* Sample positions. */
603 switch (num_samples) {
605 mspos0 = r300_get_mspos(0, sample_locs_1x);
606 mspos1 = r300_get_mspos(1, sample_locs_1x);
609 mspos0 = r300_get_mspos(0, sample_locs_2x);
610 mspos1 = r300_get_mspos(1, sample_locs_2x);
613 mspos0 = r300_get_mspos(0, sample_locs_4x);
614 mspos1 = r300_get_mspos(1, sample_locs_4x);
617 mspos0 = r300_get_mspos(0, sample_locs_6x);
618 mspos1 = r300_get_mspos(1, sample_locs_6x);
622 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
628 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
630 struct r300_query *query = r300->query_current;
637 if (r300->screen->caps.family == CHIP_RV530) {
638 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
640 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
642 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
644 query->begin_emitted = TRUE;
647 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
648 struct r300_query *query)
650 struct r300_capabilities* caps = &r300->screen->caps;
651 uint32_t gb_pipes = r300->screen->info.r300_num_gb_pipes;
656 BEGIN_CS(6 * gb_pipes + 2);
657 /* I'm not so sure I like this switch, but it's hard to be elegant
658 * when there's so many special cases...
660 * So here's the basic idea. For each pipe, enable writes to it only,
661 * then put out the relocation for ZPASS_ADDR, taking into account a
662 * 4-byte offset for each pipe. RV380 and older are special; they have
663 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
664 * so there's a chipset cap for that. */
668 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
669 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 3) * 4);
670 OUT_CS_RELOC(r300->query_current);
673 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
674 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 2) * 4);
675 OUT_CS_RELOC(r300->query_current);
678 /* As mentioned above, accomodate RV380 and older. */
679 OUT_CS_REG(R300_SU_REG_DEST,
680 1 << (caps->high_second_pipe ? 3 : 1));
681 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
682 OUT_CS_RELOC(r300->query_current);
685 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
686 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
687 OUT_CS_RELOC(r300->query_current);
690 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
691 " pixel pipes!\n", gb_pipes);
695 /* And, finally, reset it to normal... */
696 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
700 static void rv530_emit_query_end_single_z(struct r300_context *r300,
701 struct r300_query *query)
706 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
707 OUT_CS_REG(R300_ZB_ZPASS_ADDR, query->num_results * 4);
708 OUT_CS_RELOC(r300->query_current);
709 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
713 static void rv530_emit_query_end_double_z(struct r300_context *r300,
714 struct r300_query *query)
719 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
720 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
721 OUT_CS_RELOC(r300->query_current);
722 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
723 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
724 OUT_CS_RELOC(r300->query_current);
725 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
729 void r300_emit_query_end(struct r300_context* r300)
731 struct r300_capabilities *caps = &r300->screen->caps;
732 struct r300_query *query = r300->query_current;
737 if (query->begin_emitted == FALSE)
740 if (caps->family == CHIP_RV530) {
741 if (r300->screen->info.r300_num_z_pipes == 2)
742 rv530_emit_query_end_double_z(r300, query);
744 rv530_emit_query_end_single_z(r300, query);
746 r300_emit_query_end_frag_pipes(r300, query);
748 query->begin_emitted = FALSE;
749 query->num_results += query->num_pipes;
751 /* XXX grab all the results and reset the counter. */
752 if (query->num_results >= query->buf->size / 4 - 4) {
753 query->num_results = (query->buf->size / 4) / 2;
754 fprintf(stderr, "r300: Rewinding OQBO...\n");
758 void r300_emit_invariant_state(struct r300_context *r300,
759 unsigned size, void *state)
762 WRITE_CS_TABLE(state, size);
765 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
767 struct r300_rs_state* rs = state;
771 OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE);
772 if (rs->polygon_offset_enable) {
773 if (r300->zbuffer_bpp == 16) {
774 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
776 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
782 void r300_emit_rs_block_state(struct r300_context* r300,
783 unsigned size, void* state)
785 struct r300_rs_block* rs = (struct r300_rs_block*)state;
787 /* It's the same for both INST and IP tables */
788 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
791 if (DBG_ON(r300, DBG_RS_BLOCK)) {
792 r500_dump_rs_block(rs);
794 fprintf(stderr, "r300: RS emit:\n");
796 for (i = 0; i < count; i++)
797 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]);
799 for (i = 0; i < count; i++)
800 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]);
802 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n",
803 rs->count, rs->inst_count);
807 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
808 OUT_CS(rs->vap_vtx_state_cntl);
809 OUT_CS(rs->vap_vsm_vtx_assm);
810 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
811 OUT_CS(rs->vap_out_vtx_fmt[0]);
812 OUT_CS(rs->vap_out_vtx_fmt[1]);
813 OUT_CS_REG_SEQ(R300_GB_ENABLE, 1);
814 OUT_CS(rs->gb_enable);
816 if (r300->screen->caps.is_r500) {
817 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
819 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
821 OUT_CS_TABLE(rs->ip, count);
823 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
825 OUT_CS(rs->inst_count);
827 if (r300->screen->caps.is_r500) {
828 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
830 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
832 OUT_CS_TABLE(rs->inst, count);
836 void r300_emit_sample_mask(struct r300_context *r300,
837 unsigned size, void *state)
839 unsigned mask = (*(unsigned*)state) & ((1 << 6)-1);
843 OUT_CS_REG(R300_SC_SCREENDOOR,
844 mask | (mask << 6) | (mask << 12) | (mask << 18));
848 void r300_emit_scissor_state(struct r300_context* r300,
849 unsigned size, void* state)
851 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
855 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
856 if (r300->screen->caps.is_r500) {
857 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
858 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
859 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
860 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
862 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
863 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
864 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
865 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
870 void r300_emit_textures_state(struct r300_context *r300,
871 unsigned size, void *state)
873 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
874 struct r300_texture_sampler_state *texstate;
875 struct r300_resource *tex;
877 boolean has_us_format = r300->screen->caps.has_us_format;
881 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
883 for (i = 0; i < allstate->count; i++) {
884 if ((1 << i) & allstate->tx_enable) {
885 texstate = &allstate->regs[i];
886 tex = r300_resource(allstate->sampler_views[i]->base.texture);
888 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
889 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
890 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
891 texstate->border_color);
893 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
894 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
895 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
897 OUT_CS_REG(R300_TX_OFFSET_0 + (i * 4), texstate->format.tile_config);
901 OUT_CS_REG(R500_US_FORMAT0_0 + (i * 4),
902 texstate->format.us_format0);
909 void r300_emit_vertex_arrays(struct r300_context* r300, int offset,
910 boolean indexed, int instance_id)
912 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
913 struct pipe_vertex_element *velem = r300->velems->velem;
914 struct r300_resource *buf;
916 unsigned vertex_array_count = r300->velems->count;
917 unsigned packet_size = (vertex_array_count * 3 + 1) / 2;
918 struct pipe_vertex_buffer *vb1, *vb2;
919 unsigned *hw_format_size = r300->velems->format_size;
920 unsigned size1, size2, offset1, offset2, stride1, stride2;
923 BEGIN_CS(2 + packet_size + vertex_array_count * 2);
924 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
925 OUT_CS(vertex_array_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
927 if (instance_id == -1) {
928 /* Non-instanced arrays. This ignores instance_divisor and instance_id. */
929 for (i = 0; i < vertex_array_count - 1; i += 2) {
930 vb1 = &vbuf[velem[i].vertex_buffer_index];
931 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
932 size1 = hw_format_size[i];
933 size2 = hw_format_size[i+1];
935 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
936 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
937 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
938 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
941 if (vertex_array_count & 1) {
942 vb1 = &vbuf[velem[i].vertex_buffer_index];
943 size1 = hw_format_size[i];
945 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
946 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
949 for (i = 0; i < vertex_array_count; i++) {
950 buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer);
954 /* Instanced arrays. */
955 for (i = 0; i < vertex_array_count - 1; i += 2) {
956 vb1 = &vbuf[velem[i].vertex_buffer_index];
957 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
958 size1 = hw_format_size[i];
959 size2 = hw_format_size[i+1];
961 if (velem[i].instance_divisor) {
963 offset1 = vb1->buffer_offset + velem[i].src_offset +
964 (instance_id / velem[i].instance_divisor) * vb1->stride;
966 stride1 = vb1->stride;
967 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride;
969 if (velem[i+1].instance_divisor) {
971 offset2 = vb2->buffer_offset + velem[i+1].src_offset +
972 (instance_id / velem[i+1].instance_divisor) * vb2->stride;
974 stride2 = vb2->stride;
975 offset2 = vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride;
978 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1) |
979 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(stride2));
984 if (vertex_array_count & 1) {
985 vb1 = &vbuf[velem[i].vertex_buffer_index];
986 size1 = hw_format_size[i];
988 if (velem[i].instance_divisor) {
990 offset1 = vb1->buffer_offset + velem[i].src_offset +
991 (instance_id / velem[i].instance_divisor) * vb1->stride;
993 stride1 = vb1->stride;
994 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride;
997 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1));
1001 for (i = 0; i < vertex_array_count; i++) {
1002 buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer);
1009 void r300_emit_vertex_arrays_swtcl(struct r300_context *r300, boolean indexed)
1013 DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, "
1014 "vertex size %d\n", r300->vbo,
1015 r300->vertex_info.size);
1016 /* Set the pointer to our vertex buffer. The emitted values are this:
1017 * PACKET3 [3D_LOAD_VBPNTR]
1019 * FORMAT [size | stride << 8]
1020 * OFFSET [offset into BO]
1021 * VBPNTR [relocated BO]
1024 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
1025 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
1026 OUT_CS(r300->vertex_info.size |
1027 (r300->vertex_info.size << 8));
1028 OUT_CS(r300->draw_vbo_offset);
1031 assert(r300->vbo_cs);
1032 cs_winsys->cs_write_reloc(cs_copy, r300->vbo_cs);
1037 void r300_emit_vertex_stream_state(struct r300_context* r300,
1038 unsigned size, void* state)
1040 struct r300_vertex_stream_state *streams =
1041 (struct r300_vertex_stream_state*)state;
1045 if (DBG_ON(r300, DBG_PSC)) {
1046 fprintf(stderr, "r300: PSC emit:\n");
1048 for (i = 0; i < streams->count; i++) {
1049 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i,
1050 streams->vap_prog_stream_cntl[i]);
1053 for (i = 0; i < streams->count; i++) {
1054 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
1055 streams->vap_prog_stream_cntl_ext[i]);
1060 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
1061 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
1062 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
1063 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
1067 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
1072 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
1076 void r300_emit_vap_invariant_state(struct r300_context *r300,
1077 unsigned size, void *state)
1080 WRITE_CS_TABLE(state, size);
1083 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
1085 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
1086 struct r300_vertex_program_code* code = &vs->code;
1087 struct r300_screen* r300screen = r300->screen;
1088 unsigned instruction_count = code->length / 4;
1090 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
1091 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
1092 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
1093 unsigned temp_count = MAX2(code->num_temporaries, 1);
1095 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
1096 vtx_mem_size / output_count, 10);
1097 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5);
1103 /* R300_VAP_PVS_CODE_CNTL_0
1104 * R300_VAP_PVS_CONST_CNTL
1105 * R300_VAP_PVS_CODE_CNTL_1
1106 * See the r5xx docs for instructions on how to use these. */
1107 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) |
1108 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
1109 R300_PVS_LAST_INST(instruction_count - 1));
1110 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, instruction_count - 1);
1112 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
1113 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
1114 OUT_CS_TABLE(code->body.d, code->length);
1116 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
1117 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
1118 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
1119 R300_PVS_VF_MAX_VTX_NUM(12) |
1120 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
1122 /* Emit flow control instructions. Even if there are no fc instructions,
1123 * we still need to write the registers to make sure they are cleared. */
1124 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
1125 if (r300screen->caps.is_r500) {
1126 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, R300_VS_MAX_FC_OPS * 2);
1127 OUT_CS_TABLE(code->fc_op_addrs.r500, R300_VS_MAX_FC_OPS * 2);
1129 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, R300_VS_MAX_FC_OPS);
1130 OUT_CS_TABLE(code->fc_op_addrs.r300, R300_VS_MAX_FC_OPS);
1132 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, R300_VS_MAX_FC_OPS);
1133 OUT_CS_TABLE(code->fc_loop_index, R300_VS_MAX_FC_OPS);
1138 void r300_emit_vs_constants(struct r300_context* r300,
1139 unsigned size, void *state)
1142 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
1143 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
1144 struct r300_vertex_shader *vs = (struct r300_vertex_shader*)r300->vs_state.state;
1146 int imm_first = vs->externals_count;
1147 int imm_end = vs->code.constants.Count;
1148 int imm_count = vs->immediates_count;
1152 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL,
1153 R300_PVS_CONST_BASE_OFFSET(buf->buffer_base) |
1154 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end - 1, 0)));
1155 if (vs->externals_count) {
1156 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1157 (r300->screen->caps.is_r500 ?
1158 R500_PVS_CONST_START : R300_PVS_CONST_START) + buf->buffer_base);
1159 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1160 if (buf->remap_table){
1161 for (i = 0; i < count; i++) {
1162 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
1163 OUT_CS_TABLE(data, 4);
1166 OUT_CS_TABLE(buf->ptr, count * 4);
1170 /* Emit immediates. */
1172 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1173 (r300->screen->caps.is_r500 ?
1174 R500_PVS_CONST_START : R300_PVS_CONST_START) +
1175 buf->buffer_base + imm_first);
1176 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
1177 for (i = imm_first; i < imm_end; i++) {
1178 const float *data = vs->code.constants.Constants[i].u.Immediate;
1179 OUT_CS_TABLE(data, 4);
1185 void r300_emit_viewport_state(struct r300_context* r300,
1186 unsigned size, void* state)
1188 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1192 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1193 OUT_CS_TABLE(&viewport->xscale, 6);
1194 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1198 void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state)
1200 struct pipe_framebuffer_state *fb =
1201 (struct pipe_framebuffer_state*)r300->fb_state.state;
1202 struct r300_resource* tex;
1205 tex = r300_resource(fb->zsbuf->texture);
1208 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
1209 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
1210 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
1211 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2);
1213 OUT_CS(tex->tex.hiz_dwords[fb->zsbuf->u.tex.level]);
1214 OUT_CS(r300->hiz_clear_value);
1217 /* Mark the current zbuffer's hiz ram as in use. */
1218 r300->hiz_in_use = TRUE;
1219 r300->hiz_func = HIZ_FUNC_NONE;
1220 r300_mark_atom_dirty(r300, &r300->hyperz_state);
1223 void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state)
1225 struct pipe_framebuffer_state *fb =
1226 (struct pipe_framebuffer_state*)r300->fb_state.state;
1227 struct r300_resource *tex;
1230 tex = r300_resource(fb->zsbuf->texture);
1233 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
1234 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
1235 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
1236 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2);
1238 OUT_CS(tex->tex.zmask_dwords[fb->zsbuf->u.tex.level]);
1242 /* Mark the current zbuffer's zmask as in use. */
1243 r300->zmask_in_use = TRUE;
1244 r300_mark_atom_dirty(r300, &r300->hyperz_state);
1247 void r300_emit_ztop_state(struct r300_context* r300,
1248 unsigned size, void* state)
1250 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1254 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1258 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1263 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1267 boolean r300_emit_buffer_validate(struct r300_context *r300,
1268 boolean do_validate_vertex_buffers,
1269 struct pipe_resource *index_buffer)
1271 struct pipe_framebuffer_state *fb =
1272 (struct pipe_framebuffer_state*)r300->fb_state.state;
1273 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
1274 struct r300_textures_state *texstate =
1275 (struct r300_textures_state*)r300->textures_state.state;
1276 struct r300_resource *tex;
1278 boolean flushed = FALSE;
1281 if (r300->fb_state.dirty) {
1282 /* Color buffers... */
1283 for (i = 0; i < fb->nr_cbufs; i++) {
1284 tex = r300_resource(fb->cbufs[i]->texture);
1285 assert(tex && tex->buf && "cbuf is marked, but NULL!");
1286 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf,
1287 RADEON_USAGE_READWRITE,
1288 r300_surface(fb->cbufs[i])->domain);
1290 /* ...depth buffer... */
1292 tex = r300_resource(fb->zsbuf->texture);
1293 assert(tex && tex->buf && "zsbuf is marked, but NULL!");
1294 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf,
1295 RADEON_USAGE_READWRITE,
1296 r300_surface(fb->zsbuf)->domain);
1299 /* The AA resolve buffer. */
1300 if (r300->aa_state.dirty) {
1302 r300->rws->cs_add_reloc(r300->cs, aa->dest->cs_buf,
1307 if (r300->textures_state.dirty) {
1308 /* ...textures... */
1309 for (i = 0; i < texstate->count; i++) {
1310 if (!(texstate->tx_enable & (1 << i))) {
1314 tex = r300_resource(texstate->sampler_views[i]->base.texture);
1315 r300->rws->cs_add_reloc(r300->cs, tex->cs_buf, RADEON_USAGE_READ,
1319 /* ...occlusion query buffer... */
1320 if (r300->query_current)
1321 r300->rws->cs_add_reloc(r300->cs, r300->query_current->cs_buf,
1322 RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
1323 /* ...vertex buffer for SWTCL path... */
1325 r300->rws->cs_add_reloc(r300->cs, r300->vbo_cs,
1326 RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1327 /* ...vertex buffers for HWTCL path... */
1328 if (do_validate_vertex_buffers && r300->vertex_arrays_dirty) {
1329 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1330 struct pipe_vertex_buffer *last = r300->vertex_buffer +
1331 r300->nr_vertex_buffers;
1332 struct pipe_resource *buf;
1334 for (; vbuf != last; vbuf++) {
1339 r300->rws->cs_add_reloc(r300->cs, r300_resource(buf)->cs_buf,
1341 r300_resource(buf)->domain);
1344 /* ...and index buffer for HWTCL path. */
1346 r300->rws->cs_add_reloc(r300->cs, r300_resource(index_buffer)->cs_buf,
1348 r300_resource(index_buffer)->domain);
1350 /* Now do the validation (flush is called inside cs_validate on failure). */
1351 if (!r300->rws->cs_validate(r300->cs)) {
1352 /* Ooops, an infinite loop, give up. */
1363 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1365 struct r300_atom* atom;
1366 unsigned dwords = 0;
1368 foreach_dirty_atom(r300, atom) {
1370 dwords += atom->size;
1374 /* let's reserve some more, just in case */
1380 unsigned r300_get_num_cs_end_dwords(struct r300_context *r300)
1382 unsigned dwords = 0;
1384 /* Emitted in flush. */
1385 dwords += 26; /* emit_query_end */
1386 dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
1387 if (r300->screen->caps.is_r500)
1388 dwords += 2; /* emit_index_bias */
1389 if (r300->screen->info.drm_minor >= 6)
1390 dwords += 3; /* MSPOS */
1395 /* Emit all dirty state. */
1396 void r300_emit_dirty_state(struct r300_context* r300)
1398 struct r300_atom *atom;
1400 foreach_dirty_atom(r300, atom) {
1402 atom->emit(r300, atom->size, atom->state);
1403 atom->dirty = FALSE;
1407 r300->first_dirty = NULL;
1408 r300->last_dirty = NULL;