2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23 /* r300_emit: Functions for emitting state. */
25 #include "r300_emit.h"
27 void r300_emit_blend_state(struct r300_context* r300,
28 struct r300_blend_state* blend)
32 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 2);
33 OUT_CS(blend->blend_control);
34 OUT_CS(blend->alpha_blend_control);
35 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
36 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
40 void r300_emit_blend_color_state(struct r300_context* r300,
41 struct r300_blend_color_state* bc)
43 struct r300_screen* r300screen = r300_screen(r300->context.screen);
46 if (r300screen->caps->is_r500) {
48 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
49 OUT_CS(bc->blend_color_red_alpha);
50 OUT_CS(bc->blend_color_green_blue);
54 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
59 void r300_emit_clip_state(struct r300_context* r300,
60 struct pipe_clip_state* clip)
63 struct r300_screen* r300screen = r300_screen(r300->context.screen);
66 if (r300screen->caps->has_tcl) {
67 BEGIN_CS(5 + (6 * 4));
68 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
69 (r300screen->caps->is_r500 ?
70 R500_PVS_UCP_START : R300_PVS_UCP_START));
71 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
72 for (i = 0; i < 6; i++) {
73 OUT_CS_32F(clip->ucp[i][0]);
74 OUT_CS_32F(clip->ucp[i][1]);
75 OUT_CS_32F(clip->ucp[i][2]);
76 OUT_CS_32F(clip->ucp[i][3]);
78 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
79 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
83 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
89 void r300_emit_dsa_state(struct r300_context* r300,
90 struct r300_dsa_state* dsa)
92 struct r300_screen* r300screen = r300_screen(r300->context.screen);
95 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 8);
96 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
97 /* XXX figure out the r300 counterpart for this */
98 if (r300screen->caps->is_r500) {
99 /* OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference); */
101 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
102 OUT_CS(dsa->z_buffer_control);
103 OUT_CS(dsa->z_stencil_control);
104 OUT_CS(dsa->stencil_ref_mask);
105 OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top);
106 if (r300screen->caps->is_r500) {
107 /* OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); */
112 void r300_emit_fragment_shader(struct r300_context* r300,
113 struct r3xx_fragment_shader* fs)
120 OUT_CS_REG(R300_US_CONFIG, fs->indirections);
121 OUT_CS_REG(R300_US_PIXSIZE, fs->shader.stack_size);
122 /* XXX figure out exactly how big the sizes are on this reg */
123 OUT_CS_REG(R300_US_CODE_OFFSET, 0x40);
124 /* XXX figure these ones out a bit better kthnx */
125 OUT_CS_REG(R300_US_CODE_ADDR_0, 0x0);
126 OUT_CS_REG(R300_US_CODE_ADDR_1, 0x0);
127 OUT_CS_REG(R300_US_CODE_ADDR_2, 0x0);
128 OUT_CS_REG(R300_US_CODE_ADDR_3, 0x40 | R300_RGBA_OUT);
130 for (i = 0; i < fs->alu_instruction_count; i++) {
131 OUT_CS_REG(R300_US_ALU_RGB_INST_0 + (4 * i),
132 fs->instructions[i].alu_rgb_inst);
133 OUT_CS_REG(R300_US_ALU_RGB_ADDR_0 + (4 * i),
134 fs->instructions[i].alu_rgb_addr);
135 OUT_CS_REG(R300_US_ALU_ALPHA_INST_0 + (4 * i),
136 fs->instructions[i].alu_alpha_inst);
137 OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0 + (4 * i),
138 fs->instructions[i].alu_alpha_addr);
144 void r500_emit_fragment_shader(struct r300_context* r300,
145 struct r5xx_fragment_shader* fs)
148 struct r300_constant_buffer* constants =
149 &r300->shader_constants[PIPE_SHADER_FRAGMENT];
152 BEGIN_CS(9 + (fs->instruction_count * 6) + (constants->count ? 3 : 0) +
153 (constants->count * 4));
154 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
155 OUT_CS_REG(R500_US_PIXSIZE, fs->shader.stack_size);
156 OUT_CS_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) |
157 R500_US_CODE_END_ADDR(fs->instruction_count));
159 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
160 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, fs->instruction_count * 6);
161 for (i = 0; i < fs->instruction_count; i++) {
162 OUT_CS(fs->instructions[i].inst0);
163 OUT_CS(fs->instructions[i].inst1);
164 OUT_CS(fs->instructions[i].inst2);
165 OUT_CS(fs->instructions[i].inst3);
166 OUT_CS(fs->instructions[i].inst4);
167 OUT_CS(fs->instructions[i].inst5);
170 if (constants->count) {
171 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
172 R500_GA_US_VECTOR_INDEX_TYPE_CONST);
173 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->count * 4);
174 for (i = 0; i < constants->count; i++) {
175 OUT_CS_32F(constants->constants[i][0]);
176 OUT_CS_32F(constants->constants[i][1]);
177 OUT_CS_32F(constants->constants[i][2]);
178 OUT_CS_32F(constants->constants[i][3]);
185 void r300_emit_fb_state(struct r300_context* r300,
186 struct pipe_framebuffer_state* fb)
188 struct r300_texture* tex;
193 BEGIN_CS((8 * fb->nr_cbufs) + (fb->zsbuf ? 8 : 0) + 4);
194 for (i = 0; i < fb->nr_cbufs; i++) {
195 tex = (struct r300_texture*)fb->cbufs[i]->texture;
196 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
197 pixpitch = tex->stride / tex->tex.block.size;
199 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
200 OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
202 OUT_CS_REG(R300_RB3D_COLORPITCH0 + (4 * i), pixpitch |
203 r300_translate_colorformat(tex->tex.format));
205 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
206 r300_translate_out_fmt(fb->cbufs[i]->format));
210 tex = (struct r300_texture*)fb->zsbuf->texture;
211 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
212 pixpitch = tex->stride / tex->tex.block.size;
214 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
215 OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
217 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
219 OUT_CS_REG(R300_ZB_DEPTHPITCH, pixpitch);
222 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
223 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
224 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
225 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
226 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
227 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
231 void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs)
236 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
237 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
238 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
239 OUT_CS(rs->point_minmax);
240 OUT_CS(rs->line_control);
241 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
242 OUT_CS(rs->depth_scale_front);
243 OUT_CS(rs->depth_offset_front);
244 OUT_CS(rs->depth_scale_back);
245 OUT_CS(rs->depth_offset_back);
246 OUT_CS(rs->polygon_offset_enable);
247 OUT_CS(rs->cull_mode);
248 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
249 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
250 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
254 void r300_emit_rs_block_state(struct r300_context* r300,
255 struct r300_rs_block* rs)
258 struct r300_screen* r300screen = r300_screen(r300->context.screen);
262 if (r300screen->caps->is_r500) {
263 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
265 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
267 for (i = 0; i < 8; i++) {
269 /* debug_printf("ip %d: 0x%08x\n", i, rs->ip[i]); */
272 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
274 OUT_CS(rs->inst_count);
276 if (r300screen->caps->is_r500) {
277 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
279 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
281 for (i = 0; i < 8; i++) {
283 /* debug_printf("inst %d: 0x%08x\n", i, rs->inst[i]); */
286 /* debug_printf("count: 0x%08x inst_count: 0x%08x\n", rs->count,
287 * rs->inst_count); */
292 void r300_emit_scissor_state(struct r300_context* r300,
293 struct r300_scissor_state* scissor)
298 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
299 OUT_CS(scissor->scissor_top_left);
300 OUT_CS(scissor->scissor_bottom_right);
304 void r300_emit_texture(struct r300_context* r300,
305 struct r300_sampler_state* sampler,
306 struct r300_texture* tex,
312 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), sampler->filter0);
313 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
314 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
316 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), tex->state.format0);
317 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
318 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
319 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
320 OUT_CS_RELOC(tex->buffer, 0,
321 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
325 void r300_emit_vertex_buffer(struct r300_context* r300)
329 debug_printf("r300: Preparing vertex buffer %p for render, "
330 "vertex size %d\n", r300->vbo,
331 r300->vertex_info.vinfo.size);
332 /* Set the pointer to our vertex buffer. The emitted values are this:
333 * PACKET3 [3D_LOAD_VBPNTR]
335 * FORMAT [size | stride << 8]
336 * OFFSET [offset into BO]
337 * VBPNTR [relocated BO]
340 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
342 OUT_CS(r300->vertex_info.vinfo.size |
343 (r300->vertex_info.vinfo.size << 8));
344 OUT_CS(r300->vbo_offset);
345 OUT_CS_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
349 void r300_emit_vertex_format_state(struct r300_context* r300)
355 OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info.vinfo.size);
357 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
358 OUT_CS(r300->vertex_info.vinfo.hwfmt[0]);
359 OUT_CS(r300->vertex_info.vinfo.hwfmt[1]);
360 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
361 OUT_CS(r300->vertex_info.vinfo.hwfmt[2]);
362 OUT_CS(r300->vertex_info.vinfo.hwfmt[3]);
363 /* for (i = 0; i < 4; i++) {
364 * debug_printf("hwfmt%d: 0x%08x\n", i,
365 * r300->vertex_info.vinfo.hwfmt[i]);
368 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
369 for (i = 0; i < 8; i++) {
370 OUT_CS(r300->vertex_info.vap_prog_stream_cntl[i]);
371 /* debug_printf("prog_stream_cntl%d: 0x%08x\n", i,
372 * r300->vertex_info.vap_prog_stream_cntl[i]); */
374 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
375 for (i = 0; i < 8; i++) {
376 OUT_CS(r300->vertex_info.vap_prog_stream_cntl_ext[i]);
377 /* debug_printf("prog_stream_cntl_ext%d: 0x%08x\n", i,
378 * r300->vertex_info.vap_prog_stream_cntl_ext[i]); */
383 void r300_emit_vertex_shader(struct r300_context* r300,
384 struct r300_vertex_shader* vs)
387 struct r300_screen* r300screen = r300_screen(r300->context.screen);
388 struct r300_constant_buffer* constants =
389 &r300->shader_constants[PIPE_SHADER_VERTEX];
392 if (!r300screen->caps->has_tcl) {
393 debug_printf("r300: Implementation error: emit_vertex_shader called,"
394 " but has_tcl is FALSE!\n");
398 if (constants->count) {
399 BEGIN_CS(14 + (vs->instruction_count * 4) + (constants->count * 4));
401 BEGIN_CS(11 + (vs->instruction_count * 4));
404 /* R300_VAP_PVS_CODE_CNTL_0
405 * R300_VAP_PVS_CONST_CNTL
406 * R300_VAP_PVS_CODE_CNTL_1
407 * See the r5xx docs for instructions on how to use these.
408 * XXX these could be optimized to select better values... */
409 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
410 OUT_CS(R300_PVS_FIRST_INST(0) |
411 R300_PVS_XYZW_VALID_INST(vs->instruction_count - 1) |
412 R300_PVS_LAST_INST(vs->instruction_count - 1));
413 OUT_CS(R300_PVS_MAX_CONST_ADDR(constants->count - 1));
414 OUT_CS(vs->instruction_count - 1);
416 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
417 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, vs->instruction_count * 4);
418 for (i = 0; i < vs->instruction_count; i++) {
419 OUT_CS(vs->instructions[i].inst0);
420 OUT_CS(vs->instructions[i].inst1);
421 OUT_CS(vs->instructions[i].inst2);
422 OUT_CS(vs->instructions[i].inst3);
425 if (constants->count) {
426 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
427 (r300screen->caps->is_r500 ?
428 R500_PVS_CONST_START : R300_PVS_CONST_START));
429 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->count * 4);
430 for (i = 0; i < constants->count; i++) {
431 OUT_CS_32F(constants->constants[i][0]);
432 OUT_CS_32F(constants->constants[i][1]);
433 OUT_CS_32F(constants->constants[i][2]);
434 OUT_CS_32F(constants->constants[i][3]);
438 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(10) |
439 R300_PVS_NUM_CNTLRS(5) |
440 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
441 R300_PVS_VF_MAX_VTX_NUM(12));
442 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
446 void r300_emit_viewport_state(struct r300_context* r300,
447 struct r300_viewport_state* viewport)
452 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
453 OUT_CS_32F(viewport->xscale);
454 OUT_CS_32F(viewport->xoffset);
455 OUT_CS_32F(viewport->yscale);
456 OUT_CS_32F(viewport->yoffset);
457 OUT_CS_32F(viewport->zscale);
458 OUT_CS_32F(viewport->zoffset);
460 if (r300->rs_state->enable_vte) {
461 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
463 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
468 void r300_flush_textures(struct r300_context* r300)
473 OUT_CS_REG(R300_TX_INVALTAGS, 0);
474 OUT_CS_REG(R300_TX_ENABLE, (1 << r300->texture_count) - 1);
478 /* Emit all dirty state. */
479 void r300_emit_dirty_state(struct r300_context* r300)
481 struct r300_screen* r300screen = r300_screen(r300->context.screen);
482 struct r300_texture* tex;
483 int i, dirty_tex = 0;
484 boolean invalid = FALSE;
486 if (!(r300->dirty_state)) {
490 r300_update_derived_state(r300);
494 /* Color buffers... */
495 for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
496 tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
497 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
498 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
499 0, RADEON_GEM_DOMAIN_VRAM)) {
500 r300->context.flush(&r300->context, 0, NULL);
504 /* ...depth buffer... */
505 if (r300->framebuffer_state.zsbuf) {
506 tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
507 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
508 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
509 0, RADEON_GEM_DOMAIN_VRAM)) {
510 r300->context.flush(&r300->context, 0, NULL);
515 for (i = 0; i < r300->texture_count; i++) {
516 tex = r300->textures[i];
517 assert(tex && tex->buffer && "texture is marked, but NULL!");
518 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
519 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
520 r300->context.flush(&r300->context, 0, NULL);
524 /* ...and vertex buffer. */
526 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
527 RADEON_GEM_DOMAIN_GTT, 0)) {
528 r300->context.flush(&r300->context, 0, NULL);
532 debug_printf("No VBO while emitting dirty state!\n");
534 if (r300->winsys->validate(r300->winsys)) {
535 r300->context.flush(&r300->context, 0, NULL);
544 if (r300->dirty_state & R300_NEW_BLEND) {
545 r300_emit_blend_state(r300, r300->blend_state);
546 r300->dirty_state &= ~R300_NEW_BLEND;
549 if (r300->dirty_state & R300_NEW_BLEND_COLOR) {
550 r300_emit_blend_color_state(r300, r300->blend_color_state);
551 r300->dirty_state &= ~R300_NEW_BLEND_COLOR;
554 if (r300->dirty_state & R300_NEW_CLIP) {
555 r300_emit_clip_state(r300, &r300->clip_state);
556 r300->dirty_state &= ~R300_NEW_CLIP;
559 if (r300->dirty_state & R300_NEW_DSA) {
560 r300_emit_dsa_state(r300, r300->dsa_state);
561 r300->dirty_state &= ~R300_NEW_DSA;
564 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
565 if (r300screen->caps->is_r500) {
566 r500_emit_fragment_shader(r300,
567 (struct r5xx_fragment_shader*)r300->fs);
569 r300_emit_fragment_shader(r300,
570 (struct r3xx_fragment_shader*)r300->fs);
572 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
575 if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
576 r300_emit_fb_state(r300, &r300->framebuffer_state);
577 r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
580 if (r300->dirty_state & R300_NEW_RASTERIZER) {
581 r300_emit_rs_state(r300, r300->rs_state);
582 r300->dirty_state &= ~R300_NEW_RASTERIZER;
585 if (r300->dirty_state & R300_NEW_RS_BLOCK) {
586 r300_emit_rs_block_state(r300, r300->rs_block);
587 r300->dirty_state &= ~R300_NEW_RS_BLOCK;
590 if (r300->dirty_state & R300_NEW_SCISSOR) {
591 r300_emit_scissor_state(r300, r300->scissor_state);
592 r300->dirty_state &= ~R300_NEW_SCISSOR;
595 /* Samplers and textures are tracked separately but emitted together. */
596 if (r300->dirty_state &
597 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
598 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
599 if (r300->dirty_state &
600 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
601 r300_emit_texture(r300,
602 r300->sampler_states[i],
606 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
610 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
613 if (r300->dirty_state & R300_NEW_VIEWPORT) {
614 r300_emit_viewport_state(r300, r300->viewport_state);
615 r300->dirty_state &= ~R300_NEW_VIEWPORT;
619 r300_flush_textures(r300);
622 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
623 r300_emit_vertex_format_state(r300);
624 r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
627 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
628 r300_emit_vertex_shader(r300, r300->vs);
629 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
633 assert(r300->dirty_state == 0);
636 /* Finally, emit the VBO. */
637 r300_emit_vertex_buffer(r300);