src/gallium/drivers/r300/compiler/radeon_program_alu.c

   1 /*
   2  * Copyright (C) 2008 Nicolai Haehnle.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /**
  29  * @file
  30  *
  31  * Shareable transformations that transform "special" ALU instructions
  32  * into ALU instructions that are supported by hardware.
  33  *
  34  */
  35
  36 #include "radeon_program_alu.h"
  37
  38 #include "radeon_compiler.h"
  39 #include "radeon_compiler_util.h"
  40
  41 #include "util/log.h"
  42
  43 static struct rc_instruction *emit1(
  44         struct radeon_compiler * c, struct rc_instruction * after,
  45         rc_opcode Opcode, struct rc_sub_instruction * base,
  46         struct rc_dst_register DstReg, struct rc_src_register SrcReg)
  47 {
  48         struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
  49
  50         if (base) {
  51                 memcpy(&fpi->U.I, base, sizeof(struct rc_sub_instruction));
  52         }
  53
  54         fpi->U.I.Opcode = Opcode;
  55         fpi->U.I.DstReg = DstReg;
  56         fpi->U.I.SrcReg[0] = SrcReg;
  57         return fpi;
  58 }
  59
  60 static struct rc_instruction *emit2(
  61         struct radeon_compiler * c, struct rc_instruction * after,
  62         rc_opcode Opcode, struct rc_sub_instruction * base,
  63         struct rc_dst_register DstReg,
  64         struct rc_src_register SrcReg0, struct rc_src_register SrcReg1)
  65 {
  66         struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
  67
  68         if (base) {
  69                 memcpy(&fpi->U.I, base, sizeof(struct rc_sub_instruction));
  70         }
  71
  72         fpi->U.I.Opcode = Opcode;
  73         fpi->U.I.DstReg = DstReg;
  74         fpi->U.I.SrcReg[0] = SrcReg0;
  75         fpi->U.I.SrcReg[1] = SrcReg1;
  76         return fpi;
  77 }
  78
  79 static struct rc_instruction *emit3(
  80         struct radeon_compiler * c, struct rc_instruction * after,
  81         rc_opcode Opcode, struct rc_sub_instruction * base,
  82         struct rc_dst_register DstReg,
  83         struct rc_src_register SrcReg0, struct rc_src_register SrcReg1,
  84         struct rc_src_register SrcReg2)
  85 {
  86         struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
  87
  88         if (base) {
  89                 memcpy(&fpi->U.I, base, sizeof(struct rc_sub_instruction));
  90         }
  91
  92         fpi->U.I.Opcode = Opcode;
  93         fpi->U.I.DstReg = DstReg;
  94         fpi->U.I.SrcReg[0] = SrcReg0;
  95         fpi->U.I.SrcReg[1] = SrcReg1;
  96         fpi->U.I.SrcReg[2] = SrcReg2;
  97         return fpi;
  98 }
  99
 100 static struct rc_dst_register dstregtmpmask(int index, int mask)
 101 {
 102         struct rc_dst_register dst = {0, 0, 0};
 103         dst.File = RC_FILE_TEMPORARY;
 104         dst.Index = index;
 105         dst.WriteMask = mask;
 106         return dst;
 107 }
 108
 109 static const struct rc_src_register builtin_zero = {
 110         .File = RC_FILE_NONE,
 111         .Index = 0,
 112         .Swizzle = RC_SWIZZLE_0000
 113 };
 114 static const struct rc_src_register builtin_one = {
 115         .File = RC_FILE_NONE,
 116         .Index = 0,
 117         .Swizzle = RC_SWIZZLE_1111
 118 };
 119
 120 static const struct rc_src_register builtin_half = {
 121         .File = RC_FILE_NONE,
 122         .Index = 0,
 123         .Swizzle = RC_SWIZZLE_HHHH
 124 };
 125
 126 static const struct rc_src_register srcreg_undefined = {
 127         .File = RC_FILE_NONE,
 128         .Index = 0,
 129         .Swizzle = RC_SWIZZLE_XYZW
 130 };
 131
 132 static struct rc_src_register srcreg(int file, int index)
 133 {
 134         struct rc_src_register src = srcreg_undefined;
 135         src.File = file;
 136         src.Index = index;
 137         return src;
 138 }
 139
 140 static struct rc_src_register srcregswz(int file, int index, int swz)
 141 {
 142         struct rc_src_register src = srcreg_undefined;
 143         src.File = file;
 144         src.Index = index;
 145         src.Swizzle = swz;
 146         return src;
 147 }
 148
 149 static struct rc_src_register absolute(struct rc_src_register reg)
 150 {
 151         struct rc_src_register newreg = reg;
 152         newreg.Abs = 1;
 153         newreg.Negate = RC_MASK_NONE;
 154         return newreg;
 155 }
 156
 157 static struct rc_src_register negate(struct rc_src_register reg)
 158 {
 159         struct rc_src_register newreg = reg;
 160         newreg.Negate = newreg.Negate ^ RC_MASK_XYZW;
 161         return newreg;
 162 }
 163
 164 static struct rc_src_register swizzle(struct rc_src_register reg,
 165                 rc_swizzle x, rc_swizzle y, rc_swizzle z, rc_swizzle w)
 166 {
 167         struct rc_src_register swizzled = reg;
 168         swizzled.Swizzle = combine_swizzles4(reg.Swizzle, x, y, z, w);
 169         return swizzled;
 170 }
 171
 172 static struct rc_src_register swizzle_smear(struct rc_src_register reg,
 173                 rc_swizzle x)
 174 {
 175         return swizzle(reg, x, x, x, x);
 176 }
 177
 178 static struct rc_src_register swizzle_xxxx(struct rc_src_register reg)
 179 {
 180         return swizzle_smear(reg, RC_SWIZZLE_X);
 181 }
 182
 183 static struct rc_src_register swizzle_yyyy(struct rc_src_register reg)
 184 {
 185         return swizzle_smear(reg, RC_SWIZZLE_Y);
 186 }
 187
 188 static struct rc_src_register swizzle_zzzz(struct rc_src_register reg)
 189 {
 190         return swizzle_smear(reg, RC_SWIZZLE_Z);
 191 }
 192
 193 static struct rc_src_register swizzle_wwww(struct rc_src_register reg)
 194 {
 195         return swizzle_smear(reg, RC_SWIZZLE_W);
 196 }
 197
 198 static int is_dst_safe_to_reuse(struct rc_instruction *inst)
 199 {
 200         const struct rc_opcode_info *info = rc_get_opcode_info(inst->U.I.Opcode);
 201         unsigned i;
 202
 203         assert(info->HasDstReg);
 204
 205         if (inst->U.I.DstReg.File != RC_FILE_TEMPORARY)
 206                 return 0;
 207
 208         for (i = 0; i < info->NumSrcRegs; i++) {
 209                 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY &&
 210                     inst->U.I.SrcReg[i].Index == inst->U.I.DstReg.Index)
 211                         return 0;
 212         }
 213
 214         return 1;
 215 }
 216
 217 static struct rc_dst_register try_to_reuse_dst(struct radeon_compiler *c,
 218                                                struct rc_instruction *inst)
 219 {
 220         unsigned tmp;
 221
 222         if (is_dst_safe_to_reuse(inst))
 223                 tmp = inst->U.I.DstReg.Index;
 224         else
 225                 tmp = rc_find_free_temporary(c);
 226
 227         return dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask);
 228 }
 229
 230 static void transform_CEIL(struct radeon_compiler* c,
 231         struct rc_instruction* inst)
 232 {
 233         /* Assuming:
 234          *     ceil(x) = -floor(-x)
 235          *
 236          * After inlining floor:
 237          *     ceil(x) = -(-x-frac(-x))
 238          *
 239          * After simplification:
 240          *     ceil(x) = x+frac(-x)
 241          */
 242
 243         struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 244         emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dst, negate(inst->U.I.SrcReg[0]));
 245         emit2(c, inst->Prev, RC_OPCODE_ADD, &inst->U.I, inst->U.I.DstReg,
 246                 inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, dst.Index));
 247         rc_remove_instruction(inst);
 248 }
 249
 250 static void transform_DP2(struct radeon_compiler* c,
 251         struct rc_instruction* inst)
 252 {
 253         struct rc_src_register src0 = inst->U.I.SrcReg[0];
 254         struct rc_src_register src1 = inst->U.I.SrcReg[1];
 255         src0.Negate &= ~(RC_MASK_Z | RC_MASK_W);
 256         src0.Swizzle &= ~(63 << (3 * 2));
 257         src0.Swizzle |= (RC_SWIZZLE_ZERO << (3 * 2)) | (RC_SWIZZLE_ZERO << (3 * 3));
 258         src1.Negate &= ~(RC_MASK_Z | RC_MASK_W);
 259         src1.Swizzle &= ~(63 << (3 * 2));
 260         src1.Swizzle |= (RC_SWIZZLE_ZERO << (3 * 2)) | (RC_SWIZZLE_ZERO << (3 * 3));
 261         emit2(c, inst->Prev, RC_OPCODE_DP3, &inst->U.I, inst->U.I.DstReg, src0, src1);
 262         rc_remove_instruction(inst);
 263 }
 264
 265 /**
 266  * [1, src0.y*src1.y, src0.z, src1.w]
 267  * So basically MUL with lotsa swizzling.
 268  */
 269 static void transform_DST(struct radeon_compiler* c,
 270         struct rc_instruction* inst)
 271 {
 272         emit2(c, inst->Prev, RC_OPCODE_MUL, &inst->U.I, inst->U.I.DstReg,
 273                 swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ONE),
 274                 swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_ONE, RC_SWIZZLE_W));
 275         rc_remove_instruction(inst);
 276 }
 277
 278 static void transform_FLR(struct radeon_compiler* c,
 279         struct rc_instruction* inst)
 280 {
 281         struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 282         emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dst, inst->U.I.SrcReg[0]);
 283         emit2(c, inst->Prev, RC_OPCODE_ADD, &inst->U.I, inst->U.I.DstReg,
 284                 inst->U.I.SrcReg[0], negate(srcreg(RC_FILE_TEMPORARY, dst.Index)));
 285         rc_remove_instruction(inst);
 286 }
 287
 288 static void transform_TRUNC(struct radeon_compiler* c,
 289         struct rc_instruction* inst)
 290 {
 291         /* Definition of trunc:
 292          *   trunc(x) = (abs(x) - fract(abs(x))) * sgn(x)
 293          *
 294          * The multiplication by sgn(x) can be simplified using CMP:
 295          *   y * sgn(x) = (x < 0 ? -y : y)
 296          */
 297         struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 298         emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dst, absolute(inst->U.I.SrcReg[0]));
 299         emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, absolute(inst->U.I.SrcReg[0]),
 300               negate(srcreg(RC_FILE_TEMPORARY, dst.Index)));
 301         emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg, inst->U.I.SrcReg[0],
 302               negate(srcreg(RC_FILE_TEMPORARY, dst.Index)), srcreg(RC_FILE_TEMPORARY, dst.Index));
 303         rc_remove_instruction(inst);
 304 }
 305
 306 /**
 307  * Definition of LIT (from ARB_fragment_program):
 308  *
 309  *  tmp = VectorLoad(op0);
 310  *  if (tmp.x < 0) tmp.x = 0;
 311  *  if (tmp.y < 0) tmp.y = 0;
 312  *  if (tmp.w < -(128.0-epsilon)) tmp.w = -(128.0-epsilon);
 313  *  else if (tmp.w > 128-epsilon) tmp.w = 128-epsilon;
 314  *  result.x = 1.0;
 315  *  result.y = tmp.x;
 316  *  result.z = (tmp.x > 0) ? RoughApproxPower(tmp.y, tmp.w) : 0.0;
 317  *  result.w = 1.0;
 318  *
 319  * The longest path of computation is the one leading to result.z,
 320  * consisting of 5 operations. This implementation of LIT takes
 321  * 5 slots, if the subsequent optimization passes are clever enough
 322  * to pair instructions correctly.
 323  */
 324 static void transform_LIT(struct radeon_compiler* c,
 325         struct rc_instruction* inst)
 326 {
 327         unsigned int constant;
 328         unsigned int constant_swizzle;
 329         unsigned int temp;
 330         struct rc_src_register srctemp;
 331
 332         constant = rc_constants_add_immediate_scalar(&c->Program.Constants, -127.999999, &constant_swizzle);
 333
 334         if (inst->U.I.DstReg.WriteMask != RC_MASK_XYZW || inst->U.I.DstReg.File != RC_FILE_TEMPORARY) {
 335                 struct rc_instruction * inst_mov;
 336
 337                 inst_mov = emit1(c, inst,
 338                         RC_OPCODE_MOV, NULL, inst->U.I.DstReg,
 339                         srcreg(RC_FILE_TEMPORARY, rc_find_free_temporary(c)));
 340
 341                 inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
 342                 inst->U.I.DstReg.Index = inst_mov->U.I.SrcReg[0].Index;
 343                 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
 344         }
 345
 346         temp = inst->U.I.DstReg.Index;
 347         srctemp = srcreg(RC_FILE_TEMPORARY, temp);
 348
 349         /* tmp.x = max(0.0, Src.x); */
 350         /* tmp.y = max(0.0, Src.y); */
 351         /* tmp.w = clamp(Src.z, -128+eps, 128-eps); */
 352         emit2(c, inst->Prev, RC_OPCODE_MAX, NULL,
 353                 dstregtmpmask(temp, RC_MASK_XYW),
 354                 inst->U.I.SrcReg[0],
 355                 swizzle(srcreg(RC_FILE_CONSTANT, constant),
 356                         RC_SWIZZLE_ZERO, RC_SWIZZLE_ZERO, RC_SWIZZLE_ZERO, constant_swizzle&3));
 357         emit2(c, inst->Prev, RC_OPCODE_MIN, NULL,
 358                 dstregtmpmask(temp, RC_MASK_Z),
 359                 swizzle_wwww(srctemp),
 360                 negate(srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle)));
 361
 362         /* tmp.w = Pow(tmp.y, tmp.w) */
 363         emit1(c, inst->Prev, RC_OPCODE_LG2, NULL,
 364                 dstregtmpmask(temp, RC_MASK_W),
 365                 swizzle_yyyy(srctemp));
 366         emit2(c, inst->Prev, RC_OPCODE_MUL, NULL,
 367                 dstregtmpmask(temp, RC_MASK_W),
 368                 swizzle_wwww(srctemp),
 369                 swizzle_zzzz(srctemp));
 370         emit1(c, inst->Prev, RC_OPCODE_EX2, NULL,
 371                 dstregtmpmask(temp, RC_MASK_W),
 372                 swizzle_wwww(srctemp));
 373
 374         /* tmp.z = (tmp.x > 0) ? tmp.w : 0.0 */
 375         emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I,
 376                 dstregtmpmask(temp, RC_MASK_Z),
 377                 negate(swizzle_xxxx(srctemp)),
 378                 swizzle_wwww(srctemp),
 379                 builtin_zero);
 380
 381         /* tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0 */
 382         emit1(c, inst->Prev, RC_OPCODE_MOV, &inst->U.I,
 383                 dstregtmpmask(temp, RC_MASK_XYW),
 384                 swizzle(srctemp, RC_SWIZZLE_ONE, RC_SWIZZLE_X, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE));
 385
 386         rc_remove_instruction(inst);
 387 }
 388
 389 static void transform_LRP(struct radeon_compiler* c,
 390         struct rc_instruction* inst)
 391 {
 392         struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 393
 394         emit3(c, inst->Prev, RC_OPCODE_MAD, NULL,
 395                 dst,
 396                 negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[2], inst->U.I.SrcReg[2]);
 397         emit3(c, inst->Prev, RC_OPCODE_MAD, &inst->U.I,
 398                 inst->U.I.DstReg,
 399                 inst->U.I.SrcReg[0], inst->U.I.SrcReg[1], srcreg(RC_FILE_TEMPORARY, dst.Index));
 400
 401         rc_remove_instruction(inst);
 402 }
 403
 404 static void transform_POW(struct radeon_compiler* c,
 405         struct rc_instruction* inst)
 406 {
 407         struct rc_dst_register tempdst = try_to_reuse_dst(c, inst);
 408         struct rc_src_register tempsrc = srcreg(RC_FILE_TEMPORARY, tempdst.Index);
 409         tempdst.WriteMask = RC_MASK_W;
 410         tempsrc.Swizzle = RC_SWIZZLE_WWWW;
 411
 412         emit1(c, inst->Prev, RC_OPCODE_LG2, NULL, tempdst, swizzle_xxxx(inst->U.I.SrcReg[0]));
 413         emit2(c, inst->Prev, RC_OPCODE_MUL, NULL, tempdst, tempsrc, swizzle_xxxx(inst->U.I.SrcReg[1]));
 414         emit1(c, inst->Prev, RC_OPCODE_EX2, &inst->U.I, inst->U.I.DstReg, tempsrc);
 415
 416         rc_remove_instruction(inst);
 417 }
 418
 419 /* dst = ROUND(src) :
 420  *   add = src + .5
 421  *   frac = FRC(add)
 422  *   dst = add - frac
 423  *
 424  * According to the GLSL spec, the implementor can decide which way to round
 425  * when the fraction is .5.  We round down for .5.
 426  *
 427  */
 428 static void transform_ROUND(struct radeon_compiler* c,
 429         struct rc_instruction* inst)
 430 {
 431         unsigned int mask = inst->U.I.DstReg.WriteMask;
 432         unsigned int frac_index, add_index;
 433         struct rc_dst_register frac_dst, add_dst;
 434         struct rc_src_register frac_src, add_src;
 435
 436         /* add = src + .5 */
 437         add_index = rc_find_free_temporary(c);
 438         add_dst = dstregtmpmask(add_index, mask);
 439         emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, add_dst, inst->U.I.SrcReg[0],
 440                                                                 builtin_half);
 441         add_src = srcreg(RC_FILE_TEMPORARY, add_dst.Index);
 442
 443
 444         /* frac = FRC(add) */
 445         frac_index = rc_find_free_temporary(c);
 446         frac_dst = dstregtmpmask(frac_index, mask);
 447         emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, frac_dst, add_src);
 448         frac_src = srcreg(RC_FILE_TEMPORARY, frac_dst.Index);
 449
 450         /* dst = add - frac */
 451         emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, inst->U.I.DstReg,
 452                                                 add_src, negate(frac_src));
 453         rc_remove_instruction(inst);
 454 }
 455
 456 static void transform_RSQ(struct radeon_compiler* c,
 457         struct rc_instruction* inst)
 458 {
 459         inst->U.I.SrcReg[0] = absolute(inst->U.I.SrcReg[0]);
 460 }
 461
 462 static void transform_SEQ(struct radeon_compiler* c,
 463         struct rc_instruction* inst)
 464 {
 465         struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 466
 467         emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 468         emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
 469                 negate(absolute(srcreg(RC_FILE_TEMPORARY, dst.Index))), builtin_zero, builtin_one);
 470
 471         rc_remove_instruction(inst);
 472 }
 473
 474 static void transform_SGE(struct radeon_compiler* c,
 475         struct rc_instruction* inst)
 476 {
 477         struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 478
 479         emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 480         emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
 481                 srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_zero, builtin_one);
 482
 483         rc_remove_instruction(inst);
 484 }
 485
 486 static void transform_SGT(struct radeon_compiler* c,
 487         struct rc_instruction* inst)
 488 {
 489         struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 490
 491         emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
 492         emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
 493                 srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_one, builtin_zero);
 494
 495         rc_remove_instruction(inst);
 496 }
 497
 498 static void transform_SLE(struct radeon_compiler* c,
 499         struct rc_instruction* inst)
 500 {
 501         struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 502
 503         emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
 504         emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
 505                 srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_zero, builtin_one);
 506
 507         rc_remove_instruction(inst);
 508 }
 509
 510 static void transform_SLT(struct radeon_compiler* c,
 511         struct rc_instruction* inst)
 512 {
 513         struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 514
 515         emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 516         emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
 517                 srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_one, builtin_zero);
 518
 519         rc_remove_instruction(inst);
 520 }
 521
 522 static void transform_SNE(struct radeon_compiler* c,
 523         struct rc_instruction* inst)
 524 {
 525         struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 526
 527         emit2(c, inst->Prev, RC_OPCODE_ADD, NULL, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 528         emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
 529                 negate(absolute(srcreg(RC_FILE_TEMPORARY, dst.Index))), builtin_one, builtin_zero);
 530
 531         rc_remove_instruction(inst);
 532 }
 533
 534 static void transform_SSG(struct radeon_compiler* c,
 535         struct rc_instruction* inst)
 536 {
 537         /* result = sign(x)
 538          *
 539          *   CMP tmp0, -x, 1, 0
 540          *   CMP tmp1, x, 1, 0
 541          *   ADD result, tmp0, -tmp1;
 542          */
 543         struct rc_dst_register dst0;
 544         unsigned tmp1;
 545
 546         /* 0 < x */
 547         dst0 = try_to_reuse_dst(c, inst);
 548         emit3(c, inst->Prev, RC_OPCODE_CMP, NULL,
 549               dst0,
 550               negate(inst->U.I.SrcReg[0]),
 551               builtin_one,
 552               builtin_zero);
 553
 554         /* x < 0 */
 555         tmp1 = rc_find_free_temporary(c);
 556         emit3(c, inst->Prev, RC_OPCODE_CMP, NULL,
 557               dstregtmpmask(tmp1, inst->U.I.DstReg.WriteMask),
 558               inst->U.I.SrcReg[0],
 559               builtin_one,
 560               builtin_zero);
 561
 562         /* Either both are zero, or one of them is one and the other is zero. */
 563         /* result = tmp0 - tmp1 */
 564         emit2(c, inst->Prev, RC_OPCODE_ADD, NULL,
 565               inst->U.I.DstReg,
 566               srcreg(RC_FILE_TEMPORARY, dst0.Index),
 567               negate(srcreg(RC_FILE_TEMPORARY, tmp1)));
 568
 569         rc_remove_instruction(inst);
 570 }
 571
 572 static void transform_SUB(struct radeon_compiler* c,
 573         struct rc_instruction* inst)
 574 {
 575         inst->U.I.Opcode = RC_OPCODE_ADD;
 576         inst->U.I.SrcReg[1] = negate(inst->U.I.SrcReg[1]);
 577 }
 578
 579 /**
 580  * Can be used as a transformation for @ref radeonClauseLocalTransform,
 581  * no userData necessary.
 582  *
 583  * Eliminates the following ALU instructions:
 584  *  CEIL, DST, FLR, LIT, LRP, POW, SEQ, SGE, SGT, SLE, SLT, SNE, SUB
 585  * using:
 586  *  MOV, ADD, MUL, MAD, FRC, DP3, LG2, EX2, CMP
 587  *
 588  * Transforms RSQ to Radeon's native RSQ by explicitly setting
 589  * absolute value.
 590  *
 591  * @note should be applicable to R300 and R500 fragment programs.
 592  */
 593 int radeonTransformALU(
 594         struct radeon_compiler * c,
 595         struct rc_instruction* inst,
 596         void* unused)
 597 {
 598         switch(inst->U.I.Opcode) {
 599         case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
 600         case RC_OPCODE_DP2: transform_DP2(c, inst); return 1;
 601         case RC_OPCODE_DST: transform_DST(c, inst); return 1;
 602         case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
 603         case RC_OPCODE_LIT: transform_LIT(c, inst); return 1;
 604         case RC_OPCODE_LRP: transform_LRP(c, inst); return 1;
 605         case RC_OPCODE_POW: transform_POW(c, inst); return 1;
 606         case RC_OPCODE_ROUND: transform_ROUND(c, inst); return 1;
 607         case RC_OPCODE_RSQ: transform_RSQ(c, inst); return 1;
 608         case RC_OPCODE_SEQ: transform_SEQ(c, inst); return 1;
 609         case RC_OPCODE_SGE: transform_SGE(c, inst); return 1;
 610         case RC_OPCODE_SGT: transform_SGT(c, inst); return 1;
 611         case RC_OPCODE_SLE: transform_SLE(c, inst); return 1;
 612         case RC_OPCODE_SLT: transform_SLT(c, inst); return 1;
 613         case RC_OPCODE_SNE: transform_SNE(c, inst); return 1;
 614         case RC_OPCODE_SSG: transform_SSG(c, inst); return 1;
 615         case RC_OPCODE_SUB: transform_SUB(c, inst); return 1;
 616         case RC_OPCODE_TRUNC: transform_TRUNC(c, inst); return 1;
 617         default:
 618                 return 0;
 619         }
 620 }
 621
 622 static void transform_r300_vertex_CMP(struct radeon_compiler* c,
 623         struct rc_instruction* inst)
 624 {
 625         /* There is no decent CMP available, so let's rig one up.
 626          * CMP is defined as dst = src0 < 0.0 ? src1 : src2
 627          * The following sequence consumes zero to two temps and two extra slots
 628          * (the second temp and the second slot is consumed by transform_LRP),
 629          * but should be equivalent:
 630          *
 631          * SLT tmp0, src0, 0.0
 632          * LRP dst, tmp0, src1, src2
 633          *
 634          * Yes, I know, I'm a mad scientist. ~ C. & M. */
 635         struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 636
 637         /* SLT tmp0, src0, 0.0 */
 638         emit2(c, inst->Prev, RC_OPCODE_SLT, NULL,
 639                 dst,
 640                 inst->U.I.SrcReg[0], builtin_zero);
 641
 642         /* LRP dst, tmp0, src1, src2 */
 643         transform_LRP(c,
 644                 emit3(c, inst->Prev, RC_OPCODE_LRP, NULL,
 645                       inst->U.I.DstReg,
 646                       srcreg(RC_FILE_TEMPORARY, dst.Index), inst->U.I.SrcReg[1],  inst->U.I.SrcReg[2]));
 647
 648         rc_remove_instruction(inst);
 649 }
 650
 651 static void transform_r300_vertex_DP2(struct radeon_compiler* c,
 652         struct rc_instruction* inst)
 653 {
 654         struct rc_instruction *next_inst = inst->Next;
 655         transform_DP2(c, inst);
 656         next_inst->Prev->U.I.Opcode = RC_OPCODE_DP4;
 657 }
 658
 659 static void transform_r300_vertex_DP3(struct radeon_compiler* c,
 660         struct rc_instruction* inst)
 661 {
 662         struct rc_src_register src0 = inst->U.I.SrcReg[0];
 663         struct rc_src_register src1 = inst->U.I.SrcReg[1];
 664         src0.Negate &= ~RC_MASK_W;
 665         src0.Swizzle &= ~(7 << (3 * 3));
 666         src0.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
 667         src1.Negate &= ~RC_MASK_W;
 668         src1.Swizzle &= ~(7 << (3 * 3));
 669         src1.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
 670         emit2(c, inst->Prev, RC_OPCODE_DP4, &inst->U.I, inst->U.I.DstReg, src0, src1);
 671         rc_remove_instruction(inst);
 672 }
 673
 674 static void transform_r300_vertex_fix_LIT(struct radeon_compiler* c,
 675         struct rc_instruction* inst)
 676 {
 677         struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 678         unsigned constant_swizzle;
 679         int constant = rc_constants_add_immediate_scalar(&c->Program.Constants,
 680                                                          0.0000000000000000001,
 681                                                          &constant_swizzle);
 682
 683         /* MOV dst, src */
 684         dst.WriteMask = RC_MASK_XYZW;
 685         emit1(c, inst->Prev, RC_OPCODE_MOV, NULL,
 686                 dst,
 687                 inst->U.I.SrcReg[0]);
 688
 689         /* MAX dst.y, src, 0.00...001 */
 690         emit2(c, inst->Prev, RC_OPCODE_MAX, NULL,
 691                 dstregtmpmask(dst.Index, RC_MASK_Y),
 692                 srcreg(RC_FILE_TEMPORARY, dst.Index),
 693                 srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle));
 694
 695         inst->U.I.SrcReg[0] = srcreg(RC_FILE_TEMPORARY, dst.Index);
 696 }
 697
 698 static void transform_r300_vertex_SEQ(struct radeon_compiler *c,
 699         struct rc_instruction *inst)
 700 {
 701         /* x = y  <==>  x >= y && y >= x */
 702         int tmp = rc_find_free_temporary(c);
 703
 704         /* x <= y */
 705         emit2(c, inst->Prev, RC_OPCODE_SGE, NULL,
 706               dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask),
 707               inst->U.I.SrcReg[0],
 708               inst->U.I.SrcReg[1]);
 709
 710         /* y <= x */
 711         emit2(c, inst->Prev, RC_OPCODE_SGE, NULL,
 712               inst->U.I.DstReg,
 713               inst->U.I.SrcReg[1],
 714               inst->U.I.SrcReg[0]);
 715
 716         /* x && y  =  x * y */
 717         emit2(c, inst->Prev, RC_OPCODE_MUL, NULL,
 718               inst->U.I.DstReg,
 719               srcreg(RC_FILE_TEMPORARY, tmp),
 720               srcreg(inst->U.I.DstReg.File, inst->U.I.DstReg.Index));
 721
 722         rc_remove_instruction(inst);
 723 }
 724
 725 static void transform_r300_vertex_SNE(struct radeon_compiler *c,
 726         struct rc_instruction *inst)
 727 {
 728         /* x != y  <==>  x < y || y < x */
 729         int tmp = rc_find_free_temporary(c);
 730
 731         /* x < y */
 732         emit2(c, inst->Prev, RC_OPCODE_SLT, NULL,
 733               dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask),
 734               inst->U.I.SrcReg[0],
 735               inst->U.I.SrcReg[1]);
 736
 737         /* y < x */
 738         emit2(c, inst->Prev, RC_OPCODE_SLT, NULL,
 739               inst->U.I.DstReg,
 740               inst->U.I.SrcReg[1],
 741               inst->U.I.SrcReg[0]);
 742
 743         /* x || y  =  max(x, y) */
 744         emit2(c, inst->Prev, RC_OPCODE_MAX, NULL,
 745               inst->U.I.DstReg,
 746               srcreg(RC_FILE_TEMPORARY, tmp),
 747               srcreg(inst->U.I.DstReg.File, inst->U.I.DstReg.Index));
 748
 749         rc_remove_instruction(inst);
 750 }
 751
 752 static void transform_r300_vertex_SGT(struct radeon_compiler* c,
 753         struct rc_instruction* inst)
 754 {
 755         /* x > y  <==>  -x < -y */
 756         inst->U.I.Opcode = RC_OPCODE_SLT;
 757         inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW;
 758         inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
 759 }
 760
 761 static void transform_r300_vertex_SLE(struct radeon_compiler* c,
 762         struct rc_instruction* inst)
 763 {
 764         /* x <= y  <==>  -x >= -y */
 765         inst->U.I.Opcode = RC_OPCODE_SGE;
 766         inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW;
 767         inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
 768 }
 769
 770 static void transform_r300_vertex_SSG(struct radeon_compiler* c,
 771         struct rc_instruction* inst)
 772 {
 773         /* result = sign(x)
 774          *
 775          *   SLT tmp0, 0, x;
 776          *   SLT tmp1, x, 0;
 777          *   ADD result, tmp0, -tmp1;
 778          */
 779         struct rc_dst_register dst0;
 780         unsigned tmp1;
 781
 782         /* 0 < x */
 783         dst0 = try_to_reuse_dst(c, inst);
 784         emit2(c, inst->Prev, RC_OPCODE_SLT, NULL,
 785               dst0,
 786               builtin_zero,
 787               inst->U.I.SrcReg[0]);
 788
 789         /* x < 0 */
 790         tmp1 = rc_find_free_temporary(c);
 791         emit2(c, inst->Prev, RC_OPCODE_SLT, NULL,
 792               dstregtmpmask(tmp1, inst->U.I.DstReg.WriteMask),
 793               inst->U.I.SrcReg[0],
 794               builtin_zero);
 795
 796         /* Either both are zero, or one of them is one and the other is zero. */
 797         /* result = tmp0 - tmp1 */
 798         emit2(c, inst->Prev, RC_OPCODE_ADD, NULL,
 799               inst->U.I.DstReg,
 800               srcreg(RC_FILE_TEMPORARY, dst0.Index),
 801               negate(srcreg(RC_FILE_TEMPORARY, tmp1)));
 802
 803         rc_remove_instruction(inst);
 804 }
 805
 806 static void transform_vertex_TRUNC(struct radeon_compiler* c,
 807         struct rc_instruction* inst)
 808 {
 809         struct rc_instruction *next = inst->Next;
 810
 811         /* next->Prev is removed after each transformation and replaced
 812          * by a new instruction. */
 813         transform_TRUNC(c, next->Prev);
 814         transform_r300_vertex_CMP(c, next->Prev);
 815 }
 816
 817 /**
 818  * For use with rc_local_transform, this transforms non-native ALU
 819  * instructions of the r300 up to r500 vertex engine.
 820  */
 821 int r300_transform_vertex_alu(
 822         struct radeon_compiler * c,
 823         struct rc_instruction* inst,
 824         void* unused)
 825 {
 826         switch(inst->U.I.Opcode) {
 827         case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
 828         case RC_OPCODE_CMP: transform_r300_vertex_CMP(c, inst); return 1;
 829         case RC_OPCODE_DP2: transform_r300_vertex_DP2(c, inst); return 1;
 830         case RC_OPCODE_DP3: transform_r300_vertex_DP3(c, inst); return 1;
 831         case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
 832         case RC_OPCODE_LIT: transform_r300_vertex_fix_LIT(c, inst); return 1;
 833         case RC_OPCODE_LRP: transform_LRP(c, inst); return 1;
 834         case RC_OPCODE_SEQ:
 835                 if (!c->is_r500) {
 836                         transform_r300_vertex_SEQ(c, inst);
 837                         return 1;
 838                 }
 839                 return 0;
 840         case RC_OPCODE_SGT: transform_r300_vertex_SGT(c, inst); return 1;
 841         case RC_OPCODE_SLE: transform_r300_vertex_SLE(c, inst); return 1;
 842         case RC_OPCODE_SNE:
 843                 if (!c->is_r500) {
 844                         transform_r300_vertex_SNE(c, inst);
 845                         return 1;
 846                 }
 847                 return 0;
 848         case RC_OPCODE_SSG: transform_r300_vertex_SSG(c, inst); return 1;
 849         case RC_OPCODE_SUB: transform_SUB(c, inst); return 1;
 850         case RC_OPCODE_TRUNC: transform_vertex_TRUNC(c, inst); return 1;
 851         default:
 852                 return 0;
 853         }
 854 }
 855
 856 static void sincos_constants(struct radeon_compiler* c, unsigned int *constants)
 857 {
 858         static const float SinCosConsts[2][4] = {
 859                 {
 860                         1.273239545,            /* 4/PI */
 861                         -0.405284735,           /* -4/(PI*PI) */
 862                         3.141592654,            /* PI */
 863                         0.2225                  /* weight */
 864                 },
 865                 {
 866                         0.75,
 867                         0.5,
 868                         0.159154943,            /* 1/(2*PI) */
 869                         6.283185307             /* 2*PI */
 870                 }
 871         };
 872         int i;
 873
 874         for(i = 0; i < 2; ++i)
 875                 constants[i] = rc_constants_add_immediate_vec4(&c->Program.Constants, SinCosConsts[i]);
 876 }
 877
 878 /**
 879  * Approximate sin(x), where x is clamped to (-pi/2, pi/2).
 880  *
 881  * MUL tmp.xy, src, { 4/PI, -4/(PI^2) }
 882  * MAD tmp.x, tmp.y, |src|, tmp.x
 883  * MAD tmp.y, tmp.x, |tmp.x|, -tmp.x
 884  * MAD dest, tmp.y, weight, tmp.x
 885  */
 886 static void sin_approx(
 887         struct radeon_compiler* c, struct rc_instruction * inst,
 888         struct rc_dst_register dst, struct rc_src_register src, const unsigned int* constants)
 889 {
 890         unsigned int tempreg = rc_find_free_temporary(c);
 891
 892         emit2(c, inst->Prev, RC_OPCODE_MUL, NULL, dstregtmpmask(tempreg, RC_MASK_XY),
 893                 swizzle_xxxx(src),
 894                 srcreg(RC_FILE_CONSTANT, constants[0]));
 895         emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_X),
 896                 swizzle_yyyy(srcreg(RC_FILE_TEMPORARY, tempreg)),
 897                 absolute(swizzle_xxxx(src)),
 898                 swizzle_xxxx(srcreg(RC_FILE_TEMPORARY, tempreg)));
 899         emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_Y),
 900                 swizzle_xxxx(srcreg(RC_FILE_TEMPORARY, tempreg)),
 901                 absolute(swizzle_xxxx(srcreg(RC_FILE_TEMPORARY, tempreg))),
 902                 negate(swizzle_xxxx(srcreg(RC_FILE_TEMPORARY, tempreg))));
 903         emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dst,
 904                 swizzle_yyyy(srcreg(RC_FILE_TEMPORARY, tempreg)),
 905                 swizzle_wwww(srcreg(RC_FILE_CONSTANT, constants[0])),
 906                 swizzle_xxxx(srcreg(RC_FILE_TEMPORARY, tempreg)));
 907 }
 908
 909 /**
 910  * Translate the trigonometric functions COS and SIN
 911  * using only the basic instructions
 912  *  MOV, ADD, MUL, MAD, FRC
 913  */
 914 int r300_transform_trig_simple(struct radeon_compiler* c,
 915         struct rc_instruction* inst,
 916         void* unused)
 917 {
 918         unsigned int constants[2];
 919         unsigned int tempreg;
 920
 921         if (inst->U.I.Opcode != RC_OPCODE_COS &&
 922             inst->U.I.Opcode != RC_OPCODE_SIN)
 923                 return 0;
 924
 925         tempreg = rc_find_free_temporary(c);
 926
 927         sincos_constants(c, constants);
 928
 929         if (inst->U.I.Opcode == RC_OPCODE_COS) {
 930                 /* MAD tmp.x, src, 1/(2*PI), 0.75 */
 931                 /* FRC tmp.x, tmp.x */
 932                 /* MAD tmp.z, tmp.x, 2*PI, -PI */
 933                 emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_W),
 934                         swizzle_xxxx(inst->U.I.SrcReg[0]),
 935                         swizzle_zzzz(srcreg(RC_FILE_CONSTANT, constants[1])),
 936                         swizzle_xxxx(srcreg(RC_FILE_CONSTANT, constants[1])));
 937                 emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dstregtmpmask(tempreg, RC_MASK_W),
 938                         swizzle_wwww(srcreg(RC_FILE_TEMPORARY, tempreg)));
 939                 emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_W),
 940                         swizzle_wwww(srcreg(RC_FILE_TEMPORARY, tempreg)),
 941                         swizzle_wwww(srcreg(RC_FILE_CONSTANT, constants[1])),
 942                         negate(swizzle_zzzz(srcreg(RC_FILE_CONSTANT, constants[0]))));
 943
 944                 sin_approx(c, inst, inst->U.I.DstReg,
 945                         swizzle_wwww(srcreg(RC_FILE_TEMPORARY, tempreg)),
 946                         constants);
 947         } else if (inst->U.I.Opcode == RC_OPCODE_SIN) {
 948                 emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_W),
 949                         swizzle_xxxx(inst->U.I.SrcReg[0]),
 950                         swizzle_zzzz(srcreg(RC_FILE_CONSTANT, constants[1])),
 951                         swizzle_yyyy(srcreg(RC_FILE_CONSTANT, constants[1])));
 952                 emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dstregtmpmask(tempreg, RC_MASK_W),
 953                         swizzle_wwww(srcreg(RC_FILE_TEMPORARY, tempreg)));
 954                 emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_W),
 955                         swizzle_wwww(srcreg(RC_FILE_TEMPORARY, tempreg)),
 956                         swizzle_wwww(srcreg(RC_FILE_CONSTANT, constants[1])),
 957                         negate(swizzle_zzzz(srcreg(RC_FILE_CONSTANT, constants[0]))));
 958
 959                 sin_approx(c, inst, inst->U.I.DstReg,
 960                         swizzle_wwww(srcreg(RC_FILE_TEMPORARY, tempreg)),
 961                         constants);
 962         } else {
 963                 struct rc_dst_register dst;
 964
 965                 emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_XY),
 966                         swizzle_xxxx(inst->U.I.SrcReg[0]),
 967                         swizzle_zzzz(srcreg(RC_FILE_CONSTANT, constants[1])),
 968                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_W));
 969                 emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dstregtmpmask(tempreg, RC_MASK_XY),
 970                         srcreg(RC_FILE_TEMPORARY, tempreg));
 971                 emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(tempreg, RC_MASK_XY),
 972                         srcreg(RC_FILE_TEMPORARY, tempreg),
 973                         swizzle_wwww(srcreg(RC_FILE_CONSTANT, constants[1])),
 974                         negate(swizzle_zzzz(srcreg(RC_FILE_CONSTANT, constants[0]))));
 975
 976                 dst = inst->U.I.DstReg;
 977
 978                 dst.WriteMask = inst->U.I.DstReg.WriteMask & RC_MASK_X;
 979                 sin_approx(c, inst, dst,
 980                         swizzle_xxxx(srcreg(RC_FILE_TEMPORARY, tempreg)),
 981                         constants);
 982
 983                 dst.WriteMask = inst->U.I.DstReg.WriteMask & RC_MASK_Y;
 984                 sin_approx(c, inst, dst,
 985                         swizzle_yyyy(srcreg(RC_FILE_TEMPORARY, tempreg)),
 986                         constants);
 987         }
 988
 989         rc_remove_instruction(inst);
 990
 991         return 1;
 992 }
 993
 994 static void r300_transform_SIN_COS(struct radeon_compiler *c,
 995         struct rc_instruction *inst,
 996         unsigned srctmp)
 997 {
 998         if (inst->U.I.Opcode == RC_OPCODE_COS) {
 999                 emit1(c, inst->Prev, RC_OPCODE_COS, &inst->U.I, inst->U.I.DstReg,
1000                         srcregswz(RC_FILE_TEMPORARY, srctmp, RC_SWIZZLE_WWWW));
1001         } else if (inst->U.I.Opcode == RC_OPCODE_SIN) {
1002                 emit1(c, inst->Prev, RC_OPCODE_SIN, &inst->U.I,
1003                         inst->U.I.DstReg, srcregswz(RC_FILE_TEMPORARY, srctmp, RC_SWIZZLE_WWWW));
1004         }
1005
1006         rc_remove_instruction(inst);
1007 }
1008
1009
1010 /**
1011  * Transform the trigonometric functions COS and SIN
1012  * to include pre-scaling by 1/(2*PI) and taking the fractional
1013  * part, so that the input to COS and SIN is always in the range [0,1).
1014  *
1015  * @warning This transformation implicitly changes the semantics of SIN and COS!
1016  */
1017 int radeonTransformTrigScale(struct radeon_compiler* c,
1018         struct rc_instruction* inst,
1019         void* unused)
1020 {
1021         static const float RCP_2PI = 0.15915494309189535;
1022         unsigned int temp;
1023         unsigned int constant;
1024         unsigned int constant_swizzle;
1025
1026         if (inst->U.I.Opcode != RC_OPCODE_COS &&
1027             inst->U.I.Opcode != RC_OPCODE_SIN)
1028                 return 0;
1029
1030         if (!c->needs_trig_input_transform)
1031                 return 1;
1032
1033         temp = rc_find_free_temporary(c);
1034         constant = rc_constants_add_immediate_scalar(&c->Program.Constants, RCP_2PI, &constant_swizzle);
1035
1036         emit2(c, inst->Prev, RC_OPCODE_MUL, NULL, dstregtmpmask(temp, RC_MASK_W),
1037                 swizzle_xxxx(inst->U.I.SrcReg[0]),
1038                 srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle));
1039         emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dstregtmpmask(temp, RC_MASK_W),
1040                 srcreg(RC_FILE_TEMPORARY, temp));
1041
1042         r300_transform_SIN_COS(c, inst, temp);
1043         return 1;
1044 }
1045
1046 /**
1047  * Transform the trigonometric functions COS and SIN
1048  * so that the input to COS and SIN is always in the range [-PI, PI].
1049  */
1050 int r300_transform_trig_scale_vertex(struct radeon_compiler *c,
1051         struct rc_instruction *inst,
1052         void *unused)
1053 {
1054         static const float cons[4] = {0.15915494309189535, 0.5, 6.28318530717959, -3.14159265358979};
1055         unsigned int temp;
1056         unsigned int constant;
1057
1058         if (inst->U.I.Opcode != RC_OPCODE_COS &&
1059             inst->U.I.Opcode != RC_OPCODE_SIN)
1060                 return 0;
1061
1062         if (!c->needs_trig_input_transform)
1063                 return 1;
1064
1065         /* Repeat x in the range [-PI, PI]:
1066          *
1067          *   repeat(x) = frac(x / 2PI + 0.5) * 2PI - PI
1068          */
1069
1070         temp = rc_find_free_temporary(c);
1071         constant = rc_constants_add_immediate_vec4(&c->Program.Constants, cons);
1072
1073         emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(temp, RC_MASK_W),
1074                 swizzle_xxxx(inst->U.I.SrcReg[0]),
1075                 srcregswz(RC_FILE_CONSTANT, constant, RC_SWIZZLE_XXXX),
1076                 srcregswz(RC_FILE_CONSTANT, constant, RC_SWIZZLE_YYYY));
1077         emit1(c, inst->Prev, RC_OPCODE_FRC, NULL, dstregtmpmask(temp, RC_MASK_W),
1078                 srcreg(RC_FILE_TEMPORARY, temp));
1079         emit3(c, inst->Prev, RC_OPCODE_MAD, NULL, dstregtmpmask(temp, RC_MASK_W),
1080                 srcreg(RC_FILE_TEMPORARY, temp),
1081                 srcregswz(RC_FILE_CONSTANT, constant, RC_SWIZZLE_ZZZZ),
1082                 srcregswz(RC_FILE_CONSTANT, constant, RC_SWIZZLE_WWWW));
1083
1084         r300_transform_SIN_COS(c, inst, temp);
1085         return 1;
1086 }
1087
1088 /**
1089  * Replaces DDX/DDY instructions with MOV 0 to avoid using dummy shaders on r300/r400.
1090  *
1091  * @warning This explicitly changes the form of DDX and DDY!
1092  */
1093
1094 int radeonStubDeriv(struct radeon_compiler* c,
1095         struct rc_instruction* inst,
1096         void* unused)
1097 {
1098         if (inst->U.I.Opcode != RC_OPCODE_DDX && inst->U.I.Opcode != RC_OPCODE_DDY)
1099                 return 0;
1100
1101         inst->U.I.Opcode = RC_OPCODE_MOV;
1102         inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
1103
1104         mesa_logw_once("r300: WARNING: Shader is trying to use derivatives, "
1105                                         "but the hardware doesn't support it. "
1106                                         "Expect possible misrendering (it's not a bug, do not report it).");
1107
1108         return 1;
1109 }
1110
1111 /**
1112  * Rewrite DDX/DDY instructions to properly work with r5xx shaders.
1113  * The r5xx MDH/MDV instruction provides per-quad partial derivatives.
1114  * It takes the form A*B+C. A and C are set by setting src0. B should be -1.
1115  *
1116  * @warning This explicitly changes the form of DDX and DDY!
1117  */
1118
1119 int radeonTransformDeriv(struct radeon_compiler* c,
1120         struct rc_instruction* inst,
1121         void* unused)
1122 {
1123         if (inst->U.I.Opcode != RC_OPCODE_DDX && inst->U.I.Opcode != RC_OPCODE_DDY)
1124                 return 0;
1125
1126         inst->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_1111;
1127         inst->U.I.SrcReg[1].Negate = RC_MASK_XYZW;
1128
1129         return 1;
1130 }
1131
1132 /**
1133  * IF Temp[0].x -> IF Temp[0].x
1134  * ...          -> ...
1135  * KILL         -> KIL -abs(Temp[0].x)
1136  * ...          -> ...
1137  * ENDIF        -> ENDIF
1138  *
1139  * === OR ===
1140  *
1141  * IF Temp[0].x -> IF Temp[0].x
1142  * ...          -> ...
1143  * ELSE         -> ELSE
1144  * ...          -> ...
1145  * KILL         -> KIL -abs(Temp[0].x)
1146  * ...          -> ...
1147  * ENDIF        -> ENDIF
1148  *
1149  * === OR ===
1150  *
1151  * KILL         -> KIL -none.1111
1152  *
1153  * This needs to be done in its own pass, because it might modify the
1154  * instructions before and after KILL.
1155  */
1156 void rc_transform_KILL(struct radeon_compiler * c, void *user)
1157 {
1158         struct rc_instruction * inst;
1159         for (inst = c->Program.Instructions.Next;
1160                         inst != &c->Program.Instructions; inst = inst->Next) {
1161                 struct rc_instruction * if_inst;
1162                 unsigned in_if = 0;
1163
1164                 if (inst->U.I.Opcode != RC_OPCODE_KILP)
1165                         continue;
1166
1167                 for (if_inst = inst->Prev; if_inst != &c->Program.Instructions;
1168                                                 if_inst = if_inst->Prev) {
1169
1170                         if (if_inst->U.I.Opcode == RC_OPCODE_IF) {
1171                                 in_if = 1;
1172                                 break;
1173                         }
1174                 }
1175
1176                 inst->U.I.Opcode = RC_OPCODE_KIL;
1177
1178                 if (!in_if) {
1179                         inst->U.I.SrcReg[0] = negate(builtin_one);
1180                 } else {
1181                         /* This should work even if the KILP is inside the ELSE
1182                          * block, because -0.0 is considered negative. */
1183                         inst->U.I.SrcReg[0] =
1184                                 negate(absolute(if_inst->U.I.SrcReg[0]));
1185                 }
1186         }
1187 }
1188
1189 int rc_force_output_alpha_to_one(struct radeon_compiler *c,
1190                                  struct rc_instruction *inst, void *data)
1191 {
1192         struct r300_fragment_program_compiler *fragc = (struct r300_fragment_program_compiler*)c;
1193         const struct rc_opcode_info *info = rc_get_opcode_info(inst->U.I.Opcode);
1194         unsigned tmp;
1195
1196         if (!info->HasDstReg || inst->U.I.DstReg.File != RC_FILE_OUTPUT ||
1197             inst->U.I.DstReg.Index == fragc->OutputDepth)
1198                 return 1;
1199
1200         tmp = rc_find_free_temporary(c);
1201
1202         /* Insert MOV after inst, set alpha to 1. */
1203         emit1(c, inst, RC_OPCODE_MOV, NULL, inst->U.I.DstReg,
1204               srcregswz(RC_FILE_TEMPORARY, tmp, RC_SWIZZLE_XYZ1));
1205
1206         /* Re-route the destination of inst to the source of mov. */
1207         inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
1208         inst->U.I.DstReg.Index = tmp;
1209
1210         /* Move the saturate output modifier to the MOV instruction
1211          * (for better copy propagation). */
1212         inst->Next->U.I.SaturateMode = inst->U.I.SaturateMode;
1213         inst->U.I.SaturateMode = RC_SATURATE_NONE;
1214         return 1;
1215 }