1 #include "pipe/p_context.h"
2 #include "pipe/p_format.h"
3 #include "util/u_format.h"
4 #include "util/u_math.h"
5 #include "util/u_memory.h"
7 #include "nouveau/nouveau_winsys.h"
8 #include "nouveau/nouveau_util.h"
9 #include "nouveau/nouveau_screen.h"
10 #include "nv04_surface_2d.h"
13 nv04_surface_format(enum pipe_format format)
16 case PIPE_FORMAT_A8_UNORM:
17 case PIPE_FORMAT_L8_UNORM:
18 case PIPE_FORMAT_I8_UNORM:
19 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
20 case PIPE_FORMAT_R16_SNORM:
21 case PIPE_FORMAT_B5G6R5_UNORM:
22 case PIPE_FORMAT_Z16_UNORM:
23 case PIPE_FORMAT_L8A8_UNORM:
24 return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
25 case PIPE_FORMAT_B8G8R8X8_UNORM:
26 case PIPE_FORMAT_B8G8R8A8_UNORM:
27 return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8;
28 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
29 case PIPE_FORMAT_X8Z24_UNORM:
30 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
37 nv04_rect_format(enum pipe_format format)
40 case PIPE_FORMAT_A8_UNORM:
41 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
42 case PIPE_FORMAT_B5G6R5_UNORM:
43 case PIPE_FORMAT_L8A8_UNORM:
44 case PIPE_FORMAT_Z16_UNORM:
45 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
46 case PIPE_FORMAT_B8G8R8X8_UNORM:
47 case PIPE_FORMAT_B8G8R8A8_UNORM:
48 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
49 case PIPE_FORMAT_X8Z24_UNORM:
50 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
57 nv04_scaled_image_format(enum pipe_format format)
60 case PIPE_FORMAT_A8_UNORM:
61 case PIPE_FORMAT_L8_UNORM:
62 case PIPE_FORMAT_I8_UNORM:
63 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8;
64 case PIPE_FORMAT_B5G5R5A1_UNORM:
65 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5;
66 case PIPE_FORMAT_B8G8R8A8_UNORM:
67 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8;
68 case PIPE_FORMAT_B8G8R8X8_UNORM:
69 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8;
70 case PIPE_FORMAT_B5G6R5_UNORM:
71 case PIPE_FORMAT_R16_SNORM:
72 case PIPE_FORMAT_L8A8_UNORM:
73 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5;
79 static INLINE unsigned
80 nv04_swizzle_bits_square(unsigned x, unsigned y)
82 unsigned u = (x & 0x001) << 0 |
95 unsigned v = (y & 0x001) << 1 |
110 /* rectangular swizzled textures are linear concatenations of swizzled square tiles */
111 static INLINE unsigned
112 nv04_swizzle_bits(unsigned x, unsigned y, unsigned w, unsigned h)
114 unsigned s = MIN2(w, h);
116 return (((x | y) & ~m) * s) | nv04_swizzle_bits_square(x & m, y & m);
120 nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx,
121 struct pipe_surface *dst, int dx, int dy,
122 struct pipe_surface *src, int sx, int sy,
125 struct nouveau_channel *chan = ctx->swzsurf->channel;
126 struct nouveau_grobj *swzsurf = ctx->swzsurf;
127 struct nouveau_grobj *sifm = ctx->sifm;
128 struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
129 struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
130 const unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
131 /* Max width & height may not be the same on all HW, but must be POT */
132 const unsigned max_w = 1024;
133 const unsigned max_h = 1024;
134 unsigned sub_w = w > max_w ? max_w : w;
135 unsigned sub_h = h > max_h ? max_h : h;
139 /* Swizzled surfaces must be POT */
140 assert(util_is_pot(dst->width) && util_is_pot(dst->height));
142 /* If area is too large to copy in one shot we must copy it in POT chunks to meet alignment requirements */
143 assert(sub_w == w || util_is_pot(sub_w));
144 assert(sub_h == h || util_is_pot(sub_h));
146 MARK_RING (chan, 8 + ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*17, 2 +
147 ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*2);
149 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
150 OUT_RELOCo(chan, dst_bo,
151 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
153 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1);
154 OUT_RING (chan, nv04_surface_format(dst->format) |
155 log2i(dst->width) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT |
156 log2i(dst->height) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT);
158 BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1);
159 OUT_RELOCo(chan, src_bo,
160 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
161 BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1);
162 OUT_RING (chan, swzsurf->handle);
164 for (y = 0; y < h; y += sub_h) {
165 sub_h = MIN2(sub_h, h - y);
167 for (x = 0; x < w; x += sub_w) {
168 sub_w = MIN2(sub_w, w - x);
170 assert(!(dst->offset & 63));
172 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1);
173 OUT_RELOCl(chan, dst_bo, dst->offset,
174 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
176 BEGIN_RING(chan, sifm, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9);
177 OUT_RING (chan, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE);
178 OUT_RING (chan, nv04_scaled_image_format(src->format));
179 OUT_RING (chan, NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
180 OUT_RING (chan, (x + dx) | ((y + dy) << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT));
181 OUT_RING (chan, sub_h << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT | sub_w);
182 OUT_RING (chan, (x + dx) | ((y + dy) << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_SHIFT));
183 OUT_RING (chan, sub_h << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT | sub_w);
184 OUT_RING (chan, 1 << 20);
185 OUT_RING (chan, 1 << 20);
187 BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_SIZE, 4);
188 OUT_RING (chan, sub_h << NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT | sub_w);
189 OUT_RING (chan, src_pitch |
190 NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER |
191 NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
192 OUT_RELOCl(chan, src_bo, src->offset + (sy+y) * src_pitch + (sx+x) * util_format_get_blocksize(src->texture->format),
193 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
202 nv04_surface_copy_m2mf(struct nv04_surface_2d *ctx,
203 struct pipe_surface *dst, int dx, int dy,
204 struct pipe_surface *src, int sx, int sy, int w, int h)
206 struct nouveau_channel *chan = ctx->m2mf->channel;
207 struct nouveau_grobj *m2mf = ctx->m2mf;
208 struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
209 struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
210 unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
211 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
212 unsigned dst_offset = dst->offset + dy * dst_pitch +
213 dx * util_format_get_blocksize(dst->texture->format);
214 unsigned src_offset = src->offset + sy * src_pitch +
215 sx * util_format_get_blocksize(src->texture->format);
217 MARK_RING (chan, 3 + ((h / 2047) + 1) * 9, 2 + ((h / 2047) + 1) * 2);
218 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
219 OUT_RELOCo(chan, src_bo,
220 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
221 OUT_RELOCo(chan, dst_bo,
222 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
225 int count = (h > 2047) ? 2047 : h;
227 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
228 OUT_RELOCl(chan, src_bo, src_offset,
229 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
230 OUT_RELOCl(chan, dst_bo, dst_offset,
231 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
232 OUT_RING (chan, src_pitch);
233 OUT_RING (chan, dst_pitch);
234 OUT_RING (chan, w * util_format_get_blocksize(src->texture->format));
235 OUT_RING (chan, count);
236 OUT_RING (chan, 0x0101);
240 src_offset += src_pitch * count;
241 dst_offset += dst_pitch * count;
248 nv04_surface_copy_blit(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
249 int dx, int dy, struct pipe_surface *src, int sx, int sy,
252 struct nouveau_channel *chan = ctx->surf2d->channel;
253 struct nouveau_grobj *surf2d = ctx->surf2d;
254 struct nouveau_grobj *blit = ctx->blit;
255 struct nouveau_bo *src_bo = nouveau_bo(ctx->buf(src));
256 struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
257 unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
258 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
261 format = nv04_surface_format(dst->format);
265 MARK_RING (chan, 12, 4);
266 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
267 OUT_RELOCo(chan, src_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
268 OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
269 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
270 OUT_RING (chan, format);
271 OUT_RING (chan, (dst_pitch << 16) | src_pitch);
272 OUT_RELOCl(chan, src_bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
273 OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
275 BEGIN_RING(chan, blit, 0x0300, 3);
276 OUT_RING (chan, (sy << 16) | sx);
277 OUT_RING (chan, (dy << 16) | dx);
278 OUT_RING (chan, ( h << 16) | w);
284 nv04_surface_copy(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
285 int dx, int dy, struct pipe_surface *src, int sx, int sy,
288 unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
289 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
290 int src_linear = src->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
291 int dst_linear = dst->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR;
293 assert(src->format == dst->format);
295 /* Setup transfer to swizzle the texture to vram if needed */
296 if (src_linear && !dst_linear && w > 1 && h > 1) {
297 nv04_surface_copy_swizzle(ctx, dst, dx, dy, src, sx, sy, w, h);
301 /* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback
302 * to NV_MEMORY_TO_MEMORY_FORMAT in this case.
304 if ((src->offset & 63) || (dst->offset & 63) ||
305 (src_pitch & 63) || (dst_pitch & 63)) {
306 nv04_surface_copy_m2mf(ctx, dst, dx, dy, src, sx, sy, w, h);
310 nv04_surface_copy_blit(ctx, dst, dx, dy, src, sx, sy, w, h);
314 nv04_surface_fill(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
315 int dx, int dy, int w, int h, unsigned value)
317 struct nouveau_channel *chan = ctx->surf2d->channel;
318 struct nouveau_grobj *surf2d = ctx->surf2d;
319 struct nouveau_grobj *rect = ctx->rect;
320 struct nouveau_bo *dst_bo = nouveau_bo(ctx->buf(dst));
321 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
322 int cs2d_format, gdirect_format;
324 cs2d_format = nv04_surface_format(dst->format);
325 assert(cs2d_format >= 0);
327 gdirect_format = nv04_rect_format(dst->format);
328 assert(gdirect_format >= 0);
330 MARK_RING (chan, 16, 4);
331 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
332 OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
333 OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
334 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
335 OUT_RING (chan, cs2d_format);
336 OUT_RING (chan, (dst_pitch << 16) | dst_pitch);
337 OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
338 OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
340 BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
341 OUT_RING (chan, gdirect_format);
342 BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
343 OUT_RING (chan, value);
344 BEGIN_RING(chan, rect,
345 NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
346 OUT_RING (chan, (dx << 16) | dy);
347 OUT_RING (chan, ( w << 16) | h);
351 nv04_surface_2d_takedown(struct nv04_surface_2d **pctx)
353 struct nv04_surface_2d *ctx;
360 nouveau_notifier_free(&ctx->ntfy);
361 nouveau_grobj_free(&ctx->m2mf);
362 nouveau_grobj_free(&ctx->surf2d);
363 nouveau_grobj_free(&ctx->swzsurf);
364 nouveau_grobj_free(&ctx->rect);
365 nouveau_grobj_free(&ctx->blit);
366 nouveau_grobj_free(&ctx->sifm);
371 struct nv04_surface_2d *
372 nv04_surface_2d_init(struct nouveau_screen *screen)
374 struct nv04_surface_2d *ctx = CALLOC_STRUCT(nv04_surface_2d);
375 struct nouveau_channel *chan = screen->channel;
376 unsigned handle = 0x88000000, class;
382 ret = nouveau_notifier_alloc(chan, handle++, 1, &ctx->ntfy);
384 nv04_surface_2d_takedown(&ctx);
388 ret = nouveau_grobj_alloc(chan, handle++, 0x0039, &ctx->m2mf);
390 nv04_surface_2d_takedown(&ctx);
394 BEGIN_RING(chan, ctx->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
395 OUT_RING (chan, ctx->ntfy->handle);
397 if (chan->device->chipset < 0x10)
398 class = NV04_CONTEXT_SURFACES_2D;
400 class = NV10_CONTEXT_SURFACES_2D;
402 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->surf2d);
404 nv04_surface_2d_takedown(&ctx);
408 BEGIN_RING(chan, ctx->surf2d,
409 NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
410 OUT_RING (chan, chan->vram->handle);
411 OUT_RING (chan, chan->vram->handle);
413 if (chan->device->chipset < 0x10)
414 class = NV04_IMAGE_BLIT;
416 class = NV12_IMAGE_BLIT;
418 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit);
420 nv04_surface_2d_takedown(&ctx);
424 BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_DMA_NOTIFY, 1);
425 OUT_RING (chan, ctx->ntfy->handle);
426 BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACE, 1);
427 OUT_RING (chan, ctx->surf2d->handle);
428 BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_OPERATION, 1);
429 OUT_RING (chan, NV01_IMAGE_BLIT_OPERATION_SRCCOPY);
431 ret = nouveau_grobj_alloc(chan, handle++, NV04_GDI_RECTANGLE_TEXT,
434 nv04_surface_2d_takedown(&ctx);
438 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
439 OUT_RING (chan, ctx->ntfy->handle);
440 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
441 OUT_RING (chan, ctx->surf2d->handle);
442 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
443 OUT_RING (chan, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
444 BEGIN_RING(chan, ctx->rect,
445 NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
446 OUT_RING (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
448 switch (chan->device->chipset & 0xf0) {
451 class = NV04_SWIZZLED_SURFACE;
454 class = NV20_SWIZZLED_SURFACE;
457 class = NV30_SWIZZLED_SURFACE;
461 class = NV40_SWIZZLED_SURFACE;
464 /* Famous last words: this really can't happen.. */
469 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->swzsurf);
471 nv04_surface_2d_takedown(&ctx);
475 switch (chan->device->chipset & 0xf0) {
478 class = NV10_SCALED_IMAGE_FROM_MEMORY;
481 class = NV30_SCALED_IMAGE_FROM_MEMORY;
485 class = NV40_SCALED_IMAGE_FROM_MEMORY;
488 class = NV04_SCALED_IMAGE_FROM_MEMORY;
492 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->sifm);
494 nv04_surface_2d_takedown(&ctx);
498 ctx->copy = nv04_surface_copy;
499 ctx->fill = nv04_surface_fill;
504 nv04_surface_wrap_for_render(struct pipe_screen *pscreen, struct nv04_surface_2d* eng2d, struct nv04_surface* ns)
508 // printf("creating temp, flags is %i!\n", flags);
510 if(ns->base.usage & PIPE_BUFFER_USAGE_DISCARD)
512 temp_flags = ns->base.usage | PIPE_BUFFER_USAGE_GPU_READ;
513 ns->base.usage = PIPE_BUFFER_USAGE_GPU_WRITE | NOUVEAU_BUFFER_USAGE_NO_RENDER | PIPE_BUFFER_USAGE_DISCARD;
517 temp_flags = ns->base.usage | PIPE_BUFFER_USAGE_GPU_READ | PIPE_BUFFER_USAGE_GPU_WRITE;
518 ns->base.usage = PIPE_BUFFER_USAGE_GPU_WRITE | NOUVEAU_BUFFER_USAGE_NO_RENDER | PIPE_BUFFER_USAGE_GPU_READ;
521 ns->base.usage = PIPE_BUFFER_USAGE_GPU_READ | PIPE_BUFFER_USAGE_GPU_WRITE;
523 struct pipe_texture templ;
524 memset(&templ, 0, sizeof(templ));
525 templ.format = ns->base.texture->format;
526 templ.target = PIPE_TEXTURE_2D;
527 templ.width0 = ns->base.width;
528 templ.height0 = ns->base.height;
530 templ.last_level = 0;
532 // TODO: this is probably wrong and we should specifically handle multisampling somehow once it is implemented
533 templ.nr_samples = ns->base.texture->nr_samples;
535 templ.tex_usage = ns->base.texture->tex_usage | PIPE_TEXTURE_USAGE_RENDER_TARGET;
537 struct pipe_texture* temp_tex = pscreen->texture_create(pscreen, &templ);
538 struct nv04_surface* temp_ns = (struct nv04_surface*)pscreen->get_tex_surface(pscreen, temp_tex, 0, 0, 0, temp_flags);
539 temp_ns->backing = ns;
541 if(ns->base.usage & PIPE_BUFFER_USAGE_GPU_READ)
542 eng2d->copy(eng2d, &temp_ns->backing->base, 0, 0, &ns->base, 0, 0, ns->base.width, ns->base.height);