2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "util/u_format_s3tc.h"
24 #include "pipe/p_screen.h"
26 #include "nvc0_context.h"
27 #include "nvc0_screen.h"
29 #include "nouveau/nv_object.xml.h"
30 #include "nvc0_graph_macros.h"
33 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
34 enum pipe_format format,
35 enum pipe_texture_target target,
36 unsigned sample_count,
37 unsigned bindings, unsigned geom_flags)
42 if (!util_format_s3tc_enabled) {
44 case PIPE_FORMAT_DXT1_RGB:
45 case PIPE_FORMAT_DXT1_RGBA:
46 case PIPE_FORMAT_DXT3_RGBA:
47 case PIPE_FORMAT_DXT5_RGBA:
54 /* transfers & shared are always supported */
55 bindings &= ~(PIPE_BIND_TRANSFER_READ |
56 PIPE_BIND_TRANSFER_WRITE |
59 return (nvc0_format_table[format].usage & bindings) == bindings;
63 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
66 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
67 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
69 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
71 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
73 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
77 case PIPE_CAP_ARRAY_TEXTURES:
79 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
80 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
81 case PIPE_CAP_TEXTURE_SWIZZLE:
82 case PIPE_CAP_TEXTURE_SHADOW_MAP:
83 case PIPE_CAP_NPOT_TEXTURES:
84 case PIPE_CAP_ANISOTROPIC_FILTER:
86 case PIPE_CAP_TWO_SIDED_STENCIL:
87 case PIPE_CAP_DEPTH_CLAMP:
88 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
89 case PIPE_CAP_POINT_SPRITE:
94 case PIPE_CAP_MAX_RENDER_TARGETS:
96 case PIPE_CAP_TIMER_QUERY:
97 case PIPE_CAP_OCCLUSION_QUERY:
99 case PIPE_CAP_STREAM_OUTPUT:
101 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
102 case PIPE_CAP_INDEP_BLEND_ENABLE:
103 case PIPE_CAP_INDEP_BLEND_FUNC:
105 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
106 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
108 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
109 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
111 case PIPE_CAP_SHADER_STENCIL_EXPORT:
113 case PIPE_CAP_PRIMITIVE_RESTART:
114 case PIPE_CAP_INSTANCED_DRAWING:
117 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
123 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
124 enum pipe_shader_cap param)
127 case PIPE_SHADER_VERTEX:
129 case PIPE_SHADER_TESSELLATION_CONTROL:
130 case PIPE_SHADER_TESSELLATION_EVALUATION:
132 case PIPE_SHADER_GEOMETRY:
133 case PIPE_SHADER_FRAGMENT:
140 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
141 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
142 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
143 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
145 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
147 case PIPE_SHADER_CAP_MAX_INPUTS:
148 if (shader == PIPE_SHADER_VERTEX)
151 case PIPE_SHADER_CAP_MAX_CONSTS:
153 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
155 case PIPE_SHADER_CAP_MAX_ADDRS:
157 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
158 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
159 return shader != PIPE_SHADER_FRAGMENT;
160 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
161 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
163 case PIPE_SHADER_CAP_MAX_PREDS:
165 case PIPE_SHADER_CAP_MAX_TEMPS:
166 return NVC0_CAP_MAX_PROGRAM_TEMPS;
167 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
169 case PIPE_SHADER_CAP_SUBROUTINES:
170 return 0; /* please inline, or provide function declarations */
172 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
178 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
181 case PIPE_CAP_MAX_LINE_WIDTH:
182 case PIPE_CAP_MAX_LINE_WIDTH_AA:
184 case PIPE_CAP_MAX_POINT_WIDTH:
185 case PIPE_CAP_MAX_POINT_WIDTH_AA:
187 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
189 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
192 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
198 nvc0_screen_destroy(struct pipe_screen *pscreen)
200 struct nvc0_screen *screen = nvc0_screen(pscreen);
202 nouveau_fence_wait(screen->base.fence.current);
203 nouveau_fence_ref(NULL, &screen->base.fence.current);
205 nouveau_bo_ref(NULL, &screen->text);
206 nouveau_bo_ref(NULL, &screen->tls);
207 nouveau_bo_ref(NULL, &screen->txc);
208 nouveau_bo_ref(NULL, &screen->fence.bo);
209 nouveau_bo_ref(NULL, &screen->mp_stack_bo);
211 nouveau_resource_destroy(&screen->text_heap);
213 if (screen->tic.entries)
214 FREE(screen->tic.entries);
216 nouveau_mm_destroy(screen->mm_VRAM_fe0);
218 nouveau_grobj_free(&screen->fermi);
219 nouveau_grobj_free(&screen->eng2d);
220 nouveau_grobj_free(&screen->m2mf);
222 nouveau_screen_fini(&screen->base);
228 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
229 unsigned size, const uint32_t *data)
231 struct nouveau_channel *chan = screen->base.channel;
235 BEGIN_RING(chan, RING_3D_(NVC0_GRAPH_MACRO_ID), 2);
236 OUT_RING (chan, (m - 0x3800) / 8);
237 OUT_RING (chan, pos);
238 BEGIN_RING_1I(chan, RING_3D_(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
239 OUT_RING (chan, pos);
240 OUT_RINGp (chan, data, size);
246 nvc0_magic_3d_init(struct nouveau_channel *chan)
248 BEGIN_RING(chan, RING_3D_(0x10cc), 1);
249 OUT_RING (chan, 0xff);
250 BEGIN_RING(chan, RING_3D_(0x10e0), 2);
251 OUT_RING(chan, 0xff);
252 OUT_RING(chan, 0xff);
253 BEGIN_RING(chan, RING_3D_(0x10ec), 2);
254 OUT_RING(chan, 0xff);
255 OUT_RING(chan, 0xff);
256 BEGIN_RING(chan, RING_3D_(0x074c), 1);
257 OUT_RING (chan, 0x3f);
259 BEGIN_RING(chan, RING_3D_(0x16a8), 1);
260 OUT_RING (chan, (3 << 16) | 3);
261 BEGIN_RING(chan, RING_3D_(0x1794), 1);
262 OUT_RING (chan, (2 << 16) | 2);
263 BEGIN_RING(chan, RING_3D_(0x0de8), 1);
266 #if 0 /* software method */
267 BEGIN_RING(chan, RING_3D_(0x1528), 1); /* MP poke */
271 BEGIN_RING(chan, RING_3D_(0x12ac), 1);
273 BEGIN_RING(chan, RING_3D_(0x0218), 1);
274 OUT_RING (chan, 0x10);
275 BEGIN_RING(chan, RING_3D_(0x10fc), 1);
276 OUT_RING (chan, 0x10);
277 BEGIN_RING(chan, RING_3D_(0x1290), 1);
278 OUT_RING (chan, 0x10);
279 BEGIN_RING(chan, RING_3D_(0x12d8), 2);
280 OUT_RING (chan, 0x10);
281 OUT_RING (chan, 0x10);
282 BEGIN_RING(chan, RING_3D_(0x06d4), 1);
284 BEGIN_RING(chan, RING_3D_(0x1140), 1);
285 OUT_RING (chan, 0x10);
286 BEGIN_RING(chan, RING_3D_(0x1610), 1);
287 OUT_RING (chan, 0xe);
289 BEGIN_RING(chan, RING_3D_(0x164c), 1);
290 OUT_RING (chan, 1 << 12);
291 BEGIN_RING(chan, RING_3D_(0x151c), 1);
293 BEGIN_RING(chan, RING_3D_(0x020c), 1);
295 BEGIN_RING(chan, RING_3D_(0x030c), 1);
297 BEGIN_RING(chan, RING_3D_(0x0300), 1);
299 #if 0 /* software method */
300 BEGIN_RING(chan, RING_3D_(0x1280), 1); /* PGRAPH poke */
303 BEGIN_RING(chan, RING_3D_(0x02d0), 1);
304 OUT_RING (chan, 0x1f40);
305 BEGIN_RING(chan, RING_3D_(0x00fdc), 1);
307 BEGIN_RING(chan, RING_3D_(0x19c0), 1);
309 BEGIN_RING(chan, RING_3D_(0x075c), 1);
312 BEGIN_RING(chan, RING_3D_(0x0fac), 1);
314 BEGIN_RING(chan, RING_3D_(0x0f90), 1);
319 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 sequence)
321 struct nvc0_screen *screen = nvc0_screen(pscreen);
322 struct nouveau_channel *chan = screen->base.channel;
324 MARK_RING (chan, 5, 2);
325 BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
326 OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
327 OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
328 OUT_RING (chan, sequence);
329 OUT_RING (chan, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
330 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
334 nvc0_screen_fence_update(struct pipe_screen *pscreen)
336 struct nvc0_screen *screen = nvc0_screen(pscreen);
337 return screen->fence.map[0];
340 #define FAIL_SCREEN_INIT(str, err) \
342 NOUVEAU_ERR(str, err); \
343 nvc0_screen_destroy(pscreen); \
348 nvc0_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
350 struct nvc0_screen *screen;
351 struct nouveau_channel *chan;
352 struct pipe_screen *pscreen;
356 screen = CALLOC_STRUCT(nvc0_screen);
359 pscreen = &screen->base.base;
361 screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
363 ret = nouveau_screen_init(&screen->base, dev);
365 nvc0_screen_destroy(pscreen);
368 chan = screen->base.channel;
370 pscreen->winsys = ws;
371 pscreen->destroy = nvc0_screen_destroy;
372 pscreen->context_create = nvc0_create;
373 pscreen->is_format_supported = nvc0_screen_is_format_supported;
374 pscreen->get_param = nvc0_screen_get_param;
375 pscreen->get_shader_param = nvc0_screen_get_shader_param;
376 pscreen->get_paramf = nvc0_screen_get_paramf;
378 nvc0_screen_init_resource_functions(pscreen);
380 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
384 nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
385 screen->fence.map = screen->fence.bo->map;
386 nouveau_bo_unmap(screen->fence.bo);
387 screen->base.fence.emit = nvc0_screen_fence_emit;
388 screen->base.fence.update = nvc0_screen_fence_update;
390 for (i = 0; i < NVC0_SCRATCH_NR_BUFFERS; ++i) {
391 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART, 0, NVC0_SCRATCH_SIZE,
392 &screen->scratch.bo[i]);
397 ret = nouveau_grobj_alloc(chan, 0xbeef9039, NVC0_M2MF, &screen->m2mf);
399 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
401 BIND_RING (chan, screen->m2mf, NVC0_SUBCH_MF);
402 BEGIN_RING(chan, RING_MF(NOTIFY_ADDRESS_HIGH), 3);
403 OUT_RELOCh(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
404 OUT_RELOCl(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
407 ret = nouveau_grobj_alloc(chan, 0xbeef902d, NVC0_2D, &screen->eng2d);
409 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
411 BIND_RING (chan, screen->eng2d, NVC0_SUBCH_2D);
412 BEGIN_RING(chan, RING_2D(OPERATION), 1);
413 OUT_RING (chan, NVC0_2D_OPERATION_SRCCOPY);
414 BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
416 BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
418 BEGIN_RING(chan, RING_2D_(0x0884), 1);
419 OUT_RING (chan, 0x3f);
420 BEGIN_RING(chan, RING_2D_(0x0888), 1);
423 ret = nouveau_grobj_alloc(chan, 0xbeef9097, NVC0_3D, &screen->fermi);
425 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
427 BIND_RING (chan, screen->fermi, NVC0_SUBCH_3D);
428 BEGIN_RING(chan, RING_3D(NOTIFY_ADDRESS_HIGH), 3);
429 OUT_RELOCh(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
430 OUT_RELOCl(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
433 BEGIN_RING(chan, RING_3D(COND_MODE), 1);
434 OUT_RING (chan, NVC0_3D_COND_MODE_ALWAYS);
436 BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
439 BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
441 BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
443 BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
444 OUT_RING (chan, NVC0_3D_MULTISAMPLE_MODE_1X);
445 BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
448 nvc0_magic_3d_init(chan);
450 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, &screen->text);
454 nouveau_resource_init(&screen->text_heap, 0, 1 << 20);
456 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16,
461 /* auxiliary constants (6 user clip planes, base instance id) */
462 BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
463 OUT_RING (chan, 256);
464 OUT_RELOCh(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
465 OUT_RELOCl(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
466 for (i = 0; i < 5; ++i) {
467 BEGIN_RING(chan, RING_3D(CB_BIND(i)), 1);
468 OUT_RING (chan, (15 << 4) | 1);
471 screen->tls_size = (16 * 32) * (NVC0_CAP_MAX_PROGRAM_TEMPS * 16);
472 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17,
473 screen->tls_size, &screen->tls);
477 BEGIN_RING(chan, RING_3D(CODE_ADDRESS_HIGH), 2);
478 OUT_RELOCh(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
479 OUT_RELOCl(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
480 BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 4);
481 OUT_RELOCh(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
482 OUT_RELOCl(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
483 OUT_RING (chan, screen->tls_size >> 32);
484 OUT_RING (chan, screen->tls_size);
485 BEGIN_RING(chan, RING_3D_(0x07a0), 1);
487 BEGIN_RING(chan, RING_3D(LOCAL_BASE), 1);
490 for (i = 0; i < 5; ++i) {
491 BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
492 OUT_RING (chan, 0x54);
494 BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
497 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20,
498 &screen->mp_stack_bo);
502 BEGIN_RING(chan, RING_3D_(0x17bc), 3);
503 OUT_RELOCh(chan, screen->mp_stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
504 OUT_RELOCl(chan, screen->mp_stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
507 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, &screen->txc);
511 BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
512 OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
513 OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
514 OUT_RING (chan, NVC0_TIC_MAX_ENTRIES - 1);
516 BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
517 OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
518 OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
519 OUT_RING (chan, NVC0_TSC_MAX_ENTRIES - 1);
521 BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
523 BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
526 BEGIN_RING(chan, RING_3D_(0x1590), 1); /* deactivate ZCULL */
527 OUT_RING (chan, 0x3f);
529 BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
530 OUT_RING (chan, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
531 BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
532 for (i = 0; i < 8 * 2; ++i)
534 BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
536 BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
539 /* neither scissors, viewport nor stencil mask should affect clears */
540 BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
543 BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
545 BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
546 OUT_RINGf (chan, 0.0f);
547 OUT_RINGf (chan, 1.0f);
548 BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
549 OUT_RING (chan, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
551 /* We use scissors instead of exact view volume clipping,
552 * so they're always enabled.
554 BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
556 OUT_RING (chan, 8192 << 16);
557 OUT_RING (chan, 8192 << 16);
559 BEGIN_RING(chan, RING_3D_(0x0fac), 1);
561 BEGIN_RING(chan, RING_3D_(0x3484), 1);
563 BEGIN_RING(chan, RING_3D_(0x0dbc), 1);
564 OUT_RING (chan, 0x00010000);
565 BEGIN_RING(chan, RING_3D_(0x0dd8), 1);
566 OUT_RING (chan, 0xff800006);
567 BEGIN_RING(chan, RING_3D_(0x3488), 1);
570 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
573 MK_MACRO(NVC0_3D_BLEND_ENABLES, nvc0_9097_blend_enables);
574 MK_MACRO(NVC0_3D_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
575 MK_MACRO(NVC0_3D_TEP_SELECT, nvc0_9097_tep_select);
576 MK_MACRO(NVC0_3D_GP_SELECT, nvc0_9097_gp_select);
577 MK_MACRO(NVC0_3D_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
578 MK_MACRO(NVC0_3D_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
579 MK_MACRO(NVC0_3D_COLOR_MASK_BROADCAST, nvc0_9097_color_mask_brdc);
581 BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
583 BEGIN_RING(chan, RING_3D(GP_SELECT), 1);
584 OUT_RING (chan, 0x40);
585 BEGIN_RING(chan, RING_3D(GP_BUILTIN_RESULT_EN), 1);
587 BEGIN_RING(chan, RING_3D(TEP_SELECT), 1);
588 OUT_RING (chan, 0x30);
589 BEGIN_RING(chan, RING_3D(PATCH_VERTICES), 1);
591 BEGIN_RING(chan, RING_3D(SP_SELECT(2)), 1);
592 OUT_RING (chan, 0x20);
593 BEGIN_RING(chan, RING_3D(SP_SELECT(0)), 1);
594 OUT_RING (chan, 0x00);
596 BEGIN_RING(chan, RING_3D(POINT_COORD_REPLACE), 1);
598 BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
599 OUT_RING (chan, NVC0_3D_POINT_RASTER_RULES_OGL);
601 BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1);
602 OUT_RING (chan, 0x11111111);
603 BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
606 BEGIN_RING(chan, RING_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
607 OUT_RING (chan, 0xab);
608 OUT_RING (chan, 0x00000000);
612 screen->tic.entries = CALLOC(4096, sizeof(void *));
613 screen->tsc.entries = screen->tic.entries + 2048;
615 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
617 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
622 nvc0_screen_destroy(pscreen);
627 nvc0_screen_make_buffers_resident(struct nvc0_screen *screen)
629 struct nouveau_channel *chan = screen->base.channel;
631 const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
633 MARK_RING(chan, 5, 5);
634 nouveau_bo_validate(chan, screen->text, flags);
635 nouveau_bo_validate(chan, screen->uniforms, flags);
636 nouveau_bo_validate(chan, screen->txc, flags);
637 nouveau_bo_validate(chan, screen->mp_stack_bo, flags);
639 if (screen->cur_ctx && screen->cur_ctx->state.tls_required)
640 nouveau_bo_validate(chan, screen->tls, flags);
644 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
646 int i = screen->tic.next;
648 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
649 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
651 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
653 if (screen->tic.entries[i])
654 nvc0_tic_entry(screen->tic.entries[i])->id = -1;
656 screen->tic.entries[i] = entry;
661 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
663 int i = screen->tsc.next;
665 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
666 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
668 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
670 if (screen->tsc.entries[i])
671 nvc0_tsc_entry(screen->tsc.entries[i])->id = -1;
673 screen->tsc.entries[i] = entry;