2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
27 #include "nv50_context.h"
28 #include "nv50_screen.h"
30 #include "nouveau/nv_object.xml.h"
32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
36 extern int nouveau_device_get_param(struct nouveau_device *dev,
37 uint64_t param, uint64_t *value);
40 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
41 enum pipe_format format,
42 enum pipe_texture_target target,
43 unsigned sample_count,
46 if (sample_count > 2 && sample_count != 4 && sample_count != 8)
48 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
51 if (!util_format_is_supported(format, bindings))
55 case PIPE_FORMAT_Z16_UNORM:
56 if (nv50_screen(pscreen)->tesla->grclass < NVA0_3D)
63 /* transfers & shared are always supported */
64 bindings &= ~(PIPE_BIND_TRANSFER_READ |
65 PIPE_BIND_TRANSFER_WRITE |
68 return (nv50_format_table[format].usage & bindings) == bindings;
72 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
75 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
76 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
78 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
80 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
82 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
84 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
86 case PIPE_CAP_ARRAY_TEXTURES: /* shader support missing */
88 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
89 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
90 case PIPE_CAP_TEXTURE_SWIZZLE:
91 case PIPE_CAP_TEXTURE_SHADOW_MAP:
92 case PIPE_CAP_NPOT_TEXTURES:
93 case PIPE_CAP_ANISOTROPIC_FILTER:
94 case PIPE_CAP_SCALED_RESOLVE:
96 case PIPE_CAP_SEAMLESS_CUBE_MAP:
97 return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D;
98 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
100 case PIPE_CAP_TWO_SIDED_STENCIL:
101 case PIPE_CAP_DEPTH_CLAMP:
102 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
103 case PIPE_CAP_POINT_SPRITE:
108 case PIPE_CAP_MAX_RENDER_TARGETS:
110 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
112 case PIPE_CAP_TIMER_QUERY:
113 case PIPE_CAP_OCCLUSION_QUERY:
115 case PIPE_CAP_STREAM_OUTPUT:
117 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
118 case PIPE_CAP_INDEP_BLEND_ENABLE:
120 case PIPE_CAP_INDEP_BLEND_FUNC:
121 return nv50_screen(pscreen)->tesla->grclass >= NVA3_3D;
122 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
123 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
125 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
126 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
128 case PIPE_CAP_SHADER_STENCIL_EXPORT:
130 case PIPE_CAP_PRIMITIVE_RESTART:
131 case PIPE_CAP_TGSI_INSTANCEID:
132 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
133 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
136 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
142 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
143 enum pipe_shader_cap param)
146 case PIPE_SHADER_VERTEX:
147 case PIPE_SHADER_GEOMETRY:
148 case PIPE_SHADER_FRAGMENT:
155 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
156 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
157 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
158 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
160 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
162 case PIPE_SHADER_CAP_MAX_INPUTS:
163 if (shader == PIPE_SHADER_VERTEX)
166 case PIPE_SHADER_CAP_MAX_CONSTS:
168 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
170 case PIPE_SHADER_CAP_MAX_ADDRS:
172 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
173 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
174 return shader != PIPE_SHADER_FRAGMENT;
175 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
176 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
178 case PIPE_SHADER_CAP_MAX_PREDS:
180 case PIPE_SHADER_CAP_MAX_TEMPS:
181 return NV50_CAP_MAX_PROGRAM_TEMPS;
182 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
184 case PIPE_SHADER_CAP_SUBROUTINES:
185 return 0; /* please inline, or provide function declarations */
186 case PIPE_SHADER_CAP_INTEGERS:
189 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
195 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
198 case PIPE_CAP_MAX_LINE_WIDTH:
199 case PIPE_CAP_MAX_LINE_WIDTH_AA:
201 case PIPE_CAP_MAX_POINT_WIDTH:
202 case PIPE_CAP_MAX_POINT_WIDTH_AA:
204 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
206 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
209 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
215 nv50_screen_destroy(struct pipe_screen *pscreen)
217 struct nv50_screen *screen = nv50_screen(pscreen);
219 if (screen->base.fence.current) {
220 nouveau_fence_wait(screen->base.fence.current);
221 nouveau_fence_ref (NULL, &screen->base.fence.current);
223 screen->base.channel->user_private = NULL;
225 nouveau_bo_ref(NULL, &screen->code);
226 nouveau_bo_ref(NULL, &screen->tls_bo);
227 nouveau_bo_ref(NULL, &screen->stack_bo);
228 nouveau_bo_ref(NULL, &screen->txc);
229 nouveau_bo_ref(NULL, &screen->uniforms);
230 nouveau_bo_ref(NULL, &screen->fence.bo);
232 nouveau_resource_destroy(&screen->vp_code_heap);
233 nouveau_resource_destroy(&screen->gp_code_heap);
234 nouveau_resource_destroy(&screen->fp_code_heap);
236 if (screen->tic.entries)
237 FREE(screen->tic.entries);
239 nouveau_mm_destroy(screen->mm_VRAM_fe0);
241 nouveau_grobj_free(&screen->tesla);
242 nouveau_grobj_free(&screen->eng2d);
243 nouveau_grobj_free(&screen->m2mf);
245 nouveau_notifier_free(&screen->sync);
247 nouveau_screen_fini(&screen->base);
253 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 sequence)
255 struct nv50_screen *screen = nv50_screen(pscreen);
256 struct nouveau_channel *chan = screen->base.channel;
258 MARK_RING (chan, 5, 2);
259 BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
260 OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
261 OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
262 OUT_RING (chan, sequence);
263 OUT_RING (chan, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
264 NV50_3D_QUERY_GET_UNK4 |
265 NV50_3D_QUERY_GET_UNIT_CROP |
266 NV50_3D_QUERY_GET_TYPE_QUERY |
267 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
268 NV50_3D_QUERY_GET_SHORT);
272 nv50_screen_fence_update(struct pipe_screen *pscreen)
274 struct nv50_screen *screen = nv50_screen(pscreen);
275 return screen->fence.map[0];
278 #define FAIL_SCREEN_INIT(str, err) \
280 NOUVEAU_ERR(str, err); \
281 nv50_screen_destroy(pscreen); \
286 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
288 struct nv50_screen *screen;
289 struct nouveau_channel *chan;
290 struct pipe_screen *pscreen;
292 uint32_t tesla_class;
293 unsigned stack_size, max_warps, tls_space;
297 screen = CALLOC_STRUCT(nv50_screen);
300 pscreen = &screen->base.base;
302 screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
304 ret = nouveau_screen_init(&screen->base, dev);
306 FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
308 chan = screen->base.channel;
309 chan->user_private = screen;
311 pscreen->winsys = ws;
312 pscreen->destroy = nv50_screen_destroy;
313 pscreen->context_create = nv50_create;
314 pscreen->is_format_supported = nv50_screen_is_format_supported;
315 pscreen->get_param = nv50_screen_get_param;
316 pscreen->get_shader_param = nv50_screen_get_shader_param;
317 pscreen->get_paramf = nv50_screen_get_paramf;
319 nv50_screen_init_resource_functions(pscreen);
321 nouveau_screen_init_vdec(&screen->base);
323 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
327 nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
328 screen->fence.map = screen->fence.bo->map;
329 nouveau_bo_unmap(screen->fence.bo);
330 screen->base.fence.emit = nv50_screen_fence_emit;
331 screen->base.fence.update = nv50_screen_fence_update;
333 ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
335 FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret);
337 ret = nouveau_grobj_alloc(chan, 0xbeef5039, NV50_M2MF, &screen->m2mf);
339 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
341 BIND_RING (chan, screen->m2mf, NV50_SUBCH_MF);
342 BEGIN_RING(chan, RING_MF_(NV04_M2MF_DMA_NOTIFY), 3);
343 OUT_RING (chan, screen->sync->handle);
344 OUT_RING (chan, chan->vram->handle);
345 OUT_RING (chan, chan->vram->handle);
347 ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
349 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
351 BIND_RING (chan, screen->eng2d, NV50_SUBCH_2D);
352 BEGIN_RING(chan, RING_2D(DMA_NOTIFY), 4);
353 OUT_RING (chan, screen->sync->handle);
354 OUT_RING (chan, chan->vram->handle);
355 OUT_RING (chan, chan->vram->handle);
356 OUT_RING (chan, chan->vram->handle);
357 BEGIN_RING(chan, RING_2D(OPERATION), 1);
358 OUT_RING (chan, NV50_2D_OPERATION_SRCCOPY);
359 BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
361 BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
363 BEGIN_RING(chan, RING_2D_(0x0888), 1);
366 switch (dev->chipset & 0xf0) {
368 tesla_class = NV50_3D;
372 tesla_class = NV84_3D;
375 switch (dev->chipset) {
379 tesla_class = NVA0_3D;
382 tesla_class = NVAF_3D;
385 tesla_class = NVA3_3D;
390 FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset);
394 ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla);
396 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
398 BIND_RING (chan, screen->tesla, NV50_SUBCH_3D);
400 BEGIN_RING(chan, RING_3D(COND_MODE), 1);
401 OUT_RING (chan, NV50_3D_COND_MODE_ALWAYS);
403 BEGIN_RING(chan, RING_3D(DMA_NOTIFY), 1);
404 OUT_RING (chan, screen->sync->handle);
405 BEGIN_RING(chan, RING_3D(DMA_ZETA), 11);
406 for (i = 0; i < 11; ++i)
407 OUT_RING(chan, chan->vram->handle);
408 BEGIN_RING(chan, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
409 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
410 OUT_RING(chan, chan->vram->handle);
412 BEGIN_RING(chan, RING_3D(REG_MODE), 1);
413 OUT_RING (chan, NV50_3D_REG_MODE_STRIPED);
414 BEGIN_RING(chan, RING_3D(UNK1400_LANES), 1);
415 OUT_RING (chan, 0xf);
417 BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
420 BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
422 BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
424 BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
425 OUT_RING (chan, NV50_3D_MULTISAMPLE_MODE_MS1);
426 BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
428 BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
430 BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
433 if (tesla_class >= NVA0_3D) {
434 BEGIN_RING(chan, RING_3D_(NVA0_3D_TEX_MISC), 1);
435 OUT_RING (chan, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
438 BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
440 BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
443 BEGIN_RING(chan, RING_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
444 OUT_RING (chan, 0x3f);
446 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
447 3 << NV50_CODE_BO_SIZE_LOG2, &screen->code);
451 nouveau_resource_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
452 nouveau_resource_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
453 nouveau_resource_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
455 base = 1 << NV50_CODE_BO_SIZE_LOG2;
457 BEGIN_RING(chan, RING_3D(VP_ADDRESS_HIGH), 2);
458 OUT_RELOCh(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
459 OUT_RELOCl(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
461 BEGIN_RING(chan, RING_3D(FP_ADDRESS_HIGH), 2);
462 OUT_RELOCh(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
463 OUT_RELOCl(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
465 BEGIN_RING(chan, RING_3D(GP_ADDRESS_HIGH), 2);
466 OUT_RELOCh(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
467 OUT_RELOCl(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
469 nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
471 max_warps = util_bitcount(value & 0xffff);
472 max_warps *= util_bitcount((value >> 24) & 0xf) * 32;
474 stack_size = max_warps * 64 * 8;
476 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size,
479 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
481 BEGIN_RING(chan, RING_3D(STACK_ADDRESS_HIGH), 3);
482 OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
483 OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
486 tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16;
488 screen->tls_size = tls_space * max_warps * 32;
490 debug_printf("max_warps = %i, tls_size = %llu KiB\n",
491 max_warps, screen->tls_size >> 10);
493 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size,
496 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
498 BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3);
499 OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
500 OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
501 OUT_RING (chan, util_logbase2(tls_space / 8));
503 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16,
508 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
509 OUT_RELOCh(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
510 OUT_RELOCl(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
511 OUT_RING (chan, (NV50_CB_PVP << 16) | 0x0000);
513 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
514 OUT_RELOCh(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
515 OUT_RELOCl(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
516 OUT_RING (chan, (NV50_CB_PGP << 16) | 0x0000);
518 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
519 OUT_RELOCh(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
520 OUT_RELOCl(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
521 OUT_RING (chan, (NV50_CB_PFP << 16) | 0x0000);
523 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
524 OUT_RELOCh(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
525 OUT_RELOCl(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
526 OUT_RING (chan, (NV50_CB_AUX << 16) | 0x0200);
528 BEGIN_RING_NI(chan, RING_3D(SET_PROGRAM_CB), 6);
529 OUT_RING (chan, (NV50_CB_PVP << 12) | 0x001);
530 OUT_RING (chan, (NV50_CB_PGP << 12) | 0x021);
531 OUT_RING (chan, (NV50_CB_PFP << 12) | 0x031);
532 OUT_RING (chan, (NV50_CB_AUX << 12) | 0xf01);
533 OUT_RING (chan, (NV50_CB_AUX << 12) | 0xf21);
534 OUT_RING (chan, (NV50_CB_AUX << 12) | 0xf31);
536 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16,
539 FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret);
541 /* max TIC (bits 4:8) & TSC bindings, per program type */
542 for (i = 0; i < 3; ++i) {
543 BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
544 OUT_RING (chan, 0x54);
547 BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
548 OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
549 OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
550 OUT_RING (chan, NV50_TIC_MAX_ENTRIES - 1);
552 BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
553 OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
554 OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
555 OUT_RING (chan, NV50_TSC_MAX_ENTRIES - 1);
557 BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
560 BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
562 BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
563 OUT_RING (chan, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
564 BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
565 for (i = 0; i < 8 * 2; ++i)
567 BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
570 BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
572 BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
573 OUT_RINGf (chan, 0.0f);
574 OUT_RINGf (chan, 1.0f);
576 BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
577 #ifdef NV50_SCISSORS_CLIPPING
578 OUT_RING (chan, 0x0000);
580 OUT_RING (chan, 0x1080);
583 BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
584 OUT_RING (chan, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
586 /* We use scissors instead of exact view volume clipping,
587 * so they're always enabled.
589 BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
591 OUT_RING (chan, 8192 << 16);
592 OUT_RING (chan, 8192 << 16);
594 BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
596 BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
597 OUT_RING (chan, NV50_3D_POINT_RASTER_RULES_OGL);
598 BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1);
599 OUT_RING (chan, 0x11111111);
600 BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
605 screen->tic.entries = CALLOC(4096, sizeof(void *));
606 screen->tsc.entries = screen->tic.entries + 2048;
608 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
610 if (!nv50_blitctx_create(screen))
613 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
618 nv50_screen_destroy(pscreen);
623 nv50_screen_make_buffers_resident(struct nv50_screen *screen)
625 struct nouveau_channel *chan = screen->base.channel;
627 const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
629 MARK_RING(chan, 5, 5);
630 nouveau_bo_validate(chan, screen->code, flags);
631 nouveau_bo_validate(chan, screen->uniforms, flags);
632 nouveau_bo_validate(chan, screen->txc, flags);
633 nouveau_bo_validate(chan, screen->tls_bo, flags);
634 nouveau_bo_validate(chan, screen->stack_bo, flags);
638 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
640 int i = screen->tic.next;
642 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
643 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
645 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
647 if (screen->tic.entries[i])
648 nv50_tic_entry(screen->tic.entries[i])->id = -1;
650 screen->tic.entries[i] = entry;
655 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
657 int i = screen->tsc.next;
659 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
660 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
662 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
664 if (screen->tsc.entries[i])
665 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
667 screen->tsc.entries[i] = entry;