2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "util/u_inlines.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
32 #include "nv50_context.h"
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
40 /* ARL - gallium craps itself on progs/vp/arl.txt
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
96 int vtx; /* vertex index, for GP inputs (TGSI Dimension.Index) */
97 int indirect[2]; /* index into pc->addr, or -1 */
99 ubyte buf_index; /* c{0 .. 15}[] or g{0 .. 15}[] */
102 #define NV50_MOD_NEG 1
103 #define NV50_MOD_ABS 2
104 #define NV50_MOD_NEG_ABS (NV50_MOD_NEG | NV50_MOD_ABS)
105 #define NV50_MOD_SAT 4
106 #define NV50_MOD_I32 8
108 /* NV50_MOD_I32 is used to indicate integer mode for neg/abs */
110 /* STACK: Conditionals and loops have to use the (per warp) stack.
111 * Stack entries consist of an entry type (divergent path, join at),
112 * a mask indicating the active threads of the warp, and an address.
113 * MPs can store 12 stack entries internally, if we need more (and
114 * we probably do), we have to create a stack buffer in VRAM.
116 /* impose low limits for now */
117 #define NV50_MAX_COND_NESTING 4
118 #define NV50_MAX_LOOP_NESTING 3
120 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
123 struct nv50_program *p;
126 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
127 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
130 struct nv50_reg *temp;
132 struct nv50_reg *attr;
134 struct nv50_reg *result;
136 struct nv50_reg *param;
138 struct nv50_reg *immd;
141 struct nv50_reg **addr;
143 struct nv50_reg *sysval;
146 struct nv50_reg *temp_temp[16];
147 struct nv50_program_exec *temp_temp_exec[16];
148 unsigned temp_temp_nr;
150 /* broadcast and destination replacement regs */
151 struct nv50_reg *r_brdc;
152 struct nv50_reg *r_dst[4];
154 struct nv50_reg reg_instances[16];
155 unsigned reg_instance_nr;
157 unsigned interp_mode[32];
158 /* perspective interpolation registers */
159 struct nv50_reg *iv_p;
160 struct nv50_reg *iv_c;
162 struct nv50_program_exec *if_insn[NV50_MAX_COND_NESTING];
163 struct nv50_program_exec *if_join[NV50_MAX_COND_NESTING];
164 struct nv50_program_exec *loop_brka[NV50_MAX_LOOP_NESTING];
165 int if_lvl, loop_lvl;
166 unsigned loop_pos[NV50_MAX_LOOP_NESTING];
168 unsigned *insn_pos; /* actual program offset of each TGSI insn */
169 boolean in_subroutine;
171 /* current instruction and total number of insns */
177 uint8_t edgeflag_out;
180 static struct nv50_reg *get_address_reg(struct nv50_pc *, struct nv50_reg *);
183 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
192 reg->indirect[0] = reg->indirect[1] = -1;
193 reg->buf_index = (type == P_CONST) ? 1 : 0;
196 static INLINE unsigned
197 popcnt4(uint32_t val)
199 static const unsigned cnt[16]
200 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
201 return cnt[val & 0xf];
205 terminate_mbb(struct nv50_pc *pc)
209 /* remove records of temporary address register values */
210 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
211 if (pc->r_addr[i].index < 0)
212 pc->r_addr[i].acc = 0;
216 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
220 if (reg->type == P_RESULT) {
221 if (pc->p->cfg.high_result < (reg->hw + 1))
222 pc->p->cfg.high_result = reg->hw + 1;
225 if (reg->type != P_TEMP)
229 /*XXX: do this here too to catch FP temp-as-attr usage..
230 * not clean, but works */
231 if (pc->p->cfg.high_temp < (reg->hw + 1))
232 pc->p->cfg.high_temp = reg->hw + 1;
236 if (reg->rhw != -1) {
237 /* try to allocate temporary with index rhw first */
238 if (!(pc->r_temp[reg->rhw])) {
239 pc->r_temp[reg->rhw] = reg;
241 if (pc->p->cfg.high_temp < (reg->rhw + 1))
242 pc->p->cfg.high_temp = reg->rhw + 1;
245 /* make sure we don't get things like $r0 needs to go
246 * in $r1 and $r1 in $r0
248 i = pc->result_nr * 4;
251 for (; i < NV50_SU_MAX_TEMP; i++) {
252 if (!(pc->r_temp[i])) {
255 if (pc->p->cfg.high_temp < (i + 1))
256 pc->p->cfg.high_temp = i + 1;
261 NOUVEAU_ERR("out of registers\n");
265 static INLINE struct nv50_reg *
266 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
270 assert(pc->reg_instance_nr < 16);
271 ri = &pc->reg_instances[pc->reg_instance_nr++];
275 reg->indirect[0] = reg->indirect[1] = -1;
281 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
282 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
283 * lest we risk temp_temps overwriting regs alloc'd "later".
285 static struct nv50_reg *
286 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
291 if (dst && dst->type == P_TEMP && dst->hw == -1)
294 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
295 if (!pc->r_temp[i]) {
296 r = MALLOC_STRUCT(nv50_reg);
297 ctor_reg(r, P_TEMP, -1, i);
303 NOUVEAU_ERR("out of registers\n");
308 /* release the hardware resource held by r */
310 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
312 assert(r->type == P_TEMP);
316 assert(pc->r_temp[r->hw] == r);
317 pc->r_temp[r->hw] = NULL;
325 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
327 if (r->index == -1) {
330 FREE(pc->r_temp[hw]);
331 pc->r_temp[hw] = NULL;
336 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
340 if ((idx + 4) >= NV50_SU_MAX_TEMP)
343 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
344 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
345 return alloc_temp4(pc, dst, idx + 4);
347 for (i = 0; i < 4; i++) {
348 dst[i] = MALLOC_STRUCT(nv50_reg);
349 ctor_reg(dst[i], P_TEMP, -1, idx + i);
350 pc->r_temp[idx + i] = dst[i];
357 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
361 for (i = 0; i < 4; i++)
362 free_temp(pc, reg[i]);
365 static struct nv50_reg *
366 temp_temp(struct nv50_pc *pc, struct nv50_program_exec *e)
368 if (pc->temp_temp_nr >= 16)
371 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
372 pc->temp_temp_exec[pc->temp_temp_nr] = e;
373 return pc->temp_temp[pc->temp_temp_nr++];
376 /* This *must* be called for all nv50_program_exec that have been
377 * given as argument to temp_temp, or the temps will be leaked !
380 kill_temp_temp(struct nv50_pc *pc, struct nv50_program_exec *e)
384 for (i = 0; i < pc->temp_temp_nr; i++)
385 if (pc->temp_temp_exec[i] == e)
386 free_temp(pc, pc->temp_temp[i]);
388 pc->temp_temp_nr = 0;
392 ctor_immd_4u32(struct nv50_pc *pc,
393 uint32_t x, uint32_t y, uint32_t z, uint32_t w)
395 unsigned size = pc->immd_nr * 4 * sizeof(uint32_t);
397 pc->immd_buf = REALLOC(pc->immd_buf, size, size + 4 * sizeof(uint32_t));
399 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
400 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
401 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
402 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
404 return pc->immd_nr++;
408 ctor_immd_4f32(struct nv50_pc *pc, float x, float y, float z, float w)
410 return ctor_immd_4u32(pc, fui(x), fui(y), fui(z), fui(w));
413 static struct nv50_reg *
414 alloc_immd(struct nv50_pc *pc, float f)
416 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
419 for (hw = 0; hw < pc->immd_nr * 4; hw++)
420 if (pc->immd_buf[hw] == fui(f))
423 if (hw == pc->immd_nr * 4)
424 hw = ctor_immd_4f32(pc, f, -f, 0.5 * f, 0) * 4;
426 ctor_reg(r, P_IMMD, -1, hw);
430 static struct nv50_program_exec *
431 exec(struct nv50_pc *pc)
433 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
440 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
442 struct nv50_program *p = pc->p;
445 p->exec_tail->next = e;
449 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
451 kill_temp_temp(pc, e);
454 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
457 is_long(struct nv50_program_exec *e)
465 is_immd(struct nv50_program_exec *e)
467 if (is_long(e) && (e->inst[1] & 3) == 3)
473 is_join(struct nv50_program_exec *e)
475 if (is_long(e) && (e->inst[1] & 3) == 2)
480 static INLINE boolean
481 is_control_flow(struct nv50_program_exec *e)
483 return (e->inst[0] & 2);
487 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
488 struct nv50_program_exec *e)
492 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
493 e->inst[1] |= (pred << 7) | (idx << 12);
497 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
498 struct nv50_program_exec *e)
501 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
502 e->inst[1] |= (idx << 4) | (on << 6);
506 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
512 set_pred(pc, 0xf, 0, e);
513 set_pred_wr(pc, 0, 0, e);
517 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
519 if (dst->type == P_RESULT) {
521 e->inst[1] |= 0x00000008;
527 e->inst[0] |= (dst->hw << 2);
531 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
534 /* XXX: can't be predicated - bits overlap; cases where both
535 * are required should be avoided by using pc->allow32 */
536 set_pred(pc, 0, 0, e);
537 set_pred_wr(pc, 0, 0, e);
539 e->inst[1] |= 0x00000002 | 0x00000001;
540 e->inst[0] |= (pc->immd_buf[imm->hw] & 0x3f) << 16;
541 e->inst[1] |= (pc->immd_buf[imm->hw] >> 6) << 2;
545 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
547 assert(a->type == P_ADDR);
549 assert(!(e->inst[0] & 0x0c000000));
550 assert(!(e->inst[1] & 0x00000004));
552 e->inst[0] |= (a->hw & 3) << 26;
553 e->inst[1] |= a->hw & 4;
557 emit_arl(struct nv50_pc *, struct nv50_reg *, struct nv50_reg *, uint8_t);
560 emit_shl_imm(struct nv50_pc *, struct nv50_reg *, struct nv50_reg *, int);
563 emit_mov_from_addr(struct nv50_pc *pc, struct nv50_reg *dst,
564 struct nv50_reg *src)
566 struct nv50_program_exec *e = exec(pc);
568 e->inst[1] = 0x40000000;
577 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
578 struct nv50_reg *src0, uint16_t src1_val)
580 struct nv50_program_exec *e = exec(pc);
582 e->inst[0] = 0xd0000000 | (src1_val << 9);
583 e->inst[1] = 0x20000000;
585 e->inst[0] |= dst->hw << 2;
586 if (src0) /* otherwise will add to $a0, which is always 0 */
592 #define INTERP_LINEAR 0
593 #define INTERP_FLAT 1
594 #define INTERP_PERSPECTIVE 2
595 #define INTERP_CENTROID 4
597 /* interpolant index has been stored in dst->rhw */
599 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
602 assert(dst->rhw != -1);
603 struct nv50_program_exec *e = exec(pc);
605 e->inst[0] |= 0x80000000;
607 e->inst[0] |= (dst->rhw << 16);
609 if (mode & INTERP_FLAT) {
610 e->inst[0] |= (1 << 8);
612 if (mode & INTERP_PERSPECTIVE) {
613 e->inst[0] |= (1 << 25);
615 e->inst[0] |= (iv->hw << 9);
618 if (mode & INTERP_CENTROID)
619 e->inst[0] |= (1 << 24);
626 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
627 struct nv50_program_exec *e)
631 e->param.index = src->hw & 127;
633 e->param.mask = m << (s % 32);
635 if (src->hw < 0 || src->hw > 127) /* need (additional) address reg */
636 set_addr(e, get_address_reg(pc, src));
639 assert(src->type == P_CONST);
640 set_addr(e, pc->addr[src->indirect[0]]);
643 e->inst[1] |= (src->buf_index << 22);
646 /* Never apply nv50_reg::mod in emit_mov, or carefully check the code !!! */
648 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
650 struct nv50_program_exec *e = exec(pc);
652 e->inst[0] = 0x10000000;
658 if (!is_long(e) && src->type == P_IMMD) {
659 set_immd(pc, src, e);
660 /*XXX: 32-bit, but steals part of "half" reg space - need to
661 * catch and handle this case if/when we do half-regs
664 if (src->type == P_IMMD || src->type == P_CONST) {
666 set_data(pc, src, 0x7f, 9, e);
667 e->inst[1] |= 0x20000000; /* mov from c[] */
669 if (src->type == P_ATTR) {
671 e->inst[1] |= 0x00200000;
674 /* indirect (vertex base + c) load from p[] */
675 e->inst[0] |= 0x01800000;
676 set_addr(e, get_address_reg(pc, src));
683 e->inst[0] |= (src->hw << 9);
686 if (is_long(e) && !is_immd(e)) {
687 e->inst[1] |= 0x04000000; /* 32-bit */
688 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
689 if (!(e->inst[1] & 0x20000000))
690 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
692 e->inst[0] |= 0x00008000;
698 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
700 struct nv50_reg *imm = alloc_immd(pc, f);
701 emit_mov(pc, dst, imm);
705 /* Assign the hw of the discarded temporary register src
706 * to the tgsi register dst and free src.
709 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
711 assert(src->index == -1 && src->hw != -1);
713 if (pc->if_lvl || pc->loop_lvl ||
714 (dst->type != P_TEMP) ||
715 (src->hw < pc->result_nr * 4 &&
716 pc->p->type == PIPE_SHADER_FRAGMENT) ||
717 pc->p->info.opcode_count[TGSI_OPCODE_CAL] ||
718 pc->p->info.opcode_count[TGSI_OPCODE_BRA]) {
720 emit_mov(pc, dst, src);
726 pc->r_temp[dst->hw] = NULL;
727 pc->r_temp[src->hw] = dst;
734 emit_nop(struct nv50_pc *pc)
736 struct nv50_program_exec *e = exec(pc);
738 e->inst[0] = 0xf0000000;
740 e->inst[1] = 0xe0000000;
745 check_swap_src_0_1(struct nv50_pc *pc,
746 struct nv50_reg **s0, struct nv50_reg **s1)
748 struct nv50_reg *src0 = *s0, *src1 = *s1;
750 if (src0->type == P_CONST) {
751 if (src1->type != P_CONST) {
757 if (src1->type == P_ATTR) {
758 if (src0->type != P_ATTR) {
769 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
770 struct nv50_program_exec *e)
772 struct nv50_reg *temp;
774 if (src->type != P_TEMP) {
775 temp = temp_temp(pc, e);
776 emit_mov(pc, temp, src);
783 e->inst[0] |= (src->hw << 9);
787 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
789 if (src->type == P_ATTR) {
791 e->inst[1] |= 0x00200000;
794 e->inst[0] |= 0x01800000; /* src from p[] */
795 set_addr(e, get_address_reg(pc, src));
798 if (src->type == P_CONST || src->type == P_IMMD) {
799 struct nv50_reg *temp = temp_temp(pc, e);
801 emit_mov(pc, temp, src);
808 e->inst[0] |= (src->hw << 9);
812 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
814 if (src->type == P_ATTR) {
815 struct nv50_reg *temp = temp_temp(pc, e);
817 emit_mov(pc, temp, src);
820 if (src->type == P_CONST || src->type == P_IMMD) {
821 if (e->inst[0] & 0x01800000) {
822 struct nv50_reg *temp = temp_temp(pc, e);
824 emit_mov(pc, temp, src);
827 assert(!(e->inst[0] & 0x00800000));
828 set_data(pc, src, 0x7f, 16, e);
829 e->inst[0] |= 0x00800000;
836 e->inst[0] |= ((src->hw & 127) << 16);
840 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
844 if (src->type == P_ATTR) {
845 struct nv50_reg *temp = temp_temp(pc, e);
847 emit_mov(pc, temp, src);
850 if (src->type == P_CONST || src->type == P_IMMD) {
851 if (e->inst[0] & 0x01800000) {
852 struct nv50_reg *temp = temp_temp(pc, e);
854 emit_mov(pc, temp, src);
857 assert(!(e->inst[0] & 0x01000000));
858 set_data(pc, src, 0x7f, 32+14, e);
859 e->inst[0] |= 0x01000000;
864 e->inst[1] |= ((src->hw & 127) << 14);
868 set_half_src(struct nv50_pc *pc, struct nv50_reg *src, int lh,
869 struct nv50_program_exec *e, int pos)
871 struct nv50_reg *r = src;
874 if (r->type != P_TEMP) {
875 r = temp_temp(pc, e);
876 emit_mov(pc, r, src);
879 if (r->hw > (NV50_SU_MAX_TEMP / 2)) {
880 NOUVEAU_ERR("out of low GPRs\n");
884 e->inst[pos / 32] |= ((src->hw * 2) + lh) << (pos % 32);
888 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
890 struct nv50_program_exec *e = exec(pc);
892 assert(dst->type == P_TEMP);
893 e->inst[1] = 0x20000000 | (pred << 12);
901 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
903 struct nv50_program_exec *e = exec(pc);
905 e->inst[0] = 0x000001fc;
906 e->inst[1] = 0xa0000008;
908 set_pred_wr(pc, 1, pred, e);
909 set_src_0_restricted(pc, src, e);
915 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
916 struct nv50_reg *src1)
918 struct nv50_program_exec *e = exec(pc);
920 e->inst[0] |= 0xc0000000;
925 check_swap_src_0_1(pc, &src0, &src1);
927 set_src_0(pc, src0, e);
928 if (src1->type == P_IMMD && !is_long(e)) {
929 if (src0->mod ^ src1->mod)
930 e->inst[0] |= 0x00008000;
931 set_immd(pc, src1, e);
933 set_src_1(pc, src1, e);
934 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
936 e->inst[1] |= 0x08000000;
938 e->inst[0] |= 0x00008000;
946 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
947 struct nv50_reg *src0, struct nv50_reg *src1)
949 struct nv50_program_exec *e = exec(pc);
951 e->inst[0] = 0xb0000000;
954 check_swap_src_0_1(pc, &src0, &src1);
956 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
958 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
959 ((src1->mod & NV50_MOD_NEG) << 27);
963 set_src_0(pc, src0, e);
964 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
965 set_src_2(pc, src1, e);
967 if (src1->type == P_IMMD)
968 set_immd(pc, src1, e);
970 set_src_1(pc, src1, e);
976 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
979 struct nv50_program_exec *e = exec(pc);
982 e->inst[1] |= 0xc0000000;
984 e->inst[0] |= dst->hw << 2;
985 e->inst[0] |= s << 16; /* shift left */
986 set_src_0(pc, src, e);
992 address_reg_suitable(struct nv50_reg *a, struct nv50_reg *r)
997 if (r->vtx != a->vtx)
1000 return (r->indirect[1] == a->indirect[1]);
1002 if (r->hw < a->rhw || (r->hw - a->rhw) >= 128)
1006 return (a->index == r->indirect[0]);
1007 return (a->indirect[0] == r->indirect[0]);
1011 load_vertex_base(struct nv50_pc *pc, struct nv50_reg *dst,
1012 struct nv50_reg *a, int shift)
1014 struct nv50_reg mem, *temp;
1016 ctor_reg(&mem, P_ATTR, -1, dst->vtx);
1018 assert(dst->type == P_ADDR);
1020 emit_arl(pc, dst, &mem, 0);
1023 temp = alloc_temp(pc, NULL);
1026 emit_mov_from_addr(pc, temp, a);
1028 emit_shl_imm(pc, temp, temp, shift);
1029 emit_arl(pc, dst, temp, MAX2(shift, 0));
1031 emit_mov(pc, temp, &mem);
1032 set_addr(pc->p->exec_tail, dst);
1034 emit_arl(pc, dst, temp, 0);
1035 free_temp(pc, temp);
1038 /* case (ref == NULL): allocate address register for TGSI_FILE_ADDRESS
1039 * case (vtx >= 0, acc >= 0): load vertex base from a[vtx * 4] to $aX
1040 * case (vtx >= 0, acc < 0): load vertex base from s[$aY + vtx * 4] to $aX
1041 * case (vtx < 0, acc >= 0): memory address too high to encode
1042 * case (vtx < 0, acc < 0): get source register for TGSI_FILE_ADDRESS
1044 static struct nv50_reg *
1045 get_address_reg(struct nv50_pc *pc, struct nv50_reg *ref)
1048 struct nv50_reg *a_ref, *a = NULL;
1050 for (i = 0; i < NV50_SU_MAX_ADDR; ++i) {
1051 if (pc->r_addr[i].acc == 0)
1052 a = &pc->r_addr[i]; /* an unused address reg */
1054 if (address_reg_suitable(&pc->r_addr[i], ref)) {
1055 pc->r_addr[i].acc = pc->insn_cur;
1056 return &pc->r_addr[i];
1058 if (!a && pc->r_addr[i].index < 0 &&
1059 pc->r_addr[i].acc < pc->insn_cur)
1063 /* We'll be able to spill address regs when this
1064 * mess is replaced with a proper compiler ...
1066 NOUVEAU_ERR("out of address regs\n");
1071 /* initialize and reserve for this TGSI instruction */
1073 a->index = a->indirect[0] = a->indirect[1] = -1;
1074 a->acc = pc->insn_cur;
1082 /* now put in the correct value ... */
1084 if (ref->vtx >= 0) {
1085 a->indirect[1] = ref->indirect[1];
1087 /* For an indirect vertex index, we need to shift address right
1088 * by 2, the address register will contain vtx * 16, we need to
1089 * load from a[vtx * 4].
1091 load_vertex_base(pc, a, (ref->acc < 0) ?
1092 pc->addr[ref->indirect[1]] : NULL, -2);
1094 assert(ref->acc < 0 || ref->indirect[0] < 0);
1096 a->rhw = ref->hw & ~0x7f;
1097 a->indirect[0] = ref->indirect[0];
1098 a_ref = (ref->acc < 0) ? pc->addr[ref->indirect[0]] : NULL;
1100 emit_add_addr_imm(pc, a, a_ref, a->rhw * 4);
1105 #define NV50_MAX_F32 0x880
1106 #define NV50_MAX_S32 0x08c
1107 #define NV50_MAX_U32 0x084
1108 #define NV50_MIN_F32 0x8a0
1109 #define NV50_MIN_S32 0x0ac
1110 #define NV50_MIN_U32 0x0a4
1113 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
1114 struct nv50_reg *src0, struct nv50_reg *src1)
1116 struct nv50_program_exec *e = exec(pc);
1119 e->inst[0] |= 0x30000000 | ((sub & 0x800) << 20);
1120 e->inst[1] |= (sub << 24);
1122 check_swap_src_0_1(pc, &src0, &src1);
1123 set_dst(pc, dst, e);
1124 set_src_0(pc, src0, e);
1125 set_src_1(pc, src1, e);
1127 if (src0->mod & NV50_MOD_ABS)
1128 e->inst[1] |= 0x00100000;
1129 if (src1->mod & NV50_MOD_ABS)
1130 e->inst[1] |= 0x00080000;
1136 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1137 struct nv50_reg *src1)
1139 src1->mod ^= NV50_MOD_NEG;
1140 emit_add(pc, dst, src0, src1);
1141 src1->mod ^= NV50_MOD_NEG;
1145 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1146 struct nv50_reg *src1, unsigned op)
1148 struct nv50_program_exec *e = exec(pc);
1150 e->inst[0] = 0xd0000000;
1153 check_swap_src_0_1(pc, &src0, &src1);
1154 set_dst(pc, dst, e);
1155 set_src_0(pc, src0, e);
1157 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
1158 op != TGSI_OPCODE_XOR)
1159 assert(!"invalid bit op");
1161 assert(!(src0->mod | src1->mod));
1163 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
1164 set_immd(pc, src1, e);
1165 if (op == TGSI_OPCODE_OR)
1166 e->inst[0] |= 0x0100;
1168 if (op == TGSI_OPCODE_XOR)
1169 e->inst[0] |= 0x8000;
1171 set_src_1(pc, src1, e);
1172 e->inst[1] |= 0x04000000; /* 32 bit */
1173 if (op == TGSI_OPCODE_OR)
1174 e->inst[1] |= 0x4000;
1176 if (op == TGSI_OPCODE_XOR)
1177 e->inst[1] |= 0x8000;
1184 emit_not(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1186 struct nv50_program_exec *e = exec(pc);
1188 e->inst[0] = 0xd0000000;
1189 e->inst[1] = 0x0402c000;
1191 set_dst(pc, dst, e);
1192 set_src_1(pc, src, e);
1198 emit_shift(struct nv50_pc *pc, struct nv50_reg *dst,
1199 struct nv50_reg *src0, struct nv50_reg *src1, unsigned dir)
1201 struct nv50_program_exec *e = exec(pc);
1203 e->inst[0] = 0x30000000;
1204 e->inst[1] = 0xc4000000;
1207 set_dst(pc, dst, e);
1208 set_src_0(pc, src0, e);
1210 if (src1->type == P_IMMD) {
1211 e->inst[1] |= (1 << 20);
1212 e->inst[0] |= (pc->immd_buf[src1->hw] & 0x7f) << 16;
1214 set_src_1(pc, src1, e);
1216 if (dir != TGSI_OPCODE_SHL)
1217 e->inst[1] |= (1 << 29);
1219 if (dir == TGSI_OPCODE_ISHR)
1220 e->inst[1] |= (1 << 27);
1226 emit_shl_imm(struct nv50_pc *pc, struct nv50_reg *dst,
1227 struct nv50_reg *src, int s)
1229 struct nv50_program_exec *e = exec(pc);
1231 e->inst[0] = 0x30000000;
1232 e->inst[1] = 0xc4100000;
1234 e->inst[1] |= 1 << 29;
1237 e->inst[1] |= ((s & 0x7f) << 16);
1240 set_dst(pc, dst, e);
1241 set_src_0(pc, src, e);
1247 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1248 struct nv50_reg *src1, struct nv50_reg *src2)
1250 struct nv50_program_exec *e = exec(pc);
1252 e->inst[0] |= 0xe0000000;
1254 check_swap_src_0_1(pc, &src0, &src1);
1255 set_dst(pc, dst, e);
1256 set_src_0(pc, src0, e);
1257 set_src_1(pc, src1, e);
1258 set_src_2(pc, src2, e);
1260 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1261 e->inst[1] |= 0x04000000;
1262 if (src2->mod & NV50_MOD_NEG)
1263 e->inst[1] |= 0x08000000;
1269 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1270 struct nv50_reg *src1, struct nv50_reg *src2)
1272 src2->mod ^= NV50_MOD_NEG;
1273 emit_mad(pc, dst, src0, src1, src2);
1274 src2->mod ^= NV50_MOD_NEG;
1277 #define NV50_FLOP_RCP 0
1278 #define NV50_FLOP_RSQ 2
1279 #define NV50_FLOP_LG2 3
1280 #define NV50_FLOP_SIN 4
1281 #define NV50_FLOP_COS 5
1282 #define NV50_FLOP_EX2 6
1284 /* rcp, rsqrt, lg2 support neg and abs */
1286 emit_flop(struct nv50_pc *pc, unsigned sub,
1287 struct nv50_reg *dst, struct nv50_reg *src)
1289 struct nv50_program_exec *e = exec(pc);
1291 e->inst[0] |= 0x90000000;
1292 if (sub || src->mod) {
1294 e->inst[1] |= (sub << 29);
1297 set_dst(pc, dst, e);
1298 set_src_0_restricted(pc, src, e);
1300 assert(!src->mod || sub < 4);
1302 if (src->mod & NV50_MOD_NEG)
1303 e->inst[1] |= 0x04000000;
1304 if (src->mod & NV50_MOD_ABS)
1305 e->inst[1] |= 0x00100000;
1311 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1313 struct nv50_program_exec *e = exec(pc);
1315 e->inst[0] |= 0xb0000000;
1317 set_dst(pc, dst, e);
1318 set_src_0(pc, src, e);
1320 e->inst[1] |= (6 << 29) | 0x00004000;
1322 if (src->mod & NV50_MOD_NEG)
1323 e->inst[1] |= 0x04000000;
1324 if (src->mod & NV50_MOD_ABS)
1325 e->inst[1] |= 0x00100000;
1331 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1333 struct nv50_program_exec *e = exec(pc);
1335 e->inst[0] |= 0xb0000000;
1337 set_dst(pc, dst, e);
1338 set_src_0(pc, src, e);
1340 e->inst[1] |= (6 << 29);
1342 if (src->mod & NV50_MOD_NEG)
1343 e->inst[1] |= 0x04000000;
1344 if (src->mod & NV50_MOD_ABS)
1345 e->inst[1] |= 0x00100000;
1350 #define CVT_RN (0x00 << 16)
1351 #define CVT_FLOOR (0x02 << 16)
1352 #define CVT_CEIL (0x04 << 16)
1353 #define CVT_TRUNC (0x06 << 16)
1354 #define CVT_SAT (0x08 << 16)
1355 #define CVT_ABS (0x10 << 16)
1357 #define CVT_X32_X32 0x04004000
1358 #define CVT_X32_S32 0x04014000
1359 #define CVT_F32_F32 ((0xc0 << 24) | CVT_X32_X32)
1360 #define CVT_S32_F32 ((0x88 << 24) | CVT_X32_X32)
1361 #define CVT_U32_F32 ((0x80 << 24) | CVT_X32_X32)
1362 #define CVT_F32_S32 ((0x40 << 24) | CVT_X32_S32)
1363 #define CVT_F32_U32 ((0x40 << 24) | CVT_X32_X32)
1364 #define CVT_S32_S32 ((0x08 << 24) | CVT_X32_S32)
1365 #define CVT_S32_U32 ((0x08 << 24) | CVT_X32_X32)
1366 #define CVT_U32_S32 ((0x00 << 24) | CVT_X32_S32)
1368 #define CVT_NEG 0x20000000
1369 #define CVT_RI 0x08000000
1372 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1373 int wp, uint32_t cvn)
1375 struct nv50_program_exec *e;
1379 if (src->mod & NV50_MOD_NEG) cvn |= CVT_NEG;
1380 if (src->mod & NV50_MOD_ABS) cvn |= CVT_ABS;
1382 e->inst[0] = 0xa0000000;
1385 set_src_0(pc, src, e);
1388 set_pred_wr(pc, 1, wp, e);
1391 set_dst(pc, dst, e);
1393 e->inst[0] |= 0x000001fc;
1394 e->inst[1] |= 0x00000008;
1400 /* nv50 Condition codes:
1407 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1408 * 0x8 = unordered bit (allows NaN)
1410 * mode = 0x04 (u32), 0x0c (s32), 0x80 (f32)
1413 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1414 struct nv50_reg *src0, struct nv50_reg *src1, uint8_t mode)
1416 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1418 struct nv50_program_exec *e = exec(pc);
1419 struct nv50_reg *rdst;
1422 if (check_swap_src_0_1(pc, &src0, &src1))
1423 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1426 if (dst && dst->type != P_TEMP)
1427 dst = alloc_temp(pc, NULL);
1430 e->inst[0] |= 0x30000000 | (mode << 24);
1431 e->inst[1] |= 0x60000000 | (ccode << 14);
1434 set_pred_wr(pc, 1, wp, e);
1436 set_dst(pc, dst, e);
1438 e->inst[0] |= 0x000001fc;
1439 e->inst[1] |= 0x00000008;
1442 set_src_0(pc, src0, e);
1443 set_src_1(pc, src1, e);
1447 if (rdst && mode == 0x80) /* convert to float ? */
1448 emit_cvt(pc, rdst, dst, -1, CVT_ABS | CVT_F32_S32);
1449 if (rdst && rdst != dst)
1454 map_tgsi_setop_hw(unsigned op, uint8_t *cc, uint8_t *ty)
1457 case TGSI_OPCODE_SLT: *cc = 0x1; *ty = 0x80; break;
1458 case TGSI_OPCODE_SGE: *cc = 0x6; *ty = 0x80; break;
1459 case TGSI_OPCODE_SEQ: *cc = 0x2; *ty = 0x80; break;
1460 case TGSI_OPCODE_SGT: *cc = 0x4; *ty = 0x80; break;
1461 case TGSI_OPCODE_SLE: *cc = 0x3; *ty = 0x80; break;
1462 case TGSI_OPCODE_SNE: *cc = 0xd; *ty = 0x80; break;
1464 case TGSI_OPCODE_ISLT: *cc = 0x1; *ty = 0x0c; break;
1465 case TGSI_OPCODE_ISGE: *cc = 0x6; *ty = 0x0c; break;
1466 case TGSI_OPCODE_USEQ: *cc = 0x2; *ty = 0x04; break;
1467 case TGSI_OPCODE_USGE: *cc = 0x6; *ty = 0x04; break;
1468 case TGSI_OPCODE_USLT: *cc = 0x1; *ty = 0x04; break;
1469 case TGSI_OPCODE_USNE: *cc = 0x5; *ty = 0x04; break;
1477 emit_add_b32(struct nv50_pc *pc, struct nv50_reg *dst,
1478 struct nv50_reg *src0, struct nv50_reg *rsrc1)
1480 struct nv50_program_exec *e = exec(pc);
1481 struct nv50_reg *src1;
1483 e->inst[0] = 0x20000000;
1485 alloc_reg(pc, rsrc1);
1486 check_swap_src_0_1(pc, &src0, &rsrc1);
1489 if (src0->mod & rsrc1->mod & NV50_MOD_NEG) {
1490 src1 = temp_temp(pc, e);
1491 emit_cvt(pc, src1, rsrc1, -1, CVT_S32_S32);
1494 if (!pc->allow32 || src1->hw > 63 ||
1495 (src1->type != P_TEMP && src1->type != P_IMMD))
1498 set_dst(pc, dst, e);
1499 set_src_0(pc, src0, e);
1502 e->inst[1] |= 1 << 26;
1503 set_src_2(pc, src1, e);
1505 e->inst[0] |= 0x8000;
1506 if (src1->type == P_IMMD)
1507 set_immd(pc, src1, e);
1509 set_src_1(pc, src1, e);
1512 if (src0->mod & NV50_MOD_NEG)
1513 e->inst[0] |= 1 << 28;
1515 if (src1->mod & NV50_MOD_NEG)
1516 e->inst[0] |= 1 << 22;
1522 emit_mad_u16(struct nv50_pc *pc, struct nv50_reg *dst,
1523 struct nv50_reg *src0, int lh_0, struct nv50_reg *src1, int lh_1,
1524 struct nv50_reg *src2)
1526 struct nv50_program_exec *e = exec(pc);
1528 e->inst[0] = 0x60000000;
1531 set_dst(pc, dst, e);
1533 set_half_src(pc, src0, lh_0, e, 9);
1534 set_half_src(pc, src1, lh_1, e, 16);
1535 alloc_reg(pc, src2);
1536 if (is_long(e) || (src2->type != P_TEMP) || (src2->hw != dst->hw))
1537 set_src_2(pc, src2, e);
1543 emit_mul_u16(struct nv50_pc *pc, struct nv50_reg *dst,
1544 struct nv50_reg *src0, int lh_0, struct nv50_reg *src1, int lh_1)
1546 struct nv50_program_exec *e = exec(pc);
1548 e->inst[0] = 0x40000000;
1550 set_dst(pc, dst, e);
1552 set_half_src(pc, src0, lh_0, e, 9);
1553 set_half_src(pc, src1, lh_1, e, 16);
1559 emit_sad(struct nv50_pc *pc, struct nv50_reg *dst,
1560 struct nv50_reg *src0, struct nv50_reg *src1, struct nv50_reg *src2)
1562 struct nv50_program_exec *e = exec(pc);
1564 e->inst[0] = 0x50000000;
1567 check_swap_src_0_1(pc, &src0, &src1);
1568 set_dst(pc, dst, e);
1569 set_src_0(pc, src0, e);
1570 set_src_1(pc, src1, e);
1571 alloc_reg(pc, src2);
1572 if (is_long(e) || (src2->type != dst->type) || (src2->hw != dst->hw))
1573 set_src_2(pc, src2, e);
1576 e->inst[1] |= 0x0c << 24;
1578 e->inst[0] |= 0x81 << 8;
1584 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1586 emit_cvt(pc, dst, src, -1, CVT_FLOOR | CVT_F32_F32 | CVT_RI);
1590 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1591 struct nv50_reg *v, struct nv50_reg *e)
1593 struct nv50_reg *temp = alloc_temp(pc, NULL);
1595 emit_flop(pc, NV50_FLOP_LG2, temp, v);
1596 emit_mul(pc, temp, temp, e);
1597 emit_preex2(pc, temp, temp);
1598 emit_flop(pc, NV50_FLOP_EX2, dst, temp);
1600 free_temp(pc, temp);
1604 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1606 emit_cvt(pc, dst, src, -1, CVT_SAT | CVT_F32_F32);
1610 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1611 struct nv50_reg **src)
1613 struct nv50_reg *one = alloc_immd(pc, 1.0);
1614 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1615 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1616 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1617 struct nv50_reg *tmp[4];
1618 boolean allow32 = pc->allow32;
1620 pc->allow32 = FALSE;
1622 if (mask & (3 << 1)) {
1623 tmp[0] = alloc_temp(pc, NULL);
1624 emit_minmax(pc, NV50_MAX_F32, tmp[0], src[0], zero);
1627 if (mask & (1 << 2)) {
1628 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1630 tmp[1] = temp_temp(pc, NULL);
1631 emit_minmax(pc, NV50_MAX_F32, tmp[1], src[1], zero);
1633 tmp[3] = temp_temp(pc, NULL);
1634 emit_minmax(pc, NV50_MAX_F32, tmp[3], src[3], neg128);
1635 emit_minmax(pc, NV50_MIN_F32, tmp[3], tmp[3], pos128);
1637 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1638 emit_mov(pc, dst[2], zero);
1639 set_pred(pc, 3, 0, pc->p->exec_tail);
1642 if (mask & (1 << 1))
1643 assimilate_temp(pc, dst[1], tmp[0]);
1645 if (mask & (1 << 2))
1646 free_temp(pc, tmp[0]);
1648 pc->allow32 = allow32;
1650 /* do this last, in case src[i,j] == dst[0,3] */
1651 if (mask & (1 << 0))
1652 emit_mov(pc, dst[0], one);
1654 if (mask & (1 << 3))
1655 emit_mov(pc, dst[3], one);
1664 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1666 struct nv50_program_exec *e;
1667 const int r_pred = 1;
1670 e->inst[0] = 0x00000002; /* discard */
1671 set_long(pc, e); /* sets cond code to ALWAYS */
1674 set_pred(pc, 0x1 /* cc = LT */, r_pred, e);
1675 /* write to predicate reg */
1676 emit_cvt(pc, NULL, src, r_pred, CVT_F32_F32);
1682 static struct nv50_program_exec *
1683 emit_control_flow(struct nv50_pc *pc, unsigned op, int pred, unsigned cc)
1685 struct nv50_program_exec *e = exec(pc);
1687 e->inst[0] = (op << 28) | 2;
1690 set_pred(pc, cc, pred, e);
1696 static INLINE struct nv50_program_exec *
1697 emit_breakaddr(struct nv50_pc *pc)
1699 return emit_control_flow(pc, 0x4, -1, 0);
1703 emit_break(struct nv50_pc *pc, int pred, unsigned cc)
1705 emit_control_flow(pc, 0x5, pred, cc);
1708 static INLINE struct nv50_program_exec *
1709 emit_joinat(struct nv50_pc *pc)
1711 return emit_control_flow(pc, 0xa, -1, 0);
1714 static INLINE struct nv50_program_exec *
1715 emit_branch(struct nv50_pc *pc, int pred, unsigned cc)
1717 return emit_control_flow(pc, 0x1, pred, cc);
1720 static INLINE struct nv50_program_exec *
1721 emit_call(struct nv50_pc *pc, int pred, unsigned cc)
1723 return emit_control_flow(pc, 0x2, pred, cc);
1727 emit_ret(struct nv50_pc *pc, int pred, unsigned cc)
1729 emit_control_flow(pc, 0x3, pred, cc);
1733 emit_prim_cmd(struct nv50_pc *pc, unsigned cmd)
1735 struct nv50_program_exec *e = exec(pc);
1737 e->inst[0] = 0xf0000000 | (cmd << 9);
1738 e->inst[1] = 0xc0000000;
1747 #define QOP_MOV_SRC1 3
1749 /* For a quad of threads / top left, top right, bottom left, bottom right
1750 * pixels, do a different operation, and take src0 from a specific thread.
1753 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1754 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1756 struct nv50_program_exec *e = exec(pc);
1758 e->inst[0] = 0xc0000000;
1759 e->inst[1] = 0x80000000;
1761 e->inst[0] |= lane_src0 << 16;
1762 set_src_0(pc, src0, e);
1763 set_src_2(pc, src1, e);
1766 set_pred_wr(pc, 1, wp, e);
1769 set_dst(pc, dst, e);
1771 e->inst[0] |= 0x000001fc;
1772 e->inst[1] |= 0x00000008;
1775 e->inst[0] |= (qop & 3) << 20;
1776 e->inst[1] |= (qop >> 2) << 22;
1782 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1783 struct nv50_reg **src, unsigned arg, boolean proj)
1785 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1787 src[0]->mod |= NV50_MOD_ABS;
1788 src[1]->mod |= NV50_MOD_ABS;
1789 src[2]->mod |= NV50_MOD_ABS;
1791 emit_minmax(pc, NV50_MAX_F32, t[2], src[0], src[1]);
1792 emit_minmax(pc, NV50_MAX_F32, t[2], src[2], t[2]);
1794 src[0]->mod = mod[0];
1795 src[1]->mod = mod[1];
1796 src[2]->mod = mod[2];
1798 if (proj && 0 /* looks more correct without this */)
1799 emit_mul(pc, t[2], t[2], src[3]);
1801 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1802 emit_mov(pc, t[3], src[3]);
1804 emit_flop(pc, NV50_FLOP_RCP, t[2], t[2]);
1806 emit_mul(pc, t[0], src[0], t[2]);
1807 emit_mul(pc, t[1], src[1], t[2]);
1808 emit_mul(pc, t[2], src[2], t[2]);
1812 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1813 struct nv50_reg **src, unsigned dim, unsigned arg)
1817 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1818 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1820 t[3]->rhw = src[3]->rhw;
1821 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1822 emit_flop(pc, NV50_FLOP_RCP, t[3], t[3]);
1824 for (c = 0; c < dim; ++c) {
1825 t[c]->rhw = src[c]->rhw;
1826 emit_interp(pc, t[c], t[3], mode);
1828 if (arg != dim) { /* depth reference value */
1829 t[dim]->rhw = src[2]->rhw;
1830 emit_interp(pc, t[dim], t[3], mode);
1833 /* XXX: for some reason the blob sometimes uses MAD
1834 * (mad f32 $rX $rY $rZ neg $r63)
1836 emit_flop(pc, NV50_FLOP_RCP, t[3], src[3]);
1837 for (c = 0; c < dim; ++c)
1838 emit_mul(pc, t[c], src[c], t[3]);
1839 if (arg != dim) /* depth reference value */
1840 emit_mul(pc, t[dim], src[2], t[3]);
1845 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1848 case TGSI_TEXTURE_1D:
1851 case TGSI_TEXTURE_SHADOW1D:
1855 case TGSI_TEXTURE_UNKNOWN:
1856 case TGSI_TEXTURE_2D:
1857 case TGSI_TEXTURE_RECT:
1860 case TGSI_TEXTURE_SHADOW2D:
1861 case TGSI_TEXTURE_SHADOWRECT:
1865 case TGSI_TEXTURE_3D:
1866 case TGSI_TEXTURE_CUBE:
1875 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1876 * different LOD values, so branch off groups of equal LOD.
1879 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1880 struct nv50_reg *src, struct nv50_program_exec *tex)
1882 struct nv50_program_exec *join_at;
1883 unsigned i, target = pc->p->exec_size + 9 * 2;
1885 if (pc->p->type != PIPE_SHADER_FRAGMENT) {
1889 pc->allow32 = FALSE;
1891 /* Subtract lod of each pixel from lod of top left pixel, jump
1892 * texlod insn if result is 0, then repeat for 2 other pixels.
1894 join_at = emit_joinat(pc);
1895 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1896 emit_branch(pc, 0, 2)->param.index = target;
1898 for (i = 1; i < 4; ++i) {
1899 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1900 emit_branch(pc, 0, 2)->param.index = target;
1903 emit_mov(pc, tlod, src); /* target */
1904 emit(pc, tex); /* texlod */
1906 join_at->param.index = target + 2 * 2;
1907 JOIN_ON(emit_nop(pc)); /* join _after_ tex */
1911 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1912 struct nv50_program_exec *tex)
1914 struct nv50_program_exec *e;
1915 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1917 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1919 pc->allow32 = FALSE;
1920 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1922 /* Subtract bias value of thread i from bias values of each thread,
1923 * store result in r_pred, and set bit i in r_bits if result was 0.
1926 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1927 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1928 emit_mov(pc, r_bits, &imm_1248);
1929 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1931 emit_mov_to_pred(pc, r_pred, r_bits);
1933 /* The lanes of a quad are now grouped by the bit in r_pred they have
1934 * set. Put the input values for TEX into a new register set for each
1935 * group and execute TEX only for a specific group.
1936 * We cannot use the same register set for each group because we need
1937 * the derivatives, which are implicitly calculated, to be correct.
1939 for (i = 1; i < 4; ++i) {
1940 alloc_temp4(pc, t123[i], 0);
1942 for (c = 0; c <= arg; ++c)
1943 emit_mov(pc, t123[i][c], t[c]);
1945 *(e = exec(pc)) = *(tex);
1946 e->inst[0] &= ~0x01fc;
1947 set_dst(pc, t123[i][0], e);
1948 set_pred(pc, cc[i], r_pred, e);
1951 /* finally TEX on the original regs (where we kept the input) */
1952 set_pred(pc, cc[0], r_pred, tex);
1955 /* put the 3 * n other results into regs for lane 0 */
1956 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1957 for (i = 1; i < 4; ++i) {
1958 for (c = 0; c < n; ++c) {
1959 emit_mov(pc, t[c], t123[i][c]);
1960 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1962 free_temp4(pc, t123[i]);
1966 free_temp(pc, r_bits);
1970 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1971 struct nv50_reg **src, unsigned unit, unsigned type,
1972 boolean proj, int bias_lod)
1974 struct nv50_reg *t[4];
1975 struct nv50_program_exec *e;
1976 unsigned c, dim, arg;
1978 /* t[i] must be within a single 128 bit super-reg */
1979 alloc_temp4(pc, t, 0);
1982 e->inst[0] = 0xf0000000;
1984 set_dst(pc, t[0], e);
1986 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1987 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1989 /* live flag (don't set if TEX results affect input to another TEX): */
1990 /* e->inst[0] |= 0x00000004; */
1992 get_tex_dim(type, &dim, &arg);
1994 if (type == TGSI_TEXTURE_CUBE) {
1995 e->inst[0] |= 0x08000000;
1996 load_cube_tex_coords(pc, t, src, arg, proj);
1999 load_proj_tex_coords(pc, t, src, dim, arg);
2001 for (c = 0; c < dim; c++)
2002 emit_mov(pc, t[c], src[c]);
2003 if (arg != dim) /* depth reference value (always src.z here) */
2004 emit_mov(pc, t[dim], src[2]);
2007 e->inst[0] |= (mask & 0x3) << 25;
2008 e->inst[1] |= (mask & 0xc) << 12;
2011 e->inst[0] |= (arg - 1) << 22;
2015 assert(pc->p->type == PIPE_SHADER_FRAGMENT);
2016 e->inst[0] |= arg << 22;
2017 e->inst[1] |= 0x20000000; /* texbias */
2018 emit_mov(pc, t[arg], src[3]);
2019 emit_texbias_sequence(pc, t, arg, e);
2021 e->inst[0] |= arg << 22;
2022 e->inst[1] |= 0x40000000; /* texlod */
2023 emit_mov(pc, t[arg], src[3]);
2024 emit_texlod_sequence(pc, t[arg], src[3], e);
2029 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
2030 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
2031 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
2032 if (mask & 8) emit_mov(pc, dst[3], t[c]);
2036 /* XXX: if p.e. MUL is used directly after TEX, it would still use
2037 * the texture coordinates, not the fetched values: latency ? */
2039 for (c = 0; c < 4; c++) {
2040 if (mask & (1 << c))
2041 assimilate_temp(pc, dst[c], t[c]);
2043 free_temp(pc, t[c]);
2049 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
2051 struct nv50_program_exec *e = exec(pc);
2053 assert(src->type == P_TEMP);
2055 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0240000 : 0xc0140000;
2056 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x86400000 : 0x89800000;
2058 set_dst(pc, dst, e);
2059 set_src_0(pc, src, e);
2060 set_src_2(pc, src, e);
2066 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
2068 struct nv50_program_exec *e = exec(pc);
2070 assert(src->type == P_TEMP);
2072 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0250000 : 0xc0150000;
2073 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x85800000 : 0x8a400000;
2075 set_dst(pc, dst, e);
2076 set_src_0(pc, src, e);
2077 set_src_2(pc, src, e);
2083 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
2085 unsigned q = 0, m = ~0;
2087 assert(!is_long(e));
2089 switch (e->inst[0] >> 28) {
2097 /* ADD, SUB, SUBR b32 */
2098 m = ~(0x8000 | (127 << 16));
2099 q = ((e->inst[0] & (~m)) >> 2) | (1 << 26);
2104 q = (0x0c << 24) | ((e->inst[0] & (0x7f << 2)) << 12);
2108 q = (e->inst[0] & (0x7f << 2)) << 12;
2111 /* INTERP (move centroid, perspective and flat bits) */
2113 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
2114 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
2122 q = ((e->inst[0] & (~m)) >> 2);
2127 q = ((e->inst[0] & (~m)) << 12);
2130 /* MAD (if src2 == dst) */
2131 q = ((e->inst[0] & 0x1fc) << 12);
2145 /* Some operations support an optional negation flag. */
2147 get_supported_mods(const struct tgsi_full_instruction *insn, int i)
2149 switch (insn->Instruction.Opcode) {
2150 case TGSI_OPCODE_ADD:
2151 case TGSI_OPCODE_COS:
2152 case TGSI_OPCODE_DDX:
2153 case TGSI_OPCODE_DDY:
2154 case TGSI_OPCODE_DP3:
2155 case TGSI_OPCODE_DP4:
2156 case TGSI_OPCODE_EX2:
2157 case TGSI_OPCODE_KIL:
2158 case TGSI_OPCODE_LG2:
2159 case TGSI_OPCODE_MAD:
2160 case TGSI_OPCODE_MUL:
2161 case TGSI_OPCODE_POW:
2162 case TGSI_OPCODE_RCP:
2163 case TGSI_OPCODE_RSQ: /* ignored, RSQ = rsqrt(abs(src.x)) */
2164 case TGSI_OPCODE_SCS:
2165 case TGSI_OPCODE_SIN:
2166 case TGSI_OPCODE_SUB:
2167 return NV50_MOD_NEG;
2168 case TGSI_OPCODE_MAX:
2169 case TGSI_OPCODE_MIN:
2170 case TGSI_OPCODE_INEG: /* tgsi src sign toggle/set would be stupid */
2171 return NV50_MOD_ABS;
2172 case TGSI_OPCODE_CEIL:
2173 case TGSI_OPCODE_FLR:
2174 case TGSI_OPCODE_TRUNC:
2175 return NV50_MOD_NEG | NV50_MOD_ABS;
2176 case TGSI_OPCODE_F2I:
2177 case TGSI_OPCODE_F2U:
2178 case TGSI_OPCODE_I2F:
2179 case TGSI_OPCODE_U2F:
2180 return NV50_MOD_NEG | NV50_MOD_ABS | NV50_MOD_I32;
2181 case TGSI_OPCODE_UADD:
2182 return NV50_MOD_NEG | NV50_MOD_I32;
2183 case TGSI_OPCODE_SAD:
2184 case TGSI_OPCODE_SHL:
2185 case TGSI_OPCODE_IMAX:
2186 case TGSI_OPCODE_IMIN:
2187 case TGSI_OPCODE_ISHR:
2188 case TGSI_OPCODE_NOT:
2189 case TGSI_OPCODE_UMAD:
2190 case TGSI_OPCODE_UMAX:
2191 case TGSI_OPCODE_UMIN:
2192 case TGSI_OPCODE_UMUL:
2193 case TGSI_OPCODE_USHR:
2194 return NV50_MOD_I32;
2200 /* Return a read mask for source registers deduced from opcode & write mask. */
2202 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
2204 unsigned x, mask = insn->Dst[0].Register.WriteMask;
2206 switch (insn->Instruction.Opcode) {
2207 case TGSI_OPCODE_COS:
2208 case TGSI_OPCODE_SIN:
2209 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
2210 case TGSI_OPCODE_DP3:
2212 case TGSI_OPCODE_DP4:
2213 case TGSI_OPCODE_DPH:
2214 case TGSI_OPCODE_KIL: /* WriteMask ignored */
2216 case TGSI_OPCODE_DST:
2217 return mask & (c ? 0xa : 0x6);
2218 case TGSI_OPCODE_EX2:
2219 case TGSI_OPCODE_EXP:
2220 case TGSI_OPCODE_LG2:
2221 case TGSI_OPCODE_LOG:
2222 case TGSI_OPCODE_POW:
2223 case TGSI_OPCODE_RCP:
2224 case TGSI_OPCODE_RSQ:
2225 case TGSI_OPCODE_SCS:
2227 case TGSI_OPCODE_IF:
2229 case TGSI_OPCODE_LIT:
2231 case TGSI_OPCODE_TEX:
2232 case TGSI_OPCODE_TXB:
2233 case TGSI_OPCODE_TXL:
2234 case TGSI_OPCODE_TXP:
2236 const struct tgsi_instruction_texture *tex;
2238 assert(insn->Instruction.Texture);
2239 tex = &insn->Texture;
2242 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
2243 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
2244 mask |= 0x8; /* bias, lod or proj */
2246 switch (tex->Texture) {
2247 case TGSI_TEXTURE_1D:
2250 case TGSI_TEXTURE_SHADOW1D:
2253 case TGSI_TEXTURE_2D:
2261 case TGSI_OPCODE_XPD:
2263 if (mask & 1) x |= 0x6;
2264 if (mask & 2) x |= 0x5;
2265 if (mask & 4) x |= 0x3;
2274 static struct nv50_reg *
2275 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
2277 switch (dst->Register.File) {
2278 case TGSI_FILE_TEMPORARY:
2279 return &pc->temp[dst->Register.Index * 4 + c];
2280 case TGSI_FILE_OUTPUT:
2281 return &pc->result[dst->Register.Index * 4 + c];
2282 case TGSI_FILE_ADDRESS:
2284 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
2286 r = get_address_reg(pc, NULL);
2287 r->index = dst->Register.Index * 4 + c;
2288 pc->addr[r->index] = r;
2293 case TGSI_FILE_NULL:
2295 case TGSI_FILE_SYSTEM_VALUE:
2296 assert(pc->sysval[dst->Register.Index].type == P_RESULT);
2298 return &pc->sysval[dst->Register.Index];
2306 static struct nv50_reg *
2307 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
2310 struct nv50_reg *r = NULL;
2311 struct nv50_reg *temp = NULL;
2312 unsigned sgn, c, swz, cvn;
2314 if (src->Register.File != TGSI_FILE_CONSTANT)
2315 assert(!src->Register.Indirect);
2317 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
2319 c = tgsi_util_get_full_src_register_swizzle(src, chan);
2321 case TGSI_SWIZZLE_X:
2322 case TGSI_SWIZZLE_Y:
2323 case TGSI_SWIZZLE_Z:
2324 case TGSI_SWIZZLE_W:
2325 switch (src->Register.File) {
2326 case TGSI_FILE_INPUT:
2327 r = &pc->attr[src->Register.Index * 4 + c];
2329 if (!src->Dimension.Dimension)
2331 r = reg_instance(pc, r);
2332 r->vtx = src->Dimension.Index;
2334 if (!src->Dimension.Indirect)
2336 swz = tgsi_util_get_src_register_swizzle(
2337 &src->DimIndirect, 0);
2339 r->indirect[1] = src->DimIndirect.Index * 4 + swz;
2341 case TGSI_FILE_TEMPORARY:
2342 r = &pc->temp[src->Register.Index * 4 + c];
2344 case TGSI_FILE_CONSTANT:
2345 if (!src->Register.Indirect) {
2346 r = &pc->param[src->Register.Index * 4 + c];
2349 /* Indicate indirection by setting r->acc < 0 and
2350 * use the index field to select the address reg.
2352 r = reg_instance(pc, NULL);
2353 ctor_reg(r, P_CONST, -1, src->Register.Index * 4 + c);
2355 swz = tgsi_util_get_src_register_swizzle(
2358 r->indirect[0] = src->Indirect.Index * 4 + swz;
2360 case TGSI_FILE_IMMEDIATE:
2361 r = &pc->immd[src->Register.Index * 4 + c];
2363 case TGSI_FILE_SAMPLER:
2365 case TGSI_FILE_ADDRESS:
2366 r = pc->addr[src->Register.Index * 4 + c];
2369 case TGSI_FILE_SYSTEM_VALUE:
2371 r = &pc->sysval[src->Register.Index];
2383 cvn = (mod & NV50_MOD_I32) ? CVT_S32_S32 : CVT_F32_F32;
2386 case TGSI_UTIL_SIGN_CLEAR:
2387 r->mod = NV50_MOD_ABS;
2389 case TGSI_UTIL_SIGN_SET:
2390 r->mod = NV50_MOD_NEG_ABS;
2392 case TGSI_UTIL_SIGN_TOGGLE:
2393 r->mod = NV50_MOD_NEG;
2396 assert(!r->mod && sgn == TGSI_UTIL_SIGN_KEEP);
2400 if ((r->mod & mod) != r->mod) {
2401 temp = temp_temp(pc, NULL);
2402 emit_cvt(pc, temp, r, -1, cvn);
2406 r->mod |= mod & NV50_MOD_I32;
2409 if (r->acc >= 0 && r->vtx < 0 && r != temp)
2410 return reg_instance(pc, r); /* will clear r->mod */
2414 /* return TRUE for ops that produce only a single result */
2416 is_scalar_op(unsigned op)
2419 case TGSI_OPCODE_COS:
2420 case TGSI_OPCODE_DP2:
2421 case TGSI_OPCODE_DP3:
2422 case TGSI_OPCODE_DP4:
2423 case TGSI_OPCODE_DPH:
2424 case TGSI_OPCODE_EX2:
2425 case TGSI_OPCODE_LG2:
2426 case TGSI_OPCODE_POW:
2427 case TGSI_OPCODE_RCP:
2428 case TGSI_OPCODE_RSQ:
2429 case TGSI_OPCODE_SIN:
2431 case TGSI_OPCODE_KIL:
2432 case TGSI_OPCODE_LIT:
2433 case TGSI_OPCODE_SCS:
2441 /* Returns a bitmask indicating which dst components depend
2442 * on source s, component c (reverse of nv50_tgsi_src_mask).
2445 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
2447 if (is_scalar_op(op))
2451 case TGSI_OPCODE_DST:
2452 return (1 << c) & (s ? 0xa : 0x6);
2453 case TGSI_OPCODE_XPD:
2463 case TGSI_OPCODE_EXP:
2464 case TGSI_OPCODE_LOG:
2465 case TGSI_OPCODE_LIT:
2466 case TGSI_OPCODE_SCS:
2467 case TGSI_OPCODE_TEX:
2468 case TGSI_OPCODE_TXB:
2469 case TGSI_OPCODE_TXL:
2470 case TGSI_OPCODE_TXP:
2471 /* these take care of dangerous swizzles themselves */
2473 case TGSI_OPCODE_IF:
2474 case TGSI_OPCODE_KIL:
2475 /* don't call this function for these ops */
2479 /* linear vector instruction */
2484 static INLINE boolean
2485 has_pred(struct nv50_program_exec *e, unsigned cc)
2487 if (!is_long(e) || is_immd(e))
2489 return ((e->inst[1] & 0x780) == (cc << 7));
2492 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2499 nv50_kill_branch(struct nv50_pc *pc)
2501 int lvl = pc->if_lvl;
2503 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2505 if (is_immd(pc->p->exec_tail))
2508 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2509 * reg may no longer be valid, since we currently always use $p0
2511 if (has_pred(pc->if_insn[lvl], 0xf))
2513 assert(pc->if_insn[lvl] && pc->if_join[lvl]);
2515 /* We'll use the exec allocated for JOIN_AT (we can't easily
2516 * access nv50_program_exec's prev).
2518 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2520 *pc->if_join[lvl] = *pc->p->exec_tail;
2522 FREE(pc->if_insn[lvl]);
2523 FREE(pc->p->exec_tail);
2525 pc->p->exec_tail = pc->if_join[lvl];
2526 pc->p->exec_tail->next = NULL;
2527 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2533 nv50_fp_move_results(struct nv50_pc *pc)
2535 struct nv50_reg reg;
2538 ctor_reg(®, P_TEMP, -1, -1);
2540 for (i = 0; i < pc->result_nr * 4; ++i) {
2541 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2543 if (pc->result[i].rhw != pc->result[i].hw) {
2544 reg.hw = pc->result[i].rhw;
2545 emit_mov(pc, ®, &pc->result[i]);
2551 nv50_program_tx_insn(struct nv50_pc *pc,
2552 const struct tgsi_full_instruction *inst)
2554 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2555 unsigned mask, sat, unit;
2558 mask = inst->Dst[0].Register.WriteMask;
2559 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2561 memset(src, 0, sizeof(src));
2563 for (c = 0; c < 4; c++) {
2564 if ((mask & (1 << c)) && !pc->r_dst[c])
2565 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2567 dst[c] = pc->r_dst[c];
2571 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2572 const struct tgsi_full_src_register *fs = &inst->Src[i];
2576 src_mask = nv50_tgsi_src_mask(inst, i);
2577 mod_supp = get_supported_mods(inst, i);
2579 if (fs->Register.File == TGSI_FILE_SAMPLER)
2580 unit = fs->Register.Index;
2582 for (c = 0; c < 4; c++)
2583 if (src_mask & (1 << c))
2584 src[i][c] = tgsi_src(pc, c, fs, mod_supp);
2587 brdc = temp = pc->r_brdc;
2588 if (brdc && brdc->type != P_TEMP) {
2589 temp = temp_temp(pc, NULL);
2594 for (c = 0; c < 4; c++) {
2595 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2597 /* rdst[c] = dst[c]; */ /* done above */
2598 dst[c] = temp_temp(pc, NULL);
2602 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2604 switch (inst->Instruction.Opcode) {
2605 case TGSI_OPCODE_ABS:
2606 for (c = 0; c < 4; c++) {
2607 if (!(mask & (1 << c)))
2609 emit_cvt(pc, dst[c], src[0][c], -1,
2610 CVT_ABS | CVT_F32_F32);
2613 case TGSI_OPCODE_ADD:
2614 for (c = 0; c < 4; c++) {
2615 if (!(mask & (1 << c)))
2617 emit_add(pc, dst[c], src[0][c], src[1][c]);
2620 case TGSI_OPCODE_AND:
2621 case TGSI_OPCODE_XOR:
2622 case TGSI_OPCODE_OR:
2623 for (c = 0; c < 4; c++) {
2624 if (!(mask & (1 << c)))
2626 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2627 inst->Instruction.Opcode);
2630 case TGSI_OPCODE_ARL:
2631 temp = temp_temp(pc, NULL);
2632 for (c = 0; c < 4; c++) {
2633 if (!(mask & (1 << c)))
2635 emit_cvt(pc, temp, src[0][c], -1,
2636 CVT_FLOOR | CVT_S32_F32);
2637 emit_arl(pc, dst[c], temp, 4);
2640 case TGSI_OPCODE_BGNLOOP:
2641 pc->loop_brka[pc->loop_lvl] = emit_breakaddr(pc);
2642 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2645 case TGSI_OPCODE_BGNSUB:
2646 assert(!pc->in_subroutine);
2647 pc->in_subroutine = TRUE;
2648 /* probably not necessary, but align to 8 byte boundary */
2649 if (!is_long(pc->p->exec_tail))
2650 convert_to_long(pc, pc->p->exec_tail);
2652 case TGSI_OPCODE_BRK:
2653 assert(pc->loop_lvl > 0);
2654 emit_break(pc, -1, 0);
2656 case TGSI_OPCODE_CAL:
2657 assert(inst->Label.Label < pc->insn_nr);
2658 emit_call(pc, -1, 0)->param.index = inst->Label.Label;
2659 /* replaced by actual offset in nv50_program_fixup_insns */
2661 case TGSI_OPCODE_CEIL:
2662 for (c = 0; c < 4; c++) {
2663 if (!(mask & (1 << c)))
2665 emit_cvt(pc, dst[c], src[0][c], -1,
2666 CVT_CEIL | CVT_F32_F32 | CVT_RI);
2669 case TGSI_OPCODE_CMP:
2670 pc->allow32 = FALSE;
2671 for (c = 0; c < 4; c++) {
2672 if (!(mask & (1 << c)))
2674 emit_cvt(pc, NULL, src[0][c], 1, CVT_F32_F32);
2675 emit_mov(pc, dst[c], src[1][c]);
2676 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2677 emit_mov(pc, dst[c], src[2][c]);
2678 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2681 case TGSI_OPCODE_CONT:
2682 assert(pc->loop_lvl > 0);
2683 emit_branch(pc, -1, 0)->param.index =
2684 pc->loop_pos[pc->loop_lvl - 1];
2686 case TGSI_OPCODE_COS:
2688 emit_precossin(pc, temp, src[0][3]);
2689 emit_flop(pc, NV50_FLOP_COS, dst[3], temp);
2693 temp = brdc = temp_temp(pc, NULL);
2695 emit_precossin(pc, temp, src[0][0]);
2696 emit_flop(pc, NV50_FLOP_COS, brdc, temp);
2698 case TGSI_OPCODE_DDX:
2699 for (c = 0; c < 4; c++) {
2700 if (!(mask & (1 << c)))
2702 emit_ddx(pc, dst[c], src[0][c]);
2705 case TGSI_OPCODE_DDY:
2706 for (c = 0; c < 4; c++) {
2707 if (!(mask & (1 << c)))
2709 emit_ddy(pc, dst[c], src[0][c]);
2712 case TGSI_OPCODE_DP3:
2713 emit_mul(pc, temp, src[0][0], src[1][0]);
2714 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2715 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2717 case TGSI_OPCODE_DP4:
2718 emit_mul(pc, temp, src[0][0], src[1][0]);
2719 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2720 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2721 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2723 case TGSI_OPCODE_DPH:
2724 emit_mul(pc, temp, src[0][0], src[1][0]);
2725 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2726 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2727 emit_add(pc, brdc, src[1][3], temp);
2729 case TGSI_OPCODE_DST:
2730 if (mask & (1 << 1))
2731 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2732 if (mask & (1 << 2))
2733 emit_mov(pc, dst[2], src[0][2]);
2734 if (mask & (1 << 3))
2735 emit_mov(pc, dst[3], src[1][3]);
2736 if (mask & (1 << 0))
2737 emit_mov_immdval(pc, dst[0], 1.0f);
2739 case TGSI_OPCODE_ELSE:
2740 emit_branch(pc, -1, 0);
2741 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2742 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2745 case TGSI_OPCODE_EMIT:
2746 emit_prim_cmd(pc, 1);
2748 case TGSI_OPCODE_ENDIF:
2749 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2751 /* try to replace branch over 1 insn with a predicated insn */
2752 if (nv50_kill_branch(pc) == TRUE)
2755 if (pc->if_join[pc->if_lvl]) {
2756 pc->if_join[pc->if_lvl]->param.index = pc->p->exec_size;
2757 pc->if_join[pc->if_lvl] = NULL;
2760 /* emit a NOP as join point, we could set it on the next
2761 * one, but would have to make sure it is long and !immd
2763 JOIN_ON(emit_nop(pc));
2765 case TGSI_OPCODE_ENDLOOP:
2766 emit_branch(pc, -1, 0)->param.index =
2767 pc->loop_pos[--pc->loop_lvl];
2768 pc->loop_brka[pc->loop_lvl]->param.index = pc->p->exec_size;
2771 case TGSI_OPCODE_ENDPRIM:
2772 emit_prim_cmd(pc, 2);
2774 case TGSI_OPCODE_ENDSUB:
2775 assert(pc->in_subroutine);
2777 pc->in_subroutine = FALSE;
2779 case TGSI_OPCODE_EX2:
2780 emit_preex2(pc, temp, src[0][0]);
2781 emit_flop(pc, NV50_FLOP_EX2, brdc, temp);
2783 case TGSI_OPCODE_EXP:
2785 struct nv50_reg *t[2];
2788 t[0] = temp_temp(pc, NULL);
2789 t[1] = temp_temp(pc, NULL);
2792 emit_mov(pc, t[0], src[0][0]);
2794 emit_flr(pc, t[1], src[0][0]);
2796 if (mask & (1 << 1))
2797 emit_sub(pc, dst[1], t[0], t[1]);
2798 if (mask & (1 << 0)) {
2799 emit_preex2(pc, t[1], t[1]);
2800 emit_flop(pc, NV50_FLOP_EX2, dst[0], t[1]);
2802 if (mask & (1 << 2)) {
2803 emit_preex2(pc, t[0], t[0]);
2804 emit_flop(pc, NV50_FLOP_EX2, dst[2], t[0]);
2806 if (mask & (1 << 3))
2807 emit_mov_immdval(pc, dst[3], 1.0f);
2810 case TGSI_OPCODE_F2I:
2811 for (c = 0; c < 4; c++) {
2812 if (!(mask & (1 << c)))
2814 emit_cvt(pc, dst[c], src[0][c], -1,
2815 CVT_TRUNC | CVT_S32_F32);
2818 case TGSI_OPCODE_F2U:
2819 for (c = 0; c < 4; c++) {
2820 if (!(mask & (1 << c)))
2822 emit_cvt(pc, dst[c], src[0][c], -1,
2823 CVT_TRUNC | CVT_U32_F32);
2826 case TGSI_OPCODE_FLR:
2827 for (c = 0; c < 4; c++) {
2828 if (!(mask & (1 << c)))
2830 emit_flr(pc, dst[c], src[0][c]);
2833 case TGSI_OPCODE_FRC:
2834 temp = temp_temp(pc, NULL);
2835 for (c = 0; c < 4; c++) {
2836 if (!(mask & (1 << c)))
2838 emit_flr(pc, temp, src[0][c]);
2839 emit_sub(pc, dst[c], src[0][c], temp);
2842 case TGSI_OPCODE_I2F:
2843 for (c = 0; c < 4; c++) {
2844 if (!(mask & (1 << c)))
2846 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_S32);
2849 case TGSI_OPCODE_IF:
2850 assert(pc->if_lvl < NV50_MAX_COND_NESTING);
2851 emit_cvt(pc, NULL, src[0][0], 0, CVT_ABS | CVT_F32_F32);
2852 pc->if_join[pc->if_lvl] = emit_joinat(pc);
2853 pc->if_insn[pc->if_lvl++] = emit_branch(pc, 0, 2);;
2856 case TGSI_OPCODE_IMAX:
2857 for (c = 0; c < 4; c++) {
2858 if (!(mask & (1 << c)))
2860 emit_minmax(pc, 0x08c, dst[c], src[0][c], src[1][c]);
2863 case TGSI_OPCODE_IMIN:
2864 for (c = 0; c < 4; c++) {
2865 if (!(mask & (1 << c)))
2867 emit_minmax(pc, 0x0ac, dst[c], src[0][c], src[1][c]);
2870 case TGSI_OPCODE_INEG:
2871 for (c = 0; c < 4; c++) {
2872 if (!(mask & (1 << c)))
2874 emit_cvt(pc, dst[c], src[0][c], -1,
2875 CVT_S32_S32 | CVT_NEG);
2878 case TGSI_OPCODE_KIL:
2879 assert(src[0][0] && src[0][1] && src[0][2] && src[0][3]);
2880 emit_kil(pc, src[0][0]);
2881 emit_kil(pc, src[0][1]);
2882 emit_kil(pc, src[0][2]);
2883 emit_kil(pc, src[0][3]);
2885 case TGSI_OPCODE_KILP:
2888 case TGSI_OPCODE_LIT:
2889 emit_lit(pc, &dst[0], mask, &src[0][0]);
2891 case TGSI_OPCODE_LG2:
2892 emit_flop(pc, NV50_FLOP_LG2, brdc, src[0][0]);
2894 case TGSI_OPCODE_LOG:
2896 struct nv50_reg *t[2];
2898 t[0] = temp_temp(pc, NULL);
2899 if (mask & (1 << 1))
2900 t[1] = temp_temp(pc, NULL);
2904 emit_cvt(pc, t[0], src[0][0], -1, CVT_ABS | CVT_F32_F32);
2905 emit_flop(pc, NV50_FLOP_LG2, t[1], t[0]);
2906 if (mask & (1 << 2))
2907 emit_mov(pc, dst[2], t[1]);
2908 emit_flr(pc, t[1], t[1]);
2909 if (mask & (1 << 0))
2910 emit_mov(pc, dst[0], t[1]);
2911 if (mask & (1 << 1)) {
2912 t[1]->mod = NV50_MOD_NEG;
2913 emit_preex2(pc, t[1], t[1]);
2915 emit_flop(pc, NV50_FLOP_EX2, t[1], t[1]);
2916 emit_mul(pc, dst[1], t[0], t[1]);
2918 if (mask & (1 << 3))
2919 emit_mov_immdval(pc, dst[3], 1.0f);
2922 case TGSI_OPCODE_LRP:
2923 temp = temp_temp(pc, NULL);
2924 for (c = 0; c < 4; c++) {
2925 if (!(mask & (1 << c)))
2927 emit_sub(pc, temp, src[1][c], src[2][c]);
2928 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2931 case TGSI_OPCODE_MAD:
2932 for (c = 0; c < 4; c++) {
2933 if (!(mask & (1 << c)))
2935 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2938 case TGSI_OPCODE_MAX:
2939 for (c = 0; c < 4; c++) {
2940 if (!(mask & (1 << c)))
2942 emit_minmax(pc, 0x880, dst[c], src[0][c], src[1][c]);
2945 case TGSI_OPCODE_MIN:
2946 for (c = 0; c < 4; c++) {
2947 if (!(mask & (1 << c)))
2949 emit_minmax(pc, 0x8a0, dst[c], src[0][c], src[1][c]);
2952 case TGSI_OPCODE_MOV:
2953 for (c = 0; c < 4; c++) {
2954 if (!(mask & (1 << c)))
2956 emit_mov(pc, dst[c], src[0][c]);
2959 case TGSI_OPCODE_MUL:
2960 for (c = 0; c < 4; c++) {
2961 if (!(mask & (1 << c)))
2963 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2966 case TGSI_OPCODE_NOT:
2967 for (c = 0; c < 4; c++) {
2968 if (!(mask & (1 << c)))
2970 emit_not(pc, dst[c], src[0][c]);
2973 case TGSI_OPCODE_POW:
2974 emit_pow(pc, brdc, src[0][0], src[1][0]);
2976 case TGSI_OPCODE_RCP:
2977 if (!sat && popcnt4(mask) == 1)
2978 brdc = dst[ffs(mask) - 1];
2979 emit_flop(pc, NV50_FLOP_RCP, brdc, src[0][0]);
2981 case TGSI_OPCODE_RET:
2982 if (pc->p->type == PIPE_SHADER_FRAGMENT && !pc->in_subroutine)
2983 nv50_fp_move_results(pc);
2984 emit_ret(pc, -1, 0);
2986 case TGSI_OPCODE_RSQ:
2987 if (!sat && popcnt4(mask) == 1)
2988 brdc = dst[ffs(mask) - 1];
2989 src[0][0]->mod |= NV50_MOD_ABS;
2990 emit_flop(pc, NV50_FLOP_RSQ, brdc, src[0][0]);
2992 case TGSI_OPCODE_SAD:
2993 for (c = 0; c < 4; c++) {
2994 if (!(mask & (1 << c)))
2996 emit_sad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2999 case TGSI_OPCODE_SCS:
3000 temp = temp_temp(pc, NULL);
3002 emit_precossin(pc, temp, src[0][0]);
3003 if (mask & (1 << 0))
3004 emit_flop(pc, NV50_FLOP_COS, dst[0], temp);
3005 if (mask & (1 << 1))
3006 emit_flop(pc, NV50_FLOP_SIN, dst[1], temp);
3007 if (mask & (1 << 2))
3008 emit_mov_immdval(pc, dst[2], 0.0);
3009 if (mask & (1 << 3))
3010 emit_mov_immdval(pc, dst[3], 1.0);
3012 case TGSI_OPCODE_SHL:
3013 case TGSI_OPCODE_ISHR:
3014 case TGSI_OPCODE_USHR:
3015 for (c = 0; c < 4; c++) {
3016 if (!(mask & (1 << c)))
3018 emit_shift(pc, dst[c], src[0][c], src[1][c],
3019 inst->Instruction.Opcode);
3022 case TGSI_OPCODE_SIN:
3024 emit_precossin(pc, temp, src[0][3]);
3025 emit_flop(pc, NV50_FLOP_SIN, dst[3], temp);
3029 temp = brdc = temp_temp(pc, NULL);
3031 emit_precossin(pc, temp, src[0][0]);
3032 emit_flop(pc, NV50_FLOP_SIN, brdc, temp);
3034 case TGSI_OPCODE_SLT:
3035 case TGSI_OPCODE_SGE:
3036 case TGSI_OPCODE_SEQ:
3037 case TGSI_OPCODE_SGT:
3038 case TGSI_OPCODE_SLE:
3039 case TGSI_OPCODE_SNE:
3040 case TGSI_OPCODE_ISLT:
3041 case TGSI_OPCODE_ISGE:
3042 case TGSI_OPCODE_USEQ:
3043 case TGSI_OPCODE_USGE:
3044 case TGSI_OPCODE_USLT:
3045 case TGSI_OPCODE_USNE:
3049 map_tgsi_setop_hw(inst->Instruction.Opcode, &cc, &ty);
3051 for (c = 0; c < 4; c++) {
3052 if (!(mask & (1 << c)))
3054 emit_set(pc, cc, dst[c], -1, src[0][c], src[1][c], ty);
3058 case TGSI_OPCODE_SUB:
3059 for (c = 0; c < 4; c++) {
3060 if (!(mask & (1 << c)))
3062 emit_sub(pc, dst[c], src[0][c], src[1][c]);
3065 case TGSI_OPCODE_TEX:
3066 emit_tex(pc, dst, mask, src[0], unit,
3067 inst->Texture.Texture, FALSE, 0);
3069 case TGSI_OPCODE_TXB:
3070 emit_tex(pc, dst, mask, src[0], unit,
3071 inst->Texture.Texture, FALSE, -1);
3073 case TGSI_OPCODE_TXL:
3074 emit_tex(pc, dst, mask, src[0], unit,
3075 inst->Texture.Texture, FALSE, 1);
3077 case TGSI_OPCODE_TXP:
3078 emit_tex(pc, dst, mask, src[0], unit,
3079 inst->Texture.Texture, TRUE, 0);
3081 case TGSI_OPCODE_TRUNC:
3082 for (c = 0; c < 4; c++) {
3083 if (!(mask & (1 << c)))
3085 emit_cvt(pc, dst[c], src[0][c], -1,
3086 CVT_TRUNC | CVT_F32_F32 | CVT_RI);
3089 case TGSI_OPCODE_U2F:
3090 for (c = 0; c < 4; c++) {
3091 if (!(mask & (1 << c)))
3093 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_U32);
3096 case TGSI_OPCODE_UADD:
3097 for (c = 0; c < 4; c++) {
3098 if (!(mask & (1 << c)))
3100 emit_add_b32(pc, dst[c], src[0][c], src[1][c]);
3103 case TGSI_OPCODE_UMAX:
3104 for (c = 0; c < 4; c++) {
3105 if (!(mask & (1 << c)))
3107 emit_minmax(pc, 0x084, dst[c], src[0][c], src[1][c]);
3110 case TGSI_OPCODE_UMIN:
3111 for (c = 0; c < 4; c++) {
3112 if (!(mask & (1 << c)))
3114 emit_minmax(pc, 0x0a4, dst[c], src[0][c], src[1][c]);
3117 case TGSI_OPCODE_UMAD:
3120 temp = temp_temp(pc, NULL);
3121 for (c = 0; c < 4; c++) {
3122 if (!(mask & (1 << c)))
3124 emit_mul_u16(pc, temp, src[0][c], 0, src[1][c], 1);
3125 emit_mad_u16(pc, temp, src[0][c], 1, src[1][c], 0,
3127 emit_shl_imm(pc, temp, temp, 16);
3128 emit_mad_u16(pc, temp, src[0][c], 0, src[1][c], 0,
3130 emit_add_b32(pc, dst[c], temp, src[2][c]);
3134 case TGSI_OPCODE_UMUL:
3137 temp = temp_temp(pc, NULL);
3138 for (c = 0; c < 4; c++) {
3139 if (!(mask & (1 << c)))
3141 emit_mul_u16(pc, temp, src[0][c], 0, src[1][c], 1);
3142 emit_mad_u16(pc, temp, src[0][c], 1, src[1][c], 0,
3144 emit_shl_imm(pc, temp, temp, 16);
3145 emit_mad_u16(pc, dst[c], src[0][c], 0, src[1][c], 0,
3150 case TGSI_OPCODE_XPD:
3151 temp = temp_temp(pc, NULL);
3152 if (mask & (1 << 0)) {
3153 emit_mul(pc, temp, src[0][2], src[1][1]);
3154 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
3156 if (mask & (1 << 1)) {
3157 emit_mul(pc, temp, src[0][0], src[1][2]);
3158 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
3160 if (mask & (1 << 2)) {
3161 emit_mul(pc, temp, src[0][1], src[1][0]);
3162 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
3164 if (mask & (1 << 3))
3165 emit_mov_immdval(pc, dst[3], 1.0);
3167 case TGSI_OPCODE_END:
3168 if (pc->p->type == PIPE_SHADER_FRAGMENT)
3169 nv50_fp_move_results(pc);
3171 /* last insn must be long so it can have the exit bit set */
3172 if (!is_long(pc->p->exec_tail))
3173 convert_to_long(pc, pc->p->exec_tail);
3175 if (is_immd(pc->p->exec_tail) ||
3176 is_join(pc->p->exec_tail) ||
3177 is_control_flow(pc->p->exec_tail))
3180 pc->p->exec_tail->inst[1] |= 1; /* set exit bit */
3185 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
3191 emit_sat(pc, brdc, brdc);
3192 for (c = 0; c < 4; c++)
3193 if ((mask & (1 << c)) && dst[c] != brdc)
3194 emit_mov(pc, dst[c], brdc);
3197 for (c = 0; c < 4; c++) {
3198 if (!(mask & (1 << c)))
3200 /* In this case we saturate later, and dst[c] won't
3201 * be another temp_temp (and thus lost), since rdst
3202 * already is TEMP (see above). */
3203 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
3205 emit_sat(pc, rdst[c], dst[c]);
3209 kill_temp_temp(pc, NULL);
3210 pc->reg_instance_nr = 0;
3216 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
3218 struct nv50_reg *r, *reg = NULL;
3219 const struct tgsi_full_src_register *src;
3220 const struct tgsi_dst_register *dst;
3221 unsigned i, c, k, mask;
3223 dst = &insn->Dst[0].Register;
3224 mask = dst->WriteMask;
3226 if (dst->File == TGSI_FILE_TEMPORARY)
3229 if (dst->File == TGSI_FILE_OUTPUT) {
3232 if (insn->Instruction.Opcode == TGSI_OPCODE_MOV &&
3233 dst->Index == pc->edgeflag_out &&
3234 insn->Src[0].Register.File == TGSI_FILE_INPUT)
3235 pc->p->cfg.edgeflag_in = insn->Src[0].Register.Index;
3239 for (c = 0; c < 4; c++) {
3240 if (!(mask & (1 << c)))
3242 reg[dst->Index * 4 + c].acc = pc->insn_nr;
3246 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
3247 src = &insn->Src[i];
3249 if (src->Register.File == TGSI_FILE_TEMPORARY)
3252 if (src->Register.File == TGSI_FILE_INPUT)
3257 mask = nv50_tgsi_src_mask(insn, i);
3259 for (c = 0; c < 4; c++) {
3260 if (!(mask & (1 << c)))
3262 k = tgsi_util_get_full_src_register_swizzle(src, c);
3264 r = ®[src->Register.Index * 4 + k];
3266 /* If used before written, pre-allocate the reg,
3267 * lest we overwrite results from a subroutine.
3269 if (!r->acc && r->type == P_TEMP)
3272 r->acc = pc->insn_nr;
3277 /* Returns a bitmask indicating which dst components need to be
3278 * written to temporaries first to avoid 'corrupting' sources.
3280 * m[i] (out) indicate component to write in the i-th position
3281 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
3284 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
3286 unsigned i, c, x, unsafe = 0;
3288 for (c = 0; c < 4; c++)
3291 /* Swap as long as a dst component written earlier is depended on
3292 * by one written later, but the next one isn't depended on by it.
3294 for (c = 0; c < 3; c++) {
3295 if (rdep[m[c + 1]] & (1 << m[c]))
3296 continue; /* if next one is depended on by us */
3297 for (i = c + 1; i < 4; i++)
3298 /* if we are depended on by a later one */
3299 if (rdep[m[c]] & (1 << m[i]))
3312 /* mark dependencies that could not be resolved by reordering */
3313 for (i = 0; i < 3; ++i)
3314 for (c = i + 1; c < 4; ++c)
3315 if (rdep[m[i]] & (1 << m[c]))
3318 /* NOTE: $unsafe is with respect to order, not component */
3322 /* Select a suitable dst register for broadcasting scalar results,
3323 * or return NULL if we have to allocate an extra TEMP.
3325 * If e.g. only 1 component is written, we may also emit the final
3326 * result to a write-only register.
3328 static struct nv50_reg *
3329 tgsi_broadcast_dst(struct nv50_pc *pc,
3330 const struct tgsi_full_dst_register *fd, unsigned mask)
3332 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
3333 int c = ffs(~mask & fd->Register.WriteMask);
3335 return tgsi_dst(pc, c - 1, fd);
3337 int c = ffs(fd->Register.WriteMask) - 1;
3338 if ((1 << c) == fd->Register.WriteMask)
3339 return tgsi_dst(pc, c, fd);
3345 /* Scan source swizzles and return a bitmask indicating dst regs that
3346 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
3349 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
3352 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
3353 const struct tgsi_full_src_register *fs;
3354 unsigned i, deqs = 0;
3356 for (i = 0; i < 4; ++i)
3359 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
3360 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
3361 int ms = get_supported_mods(insn, i);
3364 if (fs->Register.File != fd->Register.File ||
3365 fs->Register.Index != fd->Register.Index)
3368 for (chn = 0; chn < 4; ++chn) {
3371 if (!(mask & (1 << chn))) /* src is not read */
3373 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
3374 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
3376 if (!(fd->Register.WriteMask & (1 << c)))
3379 if (s == TGSI_UTIL_SIGN_TOGGLE && !(ms & NV50_MOD_NEG))
3381 if (s == TGSI_UTIL_SIGN_CLEAR && !(ms & NV50_MOD_ABS))
3383 if ((s == TGSI_UTIL_SIGN_SET) && ((ms & 3) != 3))
3386 rdep[c] |= nv50_tgsi_dst_revdep(
3387 insn->Instruction.Opcode, i, chn);
3396 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
3398 struct tgsi_full_instruction insn = tok->FullInstruction;
3399 const struct tgsi_full_dst_register *fd;
3400 unsigned i, deqs, rdep[4], m[4];
3402 fd = &tok->FullInstruction.Dst[0];
3403 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
3405 if (is_scalar_op(insn.Instruction.Opcode)) {
3406 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
3408 pc->r_brdc = temp_temp(pc, NULL);
3409 return nv50_program_tx_insn(pc, &insn);
3413 if (!deqs || (!rdep[0] && !rdep[1] && !rdep[2] && !rdep[3]))
3414 return nv50_program_tx_insn(pc, &insn);
3416 deqs = nv50_revdep_reorder(m, rdep);
3418 for (i = 0; i < 4; ++i) {
3419 assert(pc->r_dst[m[i]] == NULL);
3421 insn.Dst[0].Register.WriteMask =
3422 fd->Register.WriteMask & (1 << m[i]);
3424 if (!insn.Dst[0].Register.WriteMask)
3427 if (deqs & (1 << i))
3428 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
3430 if (!nv50_program_tx_insn(pc, &insn))
3434 for (i = 0; i < 4; i++) {
3435 struct nv50_reg *reg = pc->r_dst[i];
3438 pc->r_dst[i] = NULL;
3440 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
3441 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
3443 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
3451 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
3453 struct nv50_reg *iv, **ppiv;
3454 unsigned mode = pc->interp_mode[reg->index];
3456 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
3459 if ((mode & INTERP_PERSPECTIVE) && !iv) {
3460 iv = *ppiv = alloc_temp(pc, NULL);
3461 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
3463 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
3464 emit_flop(pc, NV50_FLOP_RCP, iv, iv);
3466 /* XXX: when loading interpolants dynamically, move these
3467 * to the program head, or make sure it can't be skipped.
3471 emit_interp(pc, reg, iv, mode);
3474 /* The face input is always at v[255] (varying space), with a
3475 * value of 0 for back-facing, and 0xffffffff for front-facing.
3478 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *sv)
3480 struct nv50_reg *temp = alloc_temp(pc, NULL);
3484 emit_interp(pc, temp, NULL, INTERP_FLAT);
3486 emit_cvt(pc, sv, temp, r_pred, CVT_ABS | CVT_F32_S32);
3488 emit_not(pc, temp, temp);
3489 set_pred(pc, 0x2, r_pred, pc->p->exec_tail);
3490 emit_cvt(pc, sv, temp, -1, CVT_F32_S32);
3491 set_pred(pc, 0x2, r_pred, pc->p->exec_tail);
3493 free_temp(pc, temp);
3497 load_instance_id(struct nv50_pc *pc, unsigned index)
3499 struct nv50_reg reg, mem;
3501 ctor_reg(®, P_TEMP, -1, -1);
3502 ctor_reg(&mem, P_CONST, -1, 24); /* startInstance */
3505 emit_add_b32(pc, ®, &pc->sysval[index], &mem);
3506 pc->sysval[index] = reg;
3510 copy_semantic_info(struct nv50_program *p)
3514 for (i = 0; i < p->cfg.in_nr; ++i) {
3515 id = p->cfg.in[i].id;
3516 p->cfg.in[i].sn = p->info.input_semantic_name[id];
3517 p->cfg.in[i].si = p->info.input_semantic_index[id];
3520 for (i = 0; i < p->cfg.out_nr; ++i) {
3521 id = p->cfg.out[i].id;
3522 p->cfg.out[i].sn = p->info.output_semantic_name[id];
3523 p->cfg.out[i].si = p->info.output_semantic_index[id];
3528 nv50_program_tx_prep(struct nv50_pc *pc)
3530 struct tgsi_parse_context tp;
3531 struct nv50_program *p = pc->p;
3532 boolean ret = FALSE;
3533 unsigned i, c, instance_id, vertex_id, flat_nr = 0;
3535 tgsi_parse_init(&tp, pc->p->pipe.tokens);
3536 while (!tgsi_parse_end_of_tokens(&tp)) {
3537 const union tgsi_full_token *tok = &tp.FullToken;
3539 tgsi_parse_token(&tp);
3540 switch (tok->Token.Type) {
3541 case TGSI_TOKEN_TYPE_IMMEDIATE:
3543 const struct tgsi_full_immediate *imm =
3544 &tp.FullToken.FullImmediate;
3546 ctor_immd_4f32(pc, imm->u[0].Float,
3552 case TGSI_TOKEN_TYPE_DECLARATION:
3554 const struct tgsi_full_declaration *d;
3555 unsigned si, last, first, mode;
3557 d = &tp.FullToken.FullDeclaration;
3558 first = d->Range.First;
3559 last = d->Range.Last;
3561 switch (d->Declaration.File) {
3562 case TGSI_FILE_TEMPORARY:
3564 case TGSI_FILE_OUTPUT:
3565 if (!d->Declaration.Semantic ||
3566 p->type == PIPE_SHADER_FRAGMENT)
3569 si = d->Semantic.Index;
3570 switch (d->Semantic.Name) {
3571 case TGSI_SEMANTIC_BCOLOR:
3572 p->cfg.two_side[si].hw = first;
3573 if (p->cfg.out_nr > first)
3574 p->cfg.out_nr = first;
3576 case TGSI_SEMANTIC_PSIZE:
3577 p->cfg.psiz = first;
3578 if (p->cfg.out_nr > first)
3579 p->cfg.out_nr = first;
3581 case TGSI_SEMANTIC_EDGEFLAG:
3582 pc->edgeflag_out = first;
3585 case TGSI_SEMANTIC_CLIP_DISTANCE:
3586 p->cfg.clpd = MIN2(p->cfg.clpd, first);
3593 case TGSI_FILE_INPUT:
3595 if (p->type != PIPE_SHADER_FRAGMENT)
3598 switch (d->Declaration.Interpolate) {
3599 case TGSI_INTERPOLATE_CONSTANT:
3603 case TGSI_INTERPOLATE_PERSPECTIVE:
3604 mode = INTERP_PERSPECTIVE;
3605 p->cfg.regs[1] |= 0x08 << 24;
3608 mode = INTERP_LINEAR;
3611 if (d->Declaration.Centroid)
3612 mode |= INTERP_CENTROID;
3615 for (i = first; i <= last; i++)
3616 pc->interp_mode[i] = mode;
3619 case TGSI_FILE_SYSTEM_VALUE:
3620 assert(d->Declaration.Semantic);
3621 switch (d->Semantic.Name) {
3622 case TGSI_SEMANTIC_FACE:
3623 assert(p->type == PIPE_SHADER_FRAGMENT);
3624 load_frontfacing(pc,
3625 &pc->sysval[first]);
3627 case TGSI_SEMANTIC_INSTANCEID:
3628 assert(p->type == PIPE_SHADER_VERTEX);
3629 instance_id = first;
3630 p->cfg.regs[0] |= (1 << 4);
3632 case TGSI_SEMANTIC_PRIMID:
3633 assert(p->type != PIPE_SHADER_VERTEX);
3634 p->cfg.prim_id = first;
3637 case TGSI_SEMANTIC_PRIMIDIN:
3638 assert(p->type == PIPE_SHADER_GEOMETRY);
3639 pc->sysval[first].hw = 6;
3640 p->cfg.regs[0] |= (1 << 8);
3642 case TGSI_SEMANTIC_VERTEXID:
3643 assert(p->type == PIPE_SHADER_VERTEX);
3645 p->cfg.regs[0] |= (1 << 12) | (1 << 0);
3650 case TGSI_FILE_ADDRESS:
3651 case TGSI_FILE_CONSTANT:
3652 case TGSI_FILE_SAMPLER:
3655 NOUVEAU_ERR("bad decl file %d\n",
3656 d->Declaration.File);
3661 case TGSI_TOKEN_TYPE_INSTRUCTION:
3663 prep_inspect_insn(pc, &tok->FullInstruction);
3670 if (p->type == PIPE_SHADER_VERTEX || p->type == PIPE_SHADER_GEOMETRY) {
3673 if (p->type == PIPE_SHADER_GEOMETRY) {
3674 for (i = 0; i < pc->attr_nr; ++i) {
3675 p->cfg.in[i].hw = rid;
3676 p->cfg.in[i].id = i;
3678 for (c = 0; c < 4; ++c) {
3680 if (!pc->attr[n].acc)
3682 pc->attr[n].hw = rid++;
3683 p->cfg.in[i].mask |= 1 << c;
3687 for (i = 0; i < pc->attr_nr * 4; ++i) {
3688 if (pc->attr[i].acc) {
3689 pc->attr[i].hw = rid++;
3690 p->cfg.attr[i / 32] |= 1 << (i % 32);
3693 if (p->cfg.regs[0] & (1 << 0))
3694 pc->sysval[vertex_id].hw = rid++;
3695 if (p->cfg.regs[0] & (1 << 4)) {
3696 pc->sysval[instance_id].hw = rid++;
3697 load_instance_id(pc, instance_id);
3701 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
3702 p->cfg.out[i].hw = rid;
3703 p->cfg.out[i].id = i;
3705 for (c = 0; c < 4; ++c) {
3707 if (!pc->result[n].acc)
3709 pc->result[n].hw = rid++;
3710 p->cfg.out[i].mask |= 1 << c;
3713 if (p->cfg.prim_id < 0x40) {
3714 /* GP has to write to PrimitiveID */
3715 ctor_reg(&pc->sysval[p->cfg.prim_id],
3716 P_RESULT, p->cfg.prim_id, rid);
3717 p->cfg.prim_id = rid++;
3720 for (c = 0; c < 2; ++c)
3721 if (p->cfg.two_side[c].hw < 0x40)
3722 p->cfg.two_side[c] = p->cfg.out[
3723 p->cfg.two_side[c].hw];
3725 if (p->cfg.psiz < 0x40)
3726 p->cfg.psiz = p->cfg.out[p->cfg.psiz].hw;
3728 copy_semantic_info(p);
3730 if (p->type == PIPE_SHADER_FRAGMENT) {
3732 unsigned n = 0, m = pc->attr_nr - flat_nr;
3736 /* do we read FragCoord ? */
3738 p->info.input_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
3739 /* select FCRD components we want accessible */
3740 for (c = 0; c < 4; ++c)
3741 if (pc->attr[c].acc)
3742 p->cfg.regs[1] |= 1 << (24 + c);
3744 } else /* offset by 1 if FCRD.w is needed for pinterp */
3745 aid = popcnt4(p->cfg.regs[1] >> 24);
3747 /* non-flat interpolants have to be mapped to
3748 * the lower hardware IDs, so sort them:
3750 for (i = 0; i < pc->attr_nr; i++) {
3751 if (pc->interp_mode[i] == INTERP_FLAT)
3752 p->cfg.in[m++].id = i;
3754 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
3755 p->cfg.in[n].linear = TRUE;
3756 p->cfg.in[n++].id = i;
3759 copy_semantic_info(p);
3761 for (n = 0; n < pc->attr_nr; ++n) {
3762 p->cfg.in[n].hw = rid = aid;
3763 i = p->cfg.in[n].id;
3765 if (p->info.input_semantic_name[n] ==
3766 TGSI_SEMANTIC_FACE) {
3767 load_frontfacing(pc, &pc->attr[i * 4]);
3771 for (c = 0; c < 4; ++c) {
3772 if (!pc->attr[i * 4 + c].acc)
3774 pc->attr[i * 4 + c].rhw = rid++;
3775 p->cfg.in[n].mask |= 1 << c;
3777 load_interpolant(pc, &pc->attr[i * 4 + c]);
3779 aid += popcnt4(p->cfg.in[n].mask);
3782 m = popcnt4(p->cfg.regs[1] >> 24);
3784 /* set count of non-position inputs and of non-flat
3785 * non-position inputs for FP_INTERPOLANT_CTRL
3787 p->cfg.regs[1] |= aid - m;
3790 i = p->cfg.in[pc->attr_nr - flat_nr].hw;
3791 p->cfg.regs[1] |= (i - m) << 16;
3793 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
3795 /* mark color semantic for light-twoside */
3797 for (i = 0; i < p->cfg.in_nr; i++) {
3798 if (p->cfg.in[i].sn == TGSI_SEMANTIC_COLOR) {
3799 n = MIN2(n, p->cfg.in[i].hw - m);
3800 p->cfg.two_side[p->cfg.in[i].si] = p->cfg.in[i];
3802 p->cfg.regs[0] += /* increase colour count */
3803 popcnt4(p->cfg.in[i].mask) << 16;
3807 p->cfg.regs[0] += n;
3809 if (p->cfg.prim_id < 0x40) {
3810 pc->sysval[p->cfg.prim_id].rhw = rid++;
3811 emit_interp(pc, &pc->sysval[p->cfg.prim_id], NULL,
3813 /* increase FP_INTERPOLANT_CTRL_COUNT */
3814 p->cfg.regs[1] += 1;
3817 /* Initialize FP results:
3818 * FragDepth is always first TGSI and last hw output
3820 i = p->info.writes_z ? 4 : 0;
3821 for (rid = 0; i < pc->result_nr * 4; i++)
3822 pc->result[i].rhw = rid++;
3823 if (p->info.writes_z)
3824 pc->result[2].rhw = rid;
3826 p->cfg.high_result = rid;
3828 /* separate/different colour results for MRTs ? */
3829 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
3830 p->cfg.regs[2] |= 1;
3836 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
3840 for (i = 0; i < pc->immd_nr; i++) {
3841 for (c = 0; c < 4; c++, rid++)
3842 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
3849 free_temp(pc, pc->iv_p);
3851 free_temp(pc, pc->iv_c);
3853 tgsi_parse_free(&tp);
3858 free_nv50_pc(struct nv50_pc *pc)
3878 static INLINE uint32_t
3879 nv50_map_gs_output_prim(unsigned pprim)
3882 case PIPE_PRIM_POINTS:
3883 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_POINTS;
3884 case PIPE_PRIM_LINE_STRIP:
3885 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_LINE_STRIP;
3886 case PIPE_PRIM_TRIANGLE_STRIP:
3887 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_TRIANGLE_STRIP;
3889 NOUVEAU_ERR("invalid GS_OUTPUT_PRIMITIVE: %u\n", pprim);
3896 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3899 unsigned rtype[2] = { P_ATTR, P_RESULT };
3902 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3903 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3904 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3905 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3906 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3907 assert(pc->addr_nr <= 2);
3908 pc->sysval_nr = p->info.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
3910 p->cfg.high_temp = 4;
3912 p->cfg.two_side[0].hw = 0x40;
3913 p->cfg.two_side[1].hw = 0x40;
3914 p->cfg.prim_id = 0x40;
3916 p->cfg.edgeflag_in = pc->edgeflag_out = 0xff;
3918 for (i = 0; i < p->info.num_properties; ++i) {
3919 unsigned *data = &p->info.properties[i].data[0];
3921 switch (p->info.properties[i].name) {
3922 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
3923 p->cfg.prim_type = nv50_map_gs_output_prim(data[0]);
3925 case TGSI_PROPERTY_GS_MAX_VERTICES:
3926 p->cfg.vert_count = data[0];
3934 case PIPE_SHADER_VERTEX:
3937 p->cfg.out_nr = pc->result_nr;
3939 case PIPE_SHADER_GEOMETRY:
3940 assert(p->cfg.prim_type);
3941 assert(p->cfg.vert_count);
3945 p->cfg.prim_id = 0x80;
3946 p->cfg.out_nr = pc->result_nr;
3947 p->cfg.in_nr = pc->attr_nr;
3949 p->cfg.two_side[0].hw = 0x80;
3950 p->cfg.two_side[1].hw = 0x80;
3952 case PIPE_SHADER_FRAGMENT:
3953 rtype[0] = rtype[1] = P_TEMP;
3955 p->cfg.regs[0] = 0x01000004;
3956 p->cfg.in_nr = pc->attr_nr;
3958 if (p->info.writes_z) {
3959 p->cfg.regs[2] |= 0x00000100;
3960 p->cfg.regs[3] |= 0x00000011;
3962 if (p->info.uses_kill)
3963 p->cfg.regs[2] |= 0x00100000;
3968 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3972 for (i = 0; i < pc->temp_nr * 4; ++i)
3973 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3977 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3981 for (i = 0; i < pc->attr_nr * 4; ++i)
3982 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3985 if (pc->result_nr) {
3986 unsigned nr = pc->result_nr * 4;
3988 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3992 for (i = 0; i < nr; ++i)
3993 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
3999 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
4003 for (i = 0; i < pc->param_nr; ++i)
4004 for (c = 0; c < 4; ++c, ++rid)
4005 ctor_reg(&pc->param[rid], P_CONST, i, rid);
4009 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
4013 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
4014 ctor_reg(&pc->r_addr[i], P_ADDR, -1, i + 1);
4016 if (pc->sysval_nr) {
4017 pc->sysval = CALLOC(pc->sysval_nr, sizeof(struct nv50_reg *));
4020 /* will only ever use SYSTEM_VALUE[i].x (hopefully) */
4021 for (i = 0; i < pc->sysval_nr; ++i)
4022 ctor_reg(&pc->sysval[i], rtype[0], i, -1);
4029 nv50_program_fixup_insns(struct nv50_pc *pc)
4031 struct nv50_program_exec *e, **bra_list;
4034 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
4036 /* Collect branch instructions, we need to adjust their offsets
4037 * when converting 32 bit instructions to 64 bit ones
4039 for (n = 0, e = pc->p->exec_head; e; e = e->next)
4040 if (e->param.index >= 0 && !e->param.mask)
4043 /* Make sure we don't have any single 32 bit instructions. */
4044 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
4045 pos += is_long(e) ? 2 : 1;
4047 if ((pos & 1) && (!e->next || is_long(e->next))) {
4048 for (i = 0; i < n; ++i)
4049 if (bra_list[i]->param.index >= pos)
4050 bra_list[i]->param.index += 1;
4051 for (i = 0; i < pc->insn_nr; ++i)
4052 if (pc->insn_pos[i] >= pos)
4053 pc->insn_pos[i] += 1;
4054 convert_to_long(pc, e);
4061 if (!pc->p->info.opcode_count[TGSI_OPCODE_CAL])
4064 /* fill in CALL offsets */
4065 for (e = pc->p->exec_head; e; e = e->next) {
4066 if ((e->inst[0] & 2) && (e->inst[0] >> 28) == 0x2)
4067 e->param.index = pc->insn_pos[e->param.index];
4072 nv50_program_tx(struct nv50_program *p)
4074 struct tgsi_parse_context parse;
4078 pc = CALLOC_STRUCT(nv50_pc);
4082 ret = ctor_nv50_pc(pc, p);
4086 ret = nv50_program_tx_prep(pc);
4090 pc->insn_pos = MALLOC(pc->insn_nr * sizeof(unsigned));
4092 tgsi_parse_init(&parse, pc->p->pipe.tokens);
4093 while (!tgsi_parse_end_of_tokens(&parse)) {
4094 const union tgsi_full_token *tok = &parse.FullToken;
4096 /* previously allow32 was FALSE for first & last instruction */
4099 tgsi_parse_token(&parse);
4101 switch (tok->Token.Type) {
4102 case TGSI_TOKEN_TYPE_INSTRUCTION:
4103 pc->insn_pos[pc->insn_cur] = pc->p->exec_size;
4105 ret = nv50_tgsi_insn(pc, tok);
4114 nv50_program_fixup_insns(pc);
4116 p->param_nr = pc->param_nr * 4;
4117 p->immd_nr = pc->immd_nr * 4;
4118 p->immd = pc->immd_buf;
4121 tgsi_parse_free(&parse);
4129 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
4131 if (nv50_program_tx(p) == FALSE)
4133 p->translated = TRUE;
4137 nv50_program_upload_data(struct nv50_context *nv50, uint32_t *map,
4138 unsigned start, unsigned count, unsigned cbuf)
4140 struct nouveau_channel *chan = nv50->screen->base.channel;
4141 struct nouveau_grobj *tesla = nv50->screen->tesla;
4144 unsigned nr = count > 2047 ? 2047 : count;
4146 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
4147 OUT_RING (chan, (cbuf << 0) | (start << 8));
4148 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
4149 OUT_RINGp (chan, map, nr);
4158 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
4160 struct pipe_screen *pscreen = nv50->pipe.screen;
4162 if (!p->data[0] && p->immd_nr) {
4163 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
4165 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
4166 while (heap->next && heap->size < p->immd_nr) {
4167 struct nv50_program *evict = heap->next->priv;
4168 nouveau_resource_free(&evict->data[0]);
4171 if (nouveau_resource_alloc(heap, p->immd_nr, p,
4176 /* immediates only need to be uploaded again when freed */
4177 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
4178 p->immd_nr, NV50_CB_PMISC);
4181 assert(p->param_nr <= 512);
4185 uint32_t *map = pipe_buffer_map(pscreen,
4186 nv50->constbuf[p->type],
4187 PIPE_BUFFER_USAGE_CPU_READ);
4189 case PIPE_SHADER_GEOMETRY: cb = NV50_CB_PGP; break;
4190 case PIPE_SHADER_FRAGMENT: cb = NV50_CB_PFP; break;
4193 assert(p->type == PIPE_SHADER_VERTEX);
4197 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
4198 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
4203 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
4205 struct nouveau_channel *chan = nv50->screen->base.channel;
4206 struct nv50_program_exec *e;
4208 boolean upload = FALSE;
4211 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
4212 p->exec_size * 4, &p->bo);
4216 if (p->data[0] && p->data[0]->start != p->data_start[0])
4222 up = MALLOC(p->exec_size * 4);
4224 for (i = 0, e = p->exec_head; e; e = e->next) {
4225 unsigned ei, ci, bs;
4227 if (e->param.index >= 0 && e->param.mask) {
4228 bs = (e->inst[1] >> 22) & 0x07;
4230 ei = e->param.shift >> 5;
4231 ci = e->param.index;
4233 ci += p->data[bs]->start;
4235 e->inst[ei] &= ~e->param.mask;
4236 e->inst[ei] |= (ci << e->param.shift);
4238 if (e->param.index >= 0) {
4239 /* zero mask means param is a jump/branch offset */
4240 assert(!(e->param.index & 1));
4241 /* seem to be 8 byte steps */
4242 ei = (e->param.index >> 1) + 0 /* START_ID */;
4244 e->inst[0] &= 0xf0000fff;
4245 e->inst[0] |= ei << 12;
4248 up[i++] = e->inst[0];
4250 up[i++] = e->inst[1];
4252 assert(i == p->exec_size);
4255 p->data_start[0] = p->data[0]->start;
4257 #ifdef NV50_PROGRAM_DUMP
4258 NOUVEAU_ERR("-------\n");
4259 for (e = p->exec_head; e; e = e->next) {
4260 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
4262 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
4265 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
4266 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
4267 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
4268 0, 0, p->exec_size * 4, 1, 1);
4274 nv50_vertprog_validate(struct nv50_context *nv50)
4276 struct nouveau_grobj *tesla = nv50->screen->tesla;
4277 struct nv50_program *p = nv50->vertprog;
4278 struct nouveau_stateobj *so;
4280 if (!p->translated) {
4281 nv50_program_validate(nv50, p);
4286 nv50_program_validate_data(nv50, p);
4287 nv50_program_validate_code(nv50, p);
4289 so = so_new(5, 7, 2);
4290 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
4291 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4292 NOUVEAU_BO_HIGH, 0, 0);
4293 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4294 NOUVEAU_BO_LOW, 0, 0);
4295 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
4296 so_data (so, p->cfg.attr[0]);
4297 so_data (so, p->cfg.attr[1]);
4298 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
4299 so_data (so, p->cfg.high_result);
4300 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_TEMP, 1);
4301 so_data (so, p->cfg.high_temp);
4302 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
4303 so_data (so, 0); /* program start offset */
4304 so_ref(so, &nv50->state.vertprog);
4309 nv50_fragprog_validate(struct nv50_context *nv50)
4311 struct nouveau_grobj *tesla = nv50->screen->tesla;
4312 struct nv50_program *p = nv50->fragprog;
4313 struct nouveau_stateobj *so;
4315 if (!p->translated) {
4316 nv50_program_validate(nv50, p);
4321 nv50_program_validate_data(nv50, p);
4322 nv50_program_validate_code(nv50, p);
4324 so = so_new(6, 7, 2);
4325 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
4326 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4327 NOUVEAU_BO_HIGH, 0, 0);
4328 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4329 NOUVEAU_BO_LOW, 0, 0);
4330 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
4331 so_data (so, p->cfg.high_temp);
4332 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
4333 so_data (so, p->cfg.high_result);
4334 so_method(so, tesla, NV50TCL_FP_CONTROL, 1);
4335 so_data (so, p->cfg.regs[2]);
4336 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
4337 so_data (so, p->cfg.regs[3]);
4338 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
4339 so_data (so, 0); /* program start offset */
4340 so_ref(so, &nv50->state.fragprog);
4345 nv50_geomprog_validate(struct nv50_context *nv50)
4347 struct nouveau_grobj *tesla = nv50->screen->tesla;
4348 struct nv50_program *p = nv50->geomprog;
4349 struct nouveau_stateobj *so;
4351 if (!p->translated) {
4352 nv50_program_validate(nv50, p);
4357 nv50_program_validate_data(nv50, p);
4358 nv50_program_validate_code(nv50, p);
4360 so = so_new(6, 7, 2);
4361 so_method(so, tesla, NV50TCL_GP_ADDRESS_HIGH, 2);
4362 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4363 NOUVEAU_BO_HIGH, 0, 0);
4364 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4365 NOUVEAU_BO_LOW, 0, 0);
4366 so_method(so, tesla, NV50TCL_GP_REG_ALLOC_TEMP, 1);
4367 so_data (so, p->cfg.high_temp);
4368 so_method(so, tesla, NV50TCL_GP_REG_ALLOC_RESULT, 1);
4369 so_data (so, p->cfg.high_result);
4370 so_method(so, tesla, NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE, 1);
4371 so_data (so, p->cfg.prim_type);
4372 so_method(so, tesla, NV50TCL_GP_VERTEX_OUTPUT_COUNT, 1);
4373 so_data (so, p->cfg.vert_count);
4374 so_method(so, tesla, NV50TCL_GP_START_ID, 1);
4376 so_ref(so, &nv50->state.geomprog);
4381 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
4383 struct nv50_program *vp;
4384 struct nv50_program *fp = nv50->fragprog;
4385 unsigned i, c, m = base;
4386 uint32_t origin = 0x00000010;
4388 vp = nv50->geomprog ? nv50->geomprog : nv50->vertprog;
4390 /* XXX: this might not work correctly in all cases yet - we'll
4391 * just assume that an FP generic input that is not written in
4392 * the VP is PointCoord.
4394 memset(pntc, 0, 8 * sizeof(uint32_t));
4396 for (i = 0; i < fp->cfg.in_nr; i++) {
4397 unsigned j, n = popcnt4(fp->cfg.in[i].mask);
4399 if (fp->cfg.in[i].sn != TGSI_SEMANTIC_GENERIC) {
4404 for (j = 0; j < vp->cfg.out_nr; ++j)
4405 if (vp->cfg.out[j].sn == fp->cfg.in[i].sn &&
4406 vp->cfg.out[j].si == fp->cfg.in[i].si)
4409 if (j < vp->cfg.out_nr) {
4410 ubyte mode = nv50->rasterizer->pipe.sprite_coord_mode[
4413 if (mode == PIPE_SPRITE_COORD_NONE) {
4417 if (mode == PIPE_SPRITE_COORD_LOWER_LEFT)
4421 /* this is either PointCoord or replaced by sprite coords */
4422 for (c = 0; c < 4; c++) {
4423 if (!(fp->cfg.in[i].mask & (1 << c)))
4425 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
4433 nv50_vec4_map(uint32_t *map32, int mid, uint8_t zval, uint32_t lin[4],
4434 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
4437 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
4438 uint8_t *map = (uint8_t *)map32;
4440 for (c = 0; c < 4; ++c) {
4442 if (fpi->linear == TRUE)
4443 lin[mid / 32] |= 1 << (mid % 32);
4447 map[mid] = (c == 3) ? (zval + 1) : zval;
4460 nv50_fp_linkage_validate(struct nv50_context *nv50)
4462 struct nouveau_grobj *tesla = nv50->screen->tesla;
4463 struct nv50_program *vp = nv50->vertprog;
4464 struct nv50_program *fp = nv50->fragprog;
4465 struct nouveau_stateobj *so;
4466 struct nv50_sreg4 dummy;
4468 uint32_t map[16], lin[4], reg[6], pcrd[8];
4469 uint8_t zval = 0x40;
4471 if (nv50->geomprog) {
4472 vp = nv50->geomprog;
4475 memset(map, 0, sizeof(map));
4476 memset(lin, 0, sizeof(lin));
4478 reg[1] = 0x00000004; /* low and high clip distance map ids */
4479 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
4480 reg[3] = 0x00000000; /* point size map id & enable */
4481 reg[5] = 0x00000000; /* primitive ID map slot */
4482 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
4483 reg[4] = fp->cfg.regs[1]; /* interpolant info */
4485 dummy.linear = FALSE;
4486 dummy.mask = 0xf; /* map all components of HPOS */
4487 m = nv50_vec4_map(map, m, zval, lin, &dummy, &vp->cfg.out[0]);
4491 if (vp->cfg.clpd < 0x40) {
4492 for (c = 0; c < vp->cfg.clpd_nr; ++c) {
4493 map[m / 4] |= (vp->cfg.clpd + c) << ((m % 4) * 8);
4499 reg[0] |= m << 8; /* adjust BFC0 id */
4501 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
4502 if (nv50->rasterizer->pipe.light_twoside) {
4503 struct nv50_sreg4 *vpo = &vp->cfg.two_side[0];
4504 struct nv50_sreg4 *fpi = &fp->cfg.two_side[0];
4506 m = nv50_vec4_map(map, m, zval, lin, &fpi[0], &vpo[0]);
4507 m = nv50_vec4_map(map, m, zval, lin, &fpi[1], &vpo[1]);
4510 reg[0] += m - 4; /* adjust FFC0 id */
4511 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
4513 for (i = 0; i < fp->cfg.in_nr; i++) {
4514 /* maybe even remove these from cfg.io */
4515 if (fp->cfg.in[i].sn == TGSI_SEMANTIC_POSITION ||
4516 fp->cfg.in[i].sn == TGSI_SEMANTIC_FACE)
4519 for (n = 0; n < vp->cfg.out_nr; ++n)
4520 if (vp->cfg.out[n].sn == fp->cfg.in[i].sn &&
4521 vp->cfg.out[n].si == fp->cfg.in[i].si)
4524 m = nv50_vec4_map(map, m, zval, lin, &fp->cfg.in[i],
4525 (n < vp->cfg.out_nr) ?
4526 &vp->cfg.out[n] : &dummy);
4528 /* PrimitiveID either is replaced by the system value, or
4529 * written by the geometry shader into an output register
4531 if (fp->cfg.prim_id < 0x40) {
4532 map[m / 4] |= vp->cfg.prim_id << ((m % 4) * 8);
4536 if (nv50->rasterizer->pipe.point_size_per_vertex) {
4537 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
4538 reg[3] = (m++ << 4) | 1;
4541 /* now fill the stateobj (at most 28 so_data) */
4542 so = so_new(10, 54, 0);
4546 if (vp->type == PIPE_SHADER_GEOMETRY) {
4547 so_method(so, tesla, NV50TCL_GP_RESULT_MAP_SIZE, 1);
4549 so_method(so, tesla, NV50TCL_GP_RESULT_MAP(0), n);
4550 so_datap (so, map, n);
4552 so_method(so, tesla, NV50TCL_VP_GP_BUILTIN_ATTR_EN, 1);
4553 so_data (so, vp->cfg.regs[0]);
4555 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_4, 1);
4556 so_data (so, reg[5]);
4558 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
4560 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
4561 so_datap (so, map, n);
4564 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
4565 so_datap (so, reg, 4);
4567 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
4568 so_data (so, reg[4]);
4570 so_method(so, tesla, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
4571 so_datap (so, lin, 4);
4573 if (nv50->rasterizer->pipe.point_sprite) {
4574 so_method(so, tesla, NV50TCL_POINT_SPRITE_CTRL, 1);
4576 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff));
4578 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
4579 so_datap (so, pcrd, 8);
4582 so_method(so, tesla, NV50TCL_GP_ENABLE, 1);
4583 so_data (so, (vp->type == PIPE_SHADER_GEOMETRY) ? 1 : 0);
4585 so_ref(so, &nv50->state.fp_linkage);
4590 construct_vp_gp_mapping(uint32_t *map32, int m,
4591 struct nv50_program *vp, struct nv50_program *gp)
4593 uint8_t *map = (uint8_t *)map32;
4596 for (i = 0; i < gp->cfg.in_nr; ++i) {
4597 uint8_t oid, mv = 0, mg = gp->cfg.in[i].mask;
4599 for (j = 0; j < vp->cfg.out_nr; ++j) {
4600 if (vp->cfg.out[j].sn == gp->cfg.in[i].sn &&
4601 vp->cfg.out[j].si == gp->cfg.in[i].si) {
4602 mv = vp->cfg.out[j].mask;
4603 oid = vp->cfg.out[j].hw;
4608 for (c = 0; c < 4; ++c, mv >>= 1, mg >>= 1) {
4613 map[m++] = (c == 3) ? 0x41 : 0x40;
4621 nv50_gp_linkage_validate(struct nv50_context *nv50)
4623 struct nouveau_grobj *tesla = nv50->screen->tesla;
4624 struct nouveau_stateobj *so;
4625 struct nv50_program *vp = nv50->vertprog;
4626 struct nv50_program *gp = nv50->geomprog;
4631 so_ref(NULL, &nv50->state.gp_linkage);
4634 memset(map, 0, sizeof(map));
4636 m = construct_vp_gp_mapping(map, m, vp, gp);
4638 so = so_new(3, 24 - 3, 0);
4640 so_method(so, tesla, NV50TCL_VP_GP_BUILTIN_ATTR_EN, 1);
4641 so_data (so, vp->cfg.regs[0] | gp->cfg.regs[0]);
4644 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
4648 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), m);
4649 so_datap (so, map, m);
4651 so_ref(so, &nv50->state.gp_linkage);
4656 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
4658 while (p->exec_head) {
4659 struct nv50_program_exec *e = p->exec_head;
4661 p->exec_head = e->next;
4664 p->exec_tail = NULL;
4667 nouveau_bo_ref(NULL, &p->bo);
4670 nouveau_resource_free(&p->data[0]);