2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 /* #define NV50PC_DEBUG */
27 #define DESCEND_ARBITRARY(j, f) \
29 b->pass_seq = ctx->pc->pass_seq; \
31 for (j = 0; j < 2; ++j) \
32 if (b->out[j] && b->out[j]->pass_seq < ctx->pc->pass_seq) \
36 extern unsigned nv50_inst_min_size(struct nv_instruction *);
43 values_equal(struct nv_value *a, struct nv_value *b)
46 return (a->reg.file == b->reg.file && a->join->reg.id == b->join->reg.id);
50 inst_commutation_check(struct nv_instruction *a,
51 struct nv_instruction *b)
55 for (di = 0; di < 4; ++di) {
58 for (si = 0; si < 5; ++si) {
61 if (values_equal(a->def[di], b->src[si]->value))
66 if (b->flags_src && b->flags_src->value == a->flags_def)
72 /* Check whether we can swap the order of the instructions,
73 * where a & b may be either the earlier or the later one.
76 inst_commutation_legal(struct nv_instruction *a,
77 struct nv_instruction *b)
79 return inst_commutation_check(a, b) && inst_commutation_check(b, a);
83 inst_cullable(struct nv_instruction *nvi)
85 return (!(nvi->is_terminator || nvi->is_join ||
88 nv_nvi_refcount(nvi)));
92 nvi_isnop(struct nv_instruction *nvi)
94 if (nvi->opcode == NV_OP_EXPORT || nvi->opcode == NV_OP_UNDEF)
97 /* NOTE: 'fixed' now only means that it shouldn't be optimized away,
98 * but we can still remove it if it is a no-op move.
100 if (/* nvi->fixed || */
101 /* nvi->flags_src || */ /* cond. MOV to same register is still NOP */
103 nvi->is_terminator ||
107 if (nvi->def[0] && nvi->def[0]->join->reg.id < 0)
110 if (nvi->opcode != NV_OP_MOV && nvi->opcode != NV_OP_SELECT)
113 if (nvi->def[0]->reg.file != nvi->src[0]->value->reg.file)
116 if (nvi->src[0]->value->join->reg.id < 0) {
117 NV50_DBGMSG("nvi_isnop: orphaned value detected\n");
121 if (nvi->opcode == NV_OP_SELECT)
122 if (!values_equal(nvi->def[0], nvi->src[1]->value))
125 return values_equal(nvi->def[0], nvi->src[0]->value);
135 nv_pass_flatten(struct nv_pass *ctx, struct nv_basic_block *b);
138 nv_pc_pass_pre_emission(void *priv, struct nv_basic_block *b)
140 struct nv_pc *pc = (struct nv_pc *)priv;
141 struct nv_basic_block *in;
142 struct nv_instruction *nvi, *next;
146 for (j = pc->num_blocks - 1; j >= 0 && !pc->bb_list[j]->bin_size; --j);
150 /* check for no-op branches (BRA $PC+8) */
151 if (in->exit && in->exit->opcode == NV_OP_BRA && in->exit->target == b) {
155 for (++j; j < pc->num_blocks; ++j)
156 pc->bb_list[j]->bin_pos -= 8;
158 nv_nvi_delete(in->exit);
160 b->bin_pos = in->bin_pos + in->bin_size;
163 pc->bb_list[pc->num_blocks++] = b;
167 for (nvi = b->entry; nvi; nvi = next) {
173 for (nvi = b->entry; nvi; nvi = next) {
176 size = nv50_inst_min_size(nvi);
177 if (nvi->next && size < 8)
180 if ((n32 & 1) && nvi->next &&
181 nv50_inst_min_size(nvi->next) == 4 &&
182 inst_commutation_legal(nvi, nvi->next)) {
184 nv_nvi_permute(nvi, nvi->next);
189 b->bin_size += n32 & 1;
191 nvi->prev->is_long = 1;
194 b->bin_size += 1 + nvi->is_long;
198 NV50_DBGMSG("block %p is now empty\n", b);
200 if (!b->exit->is_long) {
202 b->exit->is_long = 1;
205 /* might have del'd a hole tail of instructions */
206 if (!b->exit->prev->is_long && !(n32 & 1)) {
208 b->exit->prev->is_long = 1;
211 assert(!b->entry || (b->exit && b->exit->is_long));
213 pc->bin_size += b->bin_size *= 4;
217 nv_pc_exec_pass2(struct nv_pc *pc)
224 nv_pass_flatten(&pass, pc->root);
226 NV50_DBGMSG("preparing %u blocks for emission\n", pc->num_blocks);
228 pc->bb_list = CALLOC(pc->num_blocks, sizeof(struct nv_basic_block *));
231 nv_pc_pass_in_order(pc->root, nv_pc_pass_pre_emission, pc);
236 static INLINE boolean
237 is_cmem_load(struct nv_instruction *nvi)
239 return (nvi->opcode == NV_OP_LDA &&
240 nvi->src[0]->value->reg.file >= NV_FILE_MEM_C(0) &&
241 nvi->src[0]->value->reg.file <= NV_FILE_MEM_C(15));
244 static INLINE boolean
245 is_smem_load(struct nv_instruction *nvi)
247 return (nvi->opcode == NV_OP_LDA &&
248 (nvi->src[0]->value->reg.file == NV_FILE_MEM_S ||
249 nvi->src[0]->value->reg.file <= NV_FILE_MEM_P));
252 static INLINE boolean
253 is_immd_move(struct nv_instruction *nvi)
255 return (nvi->opcode == NV_OP_MOV &&
256 nvi->src[0]->value->reg.file == NV_FILE_IMM);
260 check_swap_src_0_1(struct nv_instruction *nvi)
262 static const ubyte cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
264 struct nv_ref *src0 = nvi->src[0], *src1 = nvi->src[1];
266 if (!nv_op_commutative(nvi->opcode))
268 assert(src0 && src1);
270 if (src1->value->reg.file == NV_FILE_IMM)
273 if (is_cmem_load(src0->value->insn)) {
274 if (!is_cmem_load(src1->value->insn)) {
277 /* debug_printf("swapping cmem load to 1\n"); */
280 if (is_smem_load(src1->value->insn)) {
281 if (!is_smem_load(src0->value->insn)) {
284 /* debug_printf("swapping smem load to 0\n"); */
288 if (nvi->opcode == NV_OP_SET && nvi->src[0] != src0)
289 nvi->set_cond = cc_swapped[nvi->set_cond];
293 nv_pass_fold_stores(struct nv_pass *ctx, struct nv_basic_block *b)
295 struct nv_instruction *nvi, *sti, *next;
298 for (sti = b->entry; sti; sti = next) {
301 /* only handling MOV to $oX here */
302 if (!sti->def[0] || sti->def[0]->reg.file != NV_FILE_OUT)
304 if (sti->opcode != NV_OP_MOV && sti->opcode != NV_OP_STA)
307 nvi = sti->src[0]->value->insn;
308 if (!nvi || nvi->opcode == NV_OP_PHI || nv_is_vector_op(nvi->opcode))
310 assert(nvi->def[0] == sti->src[0]->value);
312 if (nvi->def[0]->refc > 1)
315 /* cannot write to $oX when using immediate */
316 for (j = 0; j < 4 && nvi->src[j]; ++j)
317 if (nvi->src[j]->value->reg.file == NV_FILE_IMM)
319 if (j < 4 && nvi->src[j])
322 nvi->def[0] = sti->def[0];
323 nvi->fixed = sti->fixed;
327 DESCEND_ARBITRARY(j, nv_pass_fold_stores);
333 nv_pass_fold_loads(struct nv_pass *ctx, struct nv_basic_block *b)
335 struct nv_instruction *nvi, *ld;
338 for (nvi = b->entry; nvi; nvi = nvi->next) {
339 check_swap_src_0_1(nvi);
341 for (j = 0; j < 3; ++j) {
344 ld = nvi->src[j]->value->insn;
348 if (is_immd_move(ld) && nv50_nvi_can_use_imm(nvi, j)) {
349 nv_reference(ctx->pc, &nvi->src[j], ld->src[0]->value);
353 if (ld->opcode != NV_OP_LDA)
355 if (!nv50_nvi_can_load(nvi, j, ld->src[0]->value))
358 if (j == 0 && ld->src[4]) /* can't load shared mem */
361 /* fold it ! */ /* XXX: ref->insn */
362 nv_reference(ctx->pc, &nvi->src[j], ld->src[0]->value);
364 nv_reference(ctx->pc, &nvi->src[4], ld->src[4]->value);
366 if (!nv_nvi_refcount(ld))
370 DESCEND_ARBITRARY(j, nv_pass_fold_loads);
376 nv_pass_lower_mods(struct nv_pass *ctx, struct nv_basic_block *b)
379 struct nv_instruction *nvi, *mi, *next;
382 for (nvi = b->entry; nvi; nvi = next) {
384 if (nvi->opcode == NV_OP_SUB) {
385 nvi->opcode = NV_OP_ADD;
386 nvi->src[1]->mod ^= NV_MOD_NEG;
389 /* should not put any modifiers on NEG and ABS */
390 assert(nvi->opcode != NV_MOD_NEG || !nvi->src[0]->mod);
391 assert(nvi->opcode != NV_MOD_ABS || !nvi->src[0]->mod);
393 for (j = 0; j < 4; ++j) {
397 mi = nvi->src[j]->value->insn;
400 if (mi->def[0]->refc > 1)
403 if (mi->opcode == NV_OP_NEG) mod = NV_MOD_NEG;
405 if (mi->opcode == NV_OP_ABS) mod = NV_MOD_ABS;
409 if (nvi->opcode == NV_OP_ABS)
410 mod &= ~(NV_MOD_NEG | NV_MOD_ABS);
412 if (nvi->opcode == NV_OP_NEG && mod == NV_MOD_NEG) {
413 nvi->opcode = NV_OP_MOV;
417 if (!(nv50_supported_src_mods(nvi->opcode, j) & mod))
420 nv_reference(ctx->pc, &nvi->src[j], mi->src[0]->value);
422 nvi->src[j]->mod ^= mod;
425 if (nvi->opcode == NV_OP_SAT) {
426 mi = nvi->src[0]->value->insn;
428 if ((mi->opcode == NV_OP_MAD) && !mi->flags_def) {
430 mi->def[0] = nvi->def[0];
435 DESCEND_ARBITRARY(j, nv_pass_lower_mods);
440 #define SRC_IS_MUL(s) ((s)->insn && (s)->insn->opcode == NV_OP_MUL)
443 modifiers_apply(uint32_t *val, ubyte type, ubyte mod)
445 if (mod & NV_MOD_ABS) {
446 if (type == NV_TYPE_F32)
449 if ((*val) & (1 << 31))
452 if (mod & NV_MOD_NEG) {
453 if (type == NV_TYPE_F32)
461 modifiers_opcode(ubyte mod)
464 case NV_MOD_NEG: return NV_OP_NEG;
465 case NV_MOD_ABS: return NV_OP_ABS;
474 constant_expression(struct nv_pc *pc, struct nv_instruction *nvi,
475 struct nv_value *src0, struct nv_value *src1)
477 struct nv_value *val;
487 type = nvi->def[0]->reg.type;
490 u0.u32 = src0->reg.imm.u32;
491 u1.u32 = src1->reg.imm.u32;
493 modifiers_apply(&u0.u32, type, nvi->src[0]->mod);
494 modifiers_apply(&u1.u32, type, nvi->src[1]->mod);
496 switch (nvi->opcode) {
498 if (nvi->src[2]->value->reg.file != NV_FILE_GPR)
503 case NV_TYPE_F32: u.f32 = u0.f32 * u1.f32; break;
504 case NV_TYPE_U32: u.u32 = u0.u32 * u1.u32; break;
505 case NV_TYPE_S32: u.s32 = u0.s32 * u1.s32; break;
513 case NV_TYPE_F32: u.f32 = u0.f32 + u1.f32; break;
514 case NV_TYPE_U32: u.u32 = u0.u32 + u1.u32; break;
515 case NV_TYPE_S32: u.s32 = u0.s32 + u1.s32; break;
523 case NV_TYPE_F32: u.f32 = u0.f32 - u1.f32; break;
524 case NV_TYPE_U32: u.u32 = u0.u32 - u1.u32; break;
525 case NV_TYPE_S32: u.s32 = u0.s32 - u1.s32; break;
535 nvi->opcode = NV_OP_MOV;
537 val = new_value(pc, NV_FILE_IMM, type);
539 val->reg.imm.u32 = u.u32;
541 nv_reference(pc, &nvi->src[1], NULL);
542 nv_reference(pc, &nvi->src[0], val);
544 if (nvi->src[2]) { /* from MAD */
545 nvi->src[1] = nvi->src[0];
546 nvi->src[0] = nvi->src[2];
548 nvi->opcode = NV_OP_ADD;
553 constant_operand(struct nv_pc *pc,
554 struct nv_instruction *nvi, struct nv_value *val, int s)
567 type = nvi->def[0]->reg.type;
569 u.u32 = val->reg.imm.u32;
570 modifiers_apply(&u.u32, type, nvi->src[s]->mod);
572 switch (nvi->opcode) {
574 if ((type == NV_TYPE_F32 && u.f32 == 1.0f) ||
575 (NV_TYPE_ISINT(type) && u.u32 == 1)) {
576 if ((op = modifiers_opcode(nvi->src[t]->mod)) == NV_OP_NOP)
579 nv_reference(pc, &nvi->src[s], NULL);
580 nvi->src[0] = nvi->src[t];
583 if ((type == NV_TYPE_F32 && u.f32 == 2.0f) ||
584 (NV_TYPE_ISINT(type) && u.u32 == 2)) {
585 nvi->opcode = NV_OP_ADD;
586 nv_reference(pc, &nvi->src[s], nvi->src[t]->value);
587 nvi->src[s]->mod = nvi->src[t]->mod;
589 if (type == NV_TYPE_F32 && u.f32 == -1.0f) {
590 if (nvi->src[t]->mod & NV_MOD_NEG)
591 nvi->opcode = NV_OP_MOV;
593 nvi->opcode = NV_OP_NEG;
594 nv_reference(pc, &nvi->src[s], NULL);
595 nvi->src[0] = nvi->src[t];
598 if (type == NV_TYPE_F32 && u.f32 == -2.0f) {
599 nvi->opcode = NV_OP_ADD;
600 nv_reference(pc, &nvi->src[s], nvi->src[t]->value);
601 nvi->src[s]->mod = (nvi->src[t]->mod ^= NV_MOD_NEG);
604 nvi->opcode = NV_OP_MOV;
605 nv_reference(pc, &nvi->src[t], NULL);
607 nvi->src[0] = nvi->src[1];
614 if ((op = modifiers_opcode(nvi->src[t]->mod)) == NV_OP_NOP)
617 nv_reference(pc, &nvi->src[s], NULL);
618 nvi->src[0] = nvi->src[t];
623 u.f32 = 1.0f / u.f32;
624 (val = new_value(pc, NV_FILE_IMM, NV_TYPE_F32))->reg.imm.f32 = u.f32;
625 nvi->opcode = NV_OP_MOV;
627 nv_reference(pc, &nvi->src[0], val);
630 u.f32 = 1.0f / sqrtf(u.f32);
631 (val = new_value(pc, NV_FILE_IMM, NV_TYPE_F32))->reg.imm.f32 = u.f32;
632 nvi->opcode = NV_OP_MOV;
634 nv_reference(pc, &nvi->src[0], val);
642 nv_pass_lower_arith(struct nv_pass *ctx, struct nv_basic_block *b)
644 struct nv_instruction *nvi, *next;
647 for (nvi = b->entry; nvi; nvi = next) {
648 struct nv_value *src0, *src1, *src;
653 src0 = nvcg_find_immediate(nvi->src[0]);
654 src1 = nvcg_find_immediate(nvi->src[1]);
657 constant_expression(ctx->pc, nvi, src0, src1);
660 constant_operand(ctx->pc, nvi, src0, 0);
663 constant_operand(ctx->pc, nvi, src1, 1);
666 /* try to combine MUL, ADD into MAD */
667 if (nvi->opcode != NV_OP_ADD)
670 src0 = nvi->src[0]->value;
671 src1 = nvi->src[1]->value;
673 if (SRC_IS_MUL(src0) && src0->refc == 1)
676 if (SRC_IS_MUL(src1) && src1->refc == 1)
681 nvi->opcode = NV_OP_MAD;
682 mod = nvi->src[(src == src0) ? 0 : 1]->mod;
683 nv_reference(ctx->pc, &nvi->src[(src == src0) ? 0 : 1], NULL);
684 nvi->src[2] = nvi->src[(src == src0) ? 1 : 0];
686 assert(!(mod & ~NV_MOD_NEG));
687 nvi->src[0] = new_ref(ctx->pc, src->insn->src[0]->value);
688 nvi->src[1] = new_ref(ctx->pc, src->insn->src[1]->value);
689 nvi->src[0]->mod = src->insn->src[0]->mod ^ mod;
690 nvi->src[1]->mod = src->insn->src[1]->mod;
692 DESCEND_ARBITRARY(j, nv_pass_lower_arith);
697 /* TODO: redundant store elimination */
700 struct load_record *next;
702 struct nv_value *value;
705 #define LOAD_RECORD_POOL_SIZE 1024
707 struct nv_pass_reld_elim {
710 struct load_record *imm;
711 struct load_record *mem_s;
712 struct load_record *mem_v;
713 struct load_record *mem_c[16];
714 struct load_record *mem_l;
716 struct load_record pool[LOAD_RECORD_POOL_SIZE];
721 nv_pass_reload_elim(struct nv_pass_reld_elim *ctx, struct nv_basic_block *b)
723 struct load_record **rec, *it;
724 struct nv_instruction *ld, *next;
726 struct nv_value *val;
729 for (ld = b->entry; ld; ld = next) {
733 val = ld->src[0]->value;
736 if (ld->opcode == NV_OP_LINTERP || ld->opcode == NV_OP_PINTERP) {
740 if (ld->opcode == NV_OP_LDA) {
742 if (val->reg.file >= NV_FILE_MEM_C(0) &&
743 val->reg.file <= NV_FILE_MEM_C(15))
744 rec = &ctx->mem_c[val->reg.file - NV_FILE_MEM_C(0)];
746 if (val->reg.file == NV_FILE_MEM_S)
749 if (val->reg.file == NV_FILE_MEM_L)
752 if ((ld->opcode == NV_OP_MOV) && (val->reg.file == NV_FILE_IMM)) {
753 data = val->reg.imm.u32;
757 if (!rec || !ld->def[0]->refc)
760 for (it = *rec; it; it = it->next)
761 if (it->data == data)
765 if (ld->def[0]->reg.id >= 0)
766 it->value = ld->def[0];
769 nvcg_replace_value(ctx->pc, ld->def[0], it->value);
771 if (ctx->alloc == LOAD_RECORD_POOL_SIZE)
773 it = &ctx->pool[ctx->alloc++];
776 it->value = ld->def[0];
784 for (j = 0; j < 16; ++j)
785 ctx->mem_c[j] = NULL;
789 DESCEND_ARBITRARY(j, nv_pass_reload_elim);
795 nv_pass_tex_mask(struct nv_pass *ctx, struct nv_basic_block *b)
799 for (i = 0; i < ctx->pc->num_instructions; ++i) {
800 struct nv_instruction *nvi = &ctx->pc->instructions[i];
801 struct nv_value *def[4];
803 if (!nv_is_vector_op(nvi->opcode))
807 for (c = 0; c < 4; ++c) {
808 if (nvi->def[c]->refc)
809 nvi->tex_mask |= 1 << c;
810 def[c] = nvi->def[c];
814 for (c = 0; c < 4; ++c)
815 if (nvi->tex_mask & (1 << c))
816 nvi->def[j++] = def[c];
817 for (c = 0; c < 4; ++c)
818 if (!(nvi->tex_mask & (1 << c)))
819 nvi->def[j++] = def[c];
831 nv_pass_dce(struct nv_pass_dce *ctx, struct nv_basic_block *b)
834 struct nv_instruction *nvi, *next;
836 for (nvi = b->phi ? b->phi : b->entry; nvi; nvi = next) {
839 if (inst_cullable(nvi)) {
845 DESCEND_ARBITRARY(j, nv_pass_dce);
850 /* Register allocation inserted ELSE blocks for all IF/ENDIF without ELSE.
851 * Returns TRUE if @bb initiates an IF/ELSE/ENDIF clause, or is an IF with
852 * BREAK and dummy ELSE block.
854 static INLINE boolean
855 bb_is_if_else_endif(struct nv_basic_block *bb)
857 if (!bb->out[0] || !bb->out[1])
860 if (bb->out[0]->out_kind[0] == CFG_EDGE_LOOP_LEAVE) {
861 return (bb->out[0]->out[1] == bb->out[1]->out[0] &&
862 !bb->out[1]->out[1]);
864 return (bb->out[0]->out[0] == bb->out[1]->out[0] &&
865 !bb->out[0]->out[1] &&
866 !bb->out[1]->out[1]);
870 /* predicate instructions and remove branch at the end */
872 predicate_instructions(struct nv_pc *pc, struct nv_basic_block *b,
873 struct nv_value *p, ubyte cc)
875 struct nv_instruction *nvi;
879 for (nvi = b->entry; nvi->next; nvi = nvi->next) {
880 if (!nvi_isnop(nvi)) {
882 nv_reference(pc, &nvi->flags_src, p);
886 if (nvi->opcode == NV_OP_BRA)
889 if (!nvi_isnop(nvi)) {
891 nv_reference(pc, &nvi->flags_src, p);
895 /* NOTE: Run this after register allocation, we can just cut out the cflow
896 * instructions and hook the predicates to the conditional OPs if they are
897 * not using immediates; better than inserting SELECT to join definitions.
899 * NOTE: Should adapt prior optimization to make this possible more often.
902 nv_pass_flatten(struct nv_pass *ctx, struct nv_basic_block *b)
904 struct nv_instruction *nvi;
905 struct nv_value *pred;
909 if (bb_is_if_else_endif(b)) {
911 NV50_DBGMSG("pass_flatten: IF/ELSE/ENDIF construct at BB:%i\n", b->id);
913 for (n0 = 0, nvi = b->out[0]->entry; nvi; nvi = nvi->next, ++n0)
914 if (!nv50_nvi_can_predicate(nvi))
917 for (n1 = 0, nvi = b->out[1]->entry; nvi; nvi = nvi->next, ++n1)
918 if (!nv50_nvi_can_predicate(nvi))
922 debug_printf("cannot predicate: "); nv_print_instruction(nvi);
925 debug_printf("cannot predicate: "); nv_print_instruction(nvi);
929 if (!nvi && n0 < 12 && n1 < 12) { /* 12 as arbitrary limit */
930 assert(b->exit && b->exit->flags_src);
931 pred = b->exit->flags_src->value;
933 predicate_instructions(ctx->pc, b->out[0], pred, NV_CC_NE | NV_CC_U);
934 predicate_instructions(ctx->pc, b->out[1], pred, NV_CC_EQ);
936 assert(b->exit && b->exit->opcode == NV_OP_BRA);
937 nv_nvi_delete(b->exit);
939 if (b->exit && b->exit->opcode == NV_OP_JOINAT)
940 nv_nvi_delete(b->exit);
942 i = (b->out[0]->out_kind[0] == CFG_EDGE_LOOP_LEAVE) ? 1 : 0;
944 if ((nvi = b->out[0]->out[i]->entry)) {
946 if (nvi->opcode == NV_OP_JOIN)
951 DESCEND_ARBITRARY(i, nv_pass_flatten);
956 /* local common subexpression elimination, stupid O(n^2) implementation */
958 nv_pass_cse(struct nv_pass *ctx, struct nv_basic_block *b)
960 struct nv_instruction *ir, *ik, *next;
961 struct nv_instruction *entry = b->phi ? b->phi : b->entry;
967 for (ir = entry; ir; ir = next) {
969 for (ik = entry; ik != ir; ik = ik->next) {
970 if (ir->opcode != ik->opcode || ir->fixed)
973 if (!ir->def[0] || !ik->def[0] ||
974 ik->opcode == NV_OP_LDA ||
975 ik->opcode == NV_OP_STA ||
976 ik->opcode == NV_OP_MOV ||
977 nv_is_vector_op(ik->opcode))
978 continue; /* ignore loads, stores & moves */
980 if (ik->src[4] || ir->src[4])
981 continue; /* don't mess with address registers */
983 if (ik->flags_src || ir->flags_src ||
984 ik->flags_def || ir->flags_def)
985 continue; /* and also not with flags, for now */
987 if (ik->def[0]->reg.file == NV_FILE_OUT ||
988 ir->def[0]->reg.file == NV_FILE_OUT ||
989 !values_equal(ik->def[0], ir->def[0]))
992 for (s = 0; s < 3; ++s) {
993 struct nv_value *a, *b;
1000 if (ik->src[s]->mod != ir->src[s]->mod)
1002 a = ik->src[s]->value;
1003 b = ir->src[s]->value;
1006 if (a->reg.file != b->reg.file ||
1008 a->reg.id != b->reg.id)
1014 nvcg_replace_value(ctx->pc, ir->def[0], ik->def[0]);
1021 DESCEND_ARBITRARY(s, nv_pass_cse);
1027 nv_pc_exec_pass0(struct nv_pc *pc)
1029 struct nv_pass_reld_elim *reldelim;
1030 struct nv_pass pass;
1031 struct nv_pass_dce dce;
1037 /* Do this first, so we don't have to pay attention
1038 * to whether sources are supported memory loads.
1041 ret = nv_pass_lower_arith(&pass, pc->root);
1046 ret = nv_pass_fold_loads(&pass, pc->root);
1051 ret = nv_pass_fold_stores(&pass, pc->root);
1055 reldelim = CALLOC_STRUCT(nv_pass_reld_elim);
1058 ret = nv_pass_reload_elim(reldelim, pc->root);
1064 ret = nv_pass_cse(&pass, pc->root);
1069 ret = nv_pass_lower_mods(&pass, pc->root);
1077 ret = nv_pass_dce(&dce, pc->root);
1080 } while (dce.removed);
1082 ret = nv_pass_tex_mask(&pass, pc->root);