2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 /* #define NV50PC_DEBUG */
27 #define DESCEND_ARBITRARY(j, f) \
29 b->pass_seq = ctx->pc->pass_seq; \
31 for (j = 0; j < 2; ++j) \
32 if (b->out[j] && b->out[j]->pass_seq < ctx->pc->pass_seq) \
36 extern unsigned nv50_inst_min_size(struct nv_instruction *);
43 values_equal(struct nv_value *a, struct nv_value *b)
46 return (a->reg.file == b->reg.file && a->join->reg.id == b->join->reg.id);
50 inst_commutation_check(struct nv_instruction *a,
51 struct nv_instruction *b)
55 for (di = 0; di < 4; ++di) {
58 for (si = 0; si < 5; ++si) {
61 if (values_equal(a->def[di], b->src[si]->value))
66 if (b->flags_src && b->flags_src->value == a->flags_def)
72 /* Check whether we can swap the order of the instructions,
73 * where a & b may be either the earlier or the later one.
76 inst_commutation_legal(struct nv_instruction *a,
77 struct nv_instruction *b)
79 return inst_commutation_check(a, b) && inst_commutation_check(b, a);
83 inst_cullable(struct nv_instruction *nvi)
85 if (nvi->opcode == NV_OP_STA)
87 return (!(nvi->is_terminator || nvi->is_join ||
90 nv_nvi_refcount(nvi)));
94 nvi_isnop(struct nv_instruction *nvi)
96 if (nvi->opcode == NV_OP_EXPORT || nvi->opcode == NV_OP_UNDEF)
99 /* NOTE: 'fixed' now only means that it shouldn't be optimized away,
100 * but we can still remove it if it is a no-op move.
102 if (/* nvi->fixed || */
103 /* nvi->flags_src || */ /* cond. MOV to same register is still NOP */
105 nvi->is_terminator ||
109 if (nvi->def[0] && nvi->def[0]->join->reg.id < 0)
112 if (nvi->opcode != NV_OP_MOV && nvi->opcode != NV_OP_SELECT)
115 if (nvi->def[0]->reg.file != nvi->src[0]->value->reg.file)
118 if (nvi->src[0]->value->join->reg.id < 0) {
119 NV50_DBGMSG("nvi_isnop: orphaned value detected\n");
123 if (nvi->opcode == NV_OP_SELECT)
124 if (!values_equal(nvi->def[0], nvi->src[1]->value))
127 return values_equal(nvi->def[0], nvi->src[0]->value);
137 nv_pass_flatten(struct nv_pass *ctx, struct nv_basic_block *b);
140 nv_pc_pass_pre_emission(void *priv, struct nv_basic_block *b)
142 struct nv_pc *pc = (struct nv_pc *)priv;
143 struct nv_basic_block *in;
144 struct nv_instruction *nvi, *next;
148 for (j = pc->num_blocks - 1; j >= 0 && !pc->bb_list[j]->bin_size; --j);
152 /* check for no-op branches (BRA $PC+8) */
153 if (in->exit && in->exit->opcode == NV_OP_BRA && in->exit->target == b) {
157 for (++j; j < pc->num_blocks; ++j)
158 pc->bb_list[j]->bin_pos -= 8;
160 nv_nvi_delete(in->exit);
162 b->bin_pos = in->bin_pos + in->bin_size;
165 pc->bb_list[pc->num_blocks++] = b;
169 for (nvi = b->entry; nvi; nvi = next) {
175 for (nvi = b->entry; nvi; nvi = next) {
178 size = nv50_inst_min_size(nvi);
179 if (nvi->next && size < 8)
182 if ((n32 & 1) && nvi->next &&
183 nv50_inst_min_size(nvi->next) == 4 &&
184 inst_commutation_legal(nvi, nvi->next)) {
186 nv_nvi_permute(nvi, nvi->next);
191 b->bin_size += n32 & 1;
193 nvi->prev->is_long = 1;
196 b->bin_size += 1 + nvi->is_long;
200 NV50_DBGMSG("block %p is now empty\n", b);
202 if (!b->exit->is_long) {
204 b->exit->is_long = 1;
207 /* might have del'd a hole tail of instructions */
208 if (!b->exit->prev->is_long && !(n32 & 1)) {
210 b->exit->prev->is_long = 1;
213 assert(!b->entry || (b->exit && b->exit->is_long));
215 pc->bin_size += b->bin_size *= 4;
219 nv_pc_pass2(struct nv_pc *pc, struct nv_basic_block *root)
227 nv_pass_flatten(&pass, root);
229 nv_pc_pass_in_order(root, nv_pc_pass_pre_emission, pc);
235 nv_pc_exec_pass2(struct nv_pc *pc)
239 NV50_DBGMSG("preparing %u blocks for emission\n", pc->num_blocks);
241 pc->num_blocks = 0; /* will reorder bb_list */
243 for (i = 0; i < pc->num_subroutines + 1; ++i)
244 if (pc->root[i] && (ret = nv_pc_pass2(pc, pc->root[i])))
249 static INLINE boolean
250 is_cmem_load(struct nv_instruction *nvi)
252 return (nvi->opcode == NV_OP_LDA &&
253 nvi->src[0]->value->reg.file >= NV_FILE_MEM_C(0) &&
254 nvi->src[0]->value->reg.file <= NV_FILE_MEM_C(15));
257 static INLINE boolean
258 is_smem_load(struct nv_instruction *nvi)
260 return (nvi->opcode == NV_OP_LDA &&
261 (nvi->src[0]->value->reg.file == NV_FILE_MEM_S ||
262 nvi->src[0]->value->reg.file <= NV_FILE_MEM_P));
265 static INLINE boolean
266 is_immd_move(struct nv_instruction *nvi)
268 return (nvi->opcode == NV_OP_MOV &&
269 nvi->src[0]->value->reg.file == NV_FILE_IMM);
273 check_swap_src_0_1(struct nv_instruction *nvi)
275 static const ubyte cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
277 struct nv_ref *src0 = nvi->src[0], *src1 = nvi->src[1];
279 if (!nv_op_commutative(nvi->opcode))
281 assert(src0 && src1);
283 if (src1->value->reg.file == NV_FILE_IMM)
286 if (is_cmem_load(src0->value->insn)) {
287 if (!is_cmem_load(src1->value->insn)) {
290 /* debug_printf("swapping cmem load to 1\n"); */
293 if (is_smem_load(src1->value->insn)) {
294 if (!is_smem_load(src0->value->insn)) {
297 /* debug_printf("swapping smem load to 0\n"); */
301 if (nvi->opcode == NV_OP_SET && nvi->src[0] != src0)
302 nvi->set_cond = cc_swapped[nvi->set_cond];
306 nv_pass_fold_stores(struct nv_pass *ctx, struct nv_basic_block *b)
308 struct nv_instruction *nvi, *sti, *next;
311 for (sti = b->entry; sti; sti = next) {
314 /* only handling MOV to $oX here */
315 if (!sti->def[0] || sti->def[0]->reg.file != NV_FILE_OUT)
317 if (sti->opcode != NV_OP_MOV && sti->opcode != NV_OP_STA)
320 nvi = sti->src[0]->value->insn;
321 if (!nvi || nvi->opcode == NV_OP_PHI || nv_is_vector_op(nvi->opcode))
323 assert(nvi->def[0] == sti->src[0]->value);
325 if (nvi->opcode == NV_OP_SELECT)
327 if (nvi->def[0]->refc > 1)
330 /* cannot write to $oX when using immediate */
331 for (j = 0; j < 4 && nvi->src[j]; ++j)
332 if (nvi->src[j]->value->reg.file == NV_FILE_IMM ||
333 nvi->src[j]->value->reg.file == NV_FILE_MEM_L)
335 if (j < 4 && nvi->src[j])
338 nvi->def[0] = sti->def[0];
339 nvi->fixed = sti->fixed;
343 DESCEND_ARBITRARY(j, nv_pass_fold_stores);
349 nv_pass_fold_loads(struct nv_pass *ctx, struct nv_basic_block *b)
351 struct nv_instruction *nvi, *ld;
354 for (nvi = b->entry; nvi; nvi = nvi->next) {
355 check_swap_src_0_1(nvi);
357 for (j = 0; j < 3; ++j) {
360 ld = nvi->src[j]->value->insn;
364 if (is_immd_move(ld) && nv50_nvi_can_use_imm(nvi, j)) {
365 nv_reference(ctx->pc, &nvi->src[j], ld->src[0]->value);
369 if (ld->opcode != NV_OP_LDA)
371 if (!nv50_nvi_can_load(nvi, j, ld->src[0]->value))
374 if (j == 0 && ld->src[4]) /* can't load shared mem */
377 /* fold it ! */ /* XXX: ref->insn */
378 nv_reference(ctx->pc, &nvi->src[j], ld->src[0]->value);
380 nv_reference(ctx->pc, &nvi->src[4], ld->src[4]->value);
382 if (!nv_nvi_refcount(ld))
386 DESCEND_ARBITRARY(j, nv_pass_fold_loads);
392 nv_pass_lower_mods(struct nv_pass *ctx, struct nv_basic_block *b)
395 struct nv_instruction *nvi, *mi, *next;
398 for (nvi = b->entry; nvi; nvi = next) {
400 if (nvi->opcode == NV_OP_SUB) {
401 nvi->opcode = NV_OP_ADD;
402 nvi->src[1]->mod ^= NV_MOD_NEG;
405 /* should not put any modifiers on NEG and ABS */
406 assert(nvi->opcode != NV_MOD_NEG || !nvi->src[0]->mod);
407 assert(nvi->opcode != NV_MOD_ABS || !nvi->src[0]->mod);
409 for (j = 0; j < 4; ++j) {
413 mi = nvi->src[j]->value->insn;
416 if (mi->def[0]->refc > 1)
419 if (mi->opcode == NV_OP_NEG) mod = NV_MOD_NEG;
421 if (mi->opcode == NV_OP_ABS) mod = NV_MOD_ABS;
425 if (nvi->opcode == NV_OP_ABS)
426 mod &= ~(NV_MOD_NEG | NV_MOD_ABS);
428 if (nvi->opcode == NV_OP_NEG && mod == NV_MOD_NEG) {
429 nvi->opcode = NV_OP_MOV;
433 if (!(nv50_supported_src_mods(nvi->opcode, j) & mod))
436 nv_reference(ctx->pc, &nvi->src[j], mi->src[0]->value);
438 nvi->src[j]->mod ^= mod;
441 if (nvi->opcode == NV_OP_SAT) {
442 mi = nvi->src[0]->value->insn;
444 if ((mi->opcode == NV_OP_MAD) && !mi->flags_def) {
446 mi->def[0] = nvi->def[0];
451 DESCEND_ARBITRARY(j, nv_pass_lower_mods);
456 #define SRC_IS_MUL(s) ((s)->insn && (s)->insn->opcode == NV_OP_MUL)
459 modifiers_apply(uint32_t *val, ubyte type, ubyte mod)
461 if (mod & NV_MOD_ABS) {
462 if (type == NV_TYPE_F32)
465 if ((*val) & (1 << 31))
468 if (mod & NV_MOD_NEG) {
469 if (type == NV_TYPE_F32)
477 modifiers_opcode(ubyte mod)
480 case NV_MOD_NEG: return NV_OP_NEG;
481 case NV_MOD_ABS: return NV_OP_ABS;
490 constant_expression(struct nv_pc *pc, struct nv_instruction *nvi,
491 struct nv_value *src0, struct nv_value *src1)
493 struct nv_value *val;
503 type = nvi->def[0]->reg.type;
506 u0.u32 = src0->reg.imm.u32;
507 u1.u32 = src1->reg.imm.u32;
509 modifiers_apply(&u0.u32, type, nvi->src[0]->mod);
510 modifiers_apply(&u1.u32, type, nvi->src[1]->mod);
512 switch (nvi->opcode) {
514 if (nvi->src[2]->value->reg.file != NV_FILE_GPR)
519 case NV_TYPE_F32: u.f32 = u0.f32 * u1.f32; break;
520 case NV_TYPE_U32: u.u32 = u0.u32 * u1.u32; break;
521 case NV_TYPE_S32: u.s32 = u0.s32 * u1.s32; break;
529 case NV_TYPE_F32: u.f32 = u0.f32 + u1.f32; break;
530 case NV_TYPE_U32: u.u32 = u0.u32 + u1.u32; break;
531 case NV_TYPE_S32: u.s32 = u0.s32 + u1.s32; break;
539 case NV_TYPE_F32: u.f32 = u0.f32 - u1.f32; break;
540 case NV_TYPE_U32: u.u32 = u0.u32 - u1.u32; break;
541 case NV_TYPE_S32: u.s32 = u0.s32 - u1.s32; break;
551 nvi->opcode = NV_OP_MOV;
553 val = new_value(pc, NV_FILE_IMM, type);
555 val->reg.imm.u32 = u.u32;
557 nv_reference(pc, &nvi->src[1], NULL);
558 nv_reference(pc, &nvi->src[0], val);
560 if (nvi->src[2]) { /* from MAD */
561 nvi->src[1] = nvi->src[0];
562 nvi->src[0] = nvi->src[2];
564 nvi->opcode = NV_OP_ADD;
566 if (val->reg.imm.u32 == 0) {
568 nvi->opcode = NV_OP_MOV;
574 constant_operand(struct nv_pc *pc,
575 struct nv_instruction *nvi, struct nv_value *val, int s)
588 type = nvi->def[0]->reg.type;
590 u.u32 = val->reg.imm.u32;
591 modifiers_apply(&u.u32, type, nvi->src[s]->mod);
593 switch (nvi->opcode) {
595 if ((type == NV_TYPE_F32 && u.f32 == 1.0f) ||
596 (NV_TYPE_ISINT(type) && u.u32 == 1)) {
597 if ((op = modifiers_opcode(nvi->src[t]->mod)) == NV_OP_NOP)
600 nv_reference(pc, &nvi->src[s], NULL);
601 nvi->src[0] = nvi->src[t];
604 if ((type == NV_TYPE_F32 && u.f32 == 2.0f) ||
605 (NV_TYPE_ISINT(type) && u.u32 == 2)) {
606 nvi->opcode = NV_OP_ADD;
607 nv_reference(pc, &nvi->src[s], nvi->src[t]->value);
608 nvi->src[s]->mod = nvi->src[t]->mod;
610 if (type == NV_TYPE_F32 && u.f32 == -1.0f) {
611 if (nvi->src[t]->mod & NV_MOD_NEG)
612 nvi->opcode = NV_OP_MOV;
614 nvi->opcode = NV_OP_NEG;
615 nv_reference(pc, &nvi->src[s], NULL);
616 nvi->src[0] = nvi->src[t];
619 if (type == NV_TYPE_F32 && u.f32 == -2.0f) {
620 nvi->opcode = NV_OP_ADD;
621 nv_reference(pc, &nvi->src[s], nvi->src[t]->value);
622 nvi->src[s]->mod = (nvi->src[t]->mod ^= NV_MOD_NEG);
625 nvi->opcode = NV_OP_MOV;
626 nv_reference(pc, &nvi->src[t], NULL);
628 nvi->src[0] = nvi->src[1];
635 if ((op = modifiers_opcode(nvi->src[t]->mod)) == NV_OP_NOP)
638 nv_reference(pc, &nvi->src[s], NULL);
639 nvi->src[0] = nvi->src[t];
644 u.f32 = 1.0f / u.f32;
645 (val = new_value(pc, NV_FILE_IMM, NV_TYPE_F32))->reg.imm.f32 = u.f32;
646 nvi->opcode = NV_OP_MOV;
648 nv_reference(pc, &nvi->src[0], val);
651 u.f32 = 1.0f / sqrtf(u.f32);
652 (val = new_value(pc, NV_FILE_IMM, NV_TYPE_F32))->reg.imm.f32 = u.f32;
653 nvi->opcode = NV_OP_MOV;
655 nv_reference(pc, &nvi->src[0], val);
661 if (nvi->opcode == NV_OP_MOV && nvi->flags_def) {
662 struct nv_instruction *cvt = new_instruction_at(pc, nvi, NV_OP_CVT);
664 nv_reference(pc, &cvt->src[0], nvi->def[0]);
666 cvt->flags_def = nvi->flags_def;
667 nvi->flags_def = NULL;
672 nv_pass_lower_arith(struct nv_pass *ctx, struct nv_basic_block *b)
674 struct nv_instruction *nvi, *next;
677 for (nvi = b->entry; nvi; nvi = next) {
678 struct nv_value *src0, *src1, *src;
683 src0 = nvcg_find_immediate(nvi->src[0]);
684 src1 = nvcg_find_immediate(nvi->src[1]);
687 constant_expression(ctx->pc, nvi, src0, src1);
690 constant_operand(ctx->pc, nvi, src0, 0);
693 constant_operand(ctx->pc, nvi, src1, 1);
696 /* try to combine MUL, ADD into MAD */
697 if (nvi->opcode != NV_OP_ADD)
700 src0 = nvi->src[0]->value;
701 src1 = nvi->src[1]->value;
703 if (SRC_IS_MUL(src0) && src0->refc == 1)
706 if (SRC_IS_MUL(src1) && src1->refc == 1)
711 /* could have an immediate from above constant_* */
712 if (src0->reg.file != NV_FILE_GPR || src1->reg.file != NV_FILE_GPR)
715 nvi->opcode = NV_OP_MAD;
716 mod = nvi->src[(src == src0) ? 0 : 1]->mod;
717 nv_reference(ctx->pc, &nvi->src[(src == src0) ? 0 : 1], NULL);
718 nvi->src[2] = nvi->src[(src == src0) ? 1 : 0];
720 assert(!(mod & ~NV_MOD_NEG));
721 nvi->src[0] = new_ref(ctx->pc, src->insn->src[0]->value);
722 nvi->src[1] = new_ref(ctx->pc, src->insn->src[1]->value);
723 nvi->src[0]->mod = src->insn->src[0]->mod ^ mod;
724 nvi->src[1]->mod = src->insn->src[1]->mod;
726 DESCEND_ARBITRARY(j, nv_pass_lower_arith);
731 /* TODO: redundant store elimination */
734 struct load_record *next;
736 struct nv_value *value;
739 #define LOAD_RECORD_POOL_SIZE 1024
741 struct nv_pass_reld_elim {
744 struct load_record *imm;
745 struct load_record *mem_s;
746 struct load_record *mem_v;
747 struct load_record *mem_c[16];
748 struct load_record *mem_l;
750 struct load_record pool[LOAD_RECORD_POOL_SIZE];
754 /* TODO: properly handle loads from l[] memory in the presence of stores */
756 nv_pass_reload_elim(struct nv_pass_reld_elim *ctx, struct nv_basic_block *b)
758 struct load_record **rec, *it;
759 struct nv_instruction *ld, *next;
761 struct nv_value *val;
764 for (ld = b->entry; ld; ld = next) {
768 val = ld->src[0]->value;
771 if (ld->opcode == NV_OP_LINTERP || ld->opcode == NV_OP_PINTERP) {
772 data[0] = val->reg.id;
776 if (ld->opcode == NV_OP_LDA) {
777 data[0] = val->reg.id;
778 data[1] = ld->src[4] ? ld->src[4]->value->n : ~0ULL;
779 if (val->reg.file >= NV_FILE_MEM_C(0) &&
780 val->reg.file <= NV_FILE_MEM_C(15))
781 rec = &ctx->mem_c[val->reg.file - NV_FILE_MEM_C(0)];
783 if (val->reg.file == NV_FILE_MEM_S)
786 if (val->reg.file == NV_FILE_MEM_L)
789 if ((ld->opcode == NV_OP_MOV) && (val->reg.file == NV_FILE_IMM)) {
790 data[0] = val->reg.imm.u32;
795 if (!rec || !ld->def[0]->refc)
798 for (it = *rec; it; it = it->next)
799 if (it->data[0] == data[0] && it->data[1] == data[1])
803 if (ld->def[0]->reg.id >= 0)
804 it->value = ld->def[0];
807 nvcg_replace_value(ctx->pc, ld->def[0], it->value);
809 if (ctx->alloc == LOAD_RECORD_POOL_SIZE)
811 it = &ctx->pool[ctx->alloc++];
813 it->data[0] = data[0];
814 it->data[1] = data[1];
815 it->value = ld->def[0];
823 for (j = 0; j < 16; ++j)
824 ctx->mem_c[j] = NULL;
828 DESCEND_ARBITRARY(j, nv_pass_reload_elim);
834 nv_pass_tex_mask(struct nv_pass *ctx, struct nv_basic_block *b)
838 for (i = 0; i < ctx->pc->num_instructions; ++i) {
839 struct nv_instruction *nvi = &ctx->pc->instructions[i];
840 struct nv_value *def[4];
842 if (!nv_is_vector_op(nvi->opcode))
846 for (c = 0; c < 4; ++c) {
847 if (nvi->def[c]->refc)
848 nvi->tex_mask |= 1 << c;
849 def[c] = nvi->def[c];
853 for (c = 0; c < 4; ++c)
854 if (nvi->tex_mask & (1 << c))
855 nvi->def[j++] = def[c];
856 for (c = 0; c < 4; ++c)
857 if (!(nvi->tex_mask & (1 << c)))
858 nvi->def[j++] = def[c];
870 nv_pass_dce(struct nv_pass_dce *ctx, struct nv_basic_block *b)
873 struct nv_instruction *nvi, *next;
875 for (nvi = b->phi ? b->phi : b->entry; nvi; nvi = next) {
878 if (inst_cullable(nvi)) {
884 DESCEND_ARBITRARY(j, nv_pass_dce);
889 /* Register allocation inserted ELSE blocks for all IF/ENDIF without ELSE.
890 * Returns TRUE if @bb initiates an IF/ELSE/ENDIF clause, or is an IF with
891 * BREAK and dummy ELSE block.
893 static INLINE boolean
894 bb_is_if_else_endif(struct nv_basic_block *bb)
896 if (!bb->out[0] || !bb->out[1])
899 if (bb->out[0]->out_kind[0] == CFG_EDGE_LOOP_LEAVE) {
900 return (bb->out[0]->out[1] == bb->out[1]->out[0] &&
901 !bb->out[1]->out[1]);
903 return (bb->out[0]->out[0] == bb->out[1]->out[0] &&
904 !bb->out[0]->out[1] &&
905 !bb->out[1]->out[1]);
909 /* predicate instructions and remove branch at the end */
911 predicate_instructions(struct nv_pc *pc, struct nv_basic_block *b,
912 struct nv_value *p, ubyte cc)
914 struct nv_instruction *nvi;
918 for (nvi = b->entry; nvi->next; nvi = nvi->next) {
919 if (!nvi_isnop(nvi)) {
921 nv_reference(pc, &nvi->flags_src, p);
925 if (nvi->opcode == NV_OP_BRA)
928 if (!nvi_isnop(nvi)) {
930 nv_reference(pc, &nvi->flags_src, p);
934 /* NOTE: Run this after register allocation, we can just cut out the cflow
935 * instructions and hook the predicates to the conditional OPs if they are
936 * not using immediates; better than inserting SELECT to join definitions.
938 * NOTE: Should adapt prior optimization to make this possible more often.
941 nv_pass_flatten(struct nv_pass *ctx, struct nv_basic_block *b)
943 struct nv_instruction *nvi;
944 struct nv_value *pred;
948 if (bb_is_if_else_endif(b)) {
950 NV50_DBGMSG("pass_flatten: IF/ELSE/ENDIF construct at BB:%i\n", b->id);
952 for (n0 = 0, nvi = b->out[0]->entry; nvi; nvi = nvi->next, ++n0)
953 if (!nv50_nvi_can_predicate(nvi))
956 for (n1 = 0, nvi = b->out[1]->entry; nvi; nvi = nvi->next, ++n1)
957 if (!nv50_nvi_can_predicate(nvi))
961 debug_printf("cannot predicate: "); nv_print_instruction(nvi);
964 debug_printf("cannot predicate: "); nv_print_instruction(nvi);
968 if (!nvi && n0 < 12 && n1 < 12) { /* 12 as arbitrary limit */
969 assert(b->exit && b->exit->flags_src);
970 pred = b->exit->flags_src->value;
972 predicate_instructions(ctx->pc, b->out[0], pred, NV_CC_NE | NV_CC_U);
973 predicate_instructions(ctx->pc, b->out[1], pred, NV_CC_EQ);
975 assert(b->exit && b->exit->opcode == NV_OP_BRA);
976 nv_nvi_delete(b->exit);
978 if (b->exit && b->exit->opcode == NV_OP_JOINAT)
979 nv_nvi_delete(b->exit);
981 i = (b->out[0]->out_kind[0] == CFG_EDGE_LOOP_LEAVE) ? 1 : 0;
983 if ((nvi = b->out[0]->out[i]->entry)) {
985 if (nvi->opcode == NV_OP_JOIN)
990 DESCEND_ARBITRARY(i, nv_pass_flatten);
995 /* local common subexpression elimination, stupid O(n^2) implementation */
997 nv_pass_cse(struct nv_pass *ctx, struct nv_basic_block *b)
999 struct nv_instruction *ir, *ik, *next;
1000 struct nv_instruction *entry = b->phi ? b->phi : b->entry;
1006 for (ir = entry; ir; ir = next) {
1008 for (ik = entry; ik != ir; ik = ik->next) {
1009 if (ir->opcode != ik->opcode || ir->fixed)
1012 if (!ir->def[0] || !ik->def[0] ||
1013 ik->opcode == NV_OP_LDA ||
1014 ik->opcode == NV_OP_STA ||
1015 ik->opcode == NV_OP_MOV ||
1016 nv_is_vector_op(ik->opcode))
1017 continue; /* ignore loads, stores & moves */
1019 if (ik->src[4] || ir->src[4])
1020 continue; /* don't mess with address registers */
1022 if (ik->flags_src || ir->flags_src ||
1023 ik->flags_def || ir->flags_def)
1024 continue; /* and also not with flags, for now */
1026 if (ik->def[0]->reg.file == NV_FILE_OUT ||
1027 ir->def[0]->reg.file == NV_FILE_OUT ||
1028 !values_equal(ik->def[0], ir->def[0]))
1031 for (s = 0; s < 3; ++s) {
1032 struct nv_value *a, *b;
1039 if (ik->src[s]->mod != ir->src[s]->mod)
1041 a = ik->src[s]->value;
1042 b = ir->src[s]->value;
1045 if (a->reg.file != b->reg.file ||
1047 a->reg.id != b->reg.id)
1053 nvcg_replace_value(ctx->pc, ir->def[0], ik->def[0]);
1060 DESCEND_ARBITRARY(s, nv_pass_cse);
1066 nv_pc_pass0(struct nv_pc *pc, struct nv_basic_block *root)
1068 struct nv_pass_reld_elim *reldelim;
1069 struct nv_pass pass;
1070 struct nv_pass_dce dce;
1076 /* Do this first, so we don't have to pay attention
1077 * to whether sources are supported memory loads.
1080 ret = nv_pass_lower_arith(&pass, root);
1085 ret = nv_pass_fold_loads(&pass, root);
1090 ret = nv_pass_fold_stores(&pass, root);
1094 if (pc->opt_reload_elim) {
1095 reldelim = CALLOC_STRUCT(nv_pass_reld_elim);
1098 ret = nv_pass_reload_elim(reldelim, root);
1105 ret = nv_pass_cse(&pass, root);
1110 ret = nv_pass_lower_mods(&pass, root);
1118 ret = nv_pass_dce(&dce, root);
1121 } while (dce.removed);
1123 ret = nv_pass_tex_mask(&pass, root);
1131 nv_pc_exec_pass0(struct nv_pc *pc)
1135 for (i = 0; i < pc->num_subroutines + 1; ++i)
1136 if (pc->root[i] && (ret = nv_pc_pass0(pc, pc->root[i])))