1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "pipe/p_inlines.h"
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/tgsi_parse.h"
8 #include "tgsi/tgsi_dump.h"
10 #include "nv20_context.h"
11 #include "nv20_state.h"
13 /* TODO (at least...):
14 * 1. Indexed consts + ARL
15 * 2. Arb. swz/negation
16 * 3. NV_vp11, NV_vp2, NV_vp3 features
17 * - extra arith opcodes
33 #define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
36 #include "nv20_shader.h"
38 #define swz(s,x,y,z,w) nv20_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
39 #define neg(s) nv20_sr_neg((s))
40 #define abs(s) nv20_sr_abs((s))
43 struct nv20_vertex_program *vp;
45 struct nv20_vertex_program_exec *vpi;
47 unsigned output_map[PIPE_MAX_SHADER_OUTPUTS];
52 struct nv20_sreg *imm;
56 static struct nv20_sreg
57 temp(struct nv20_vpc *vpc)
61 idx = vpc->temp_temp_count++;
62 idx += vpc->high_temp + 1;
63 return nv20_sr(NV30SR_TEMP, idx);
66 static struct nv20_sreg
67 constant(struct nv20_vpc *vpc, int pipe, float x, float y, float z, float w)
69 struct nv20_vertex_program *vp = vpc->vp;
70 struct nv20_vertex_program_data *vpd;
74 for (idx = 0; idx < vp->nr_consts; idx++) {
75 if (vp->consts[idx].index == pipe)
76 return nv20_sr(NV30SR_CONST, idx);
80 idx = vp->nr_consts++;
81 vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
82 vpd = &vp->consts[idx];
89 return nv20_sr(NV30SR_CONST, idx);
92 #define arith(cc,s,o,d,m,s0,s1,s2) \
93 nv20_vp_arith((cc), (s), NV30_VP_INST_##o, (d), (m), (s0), (s1), (s2))
96 emit_src(struct nv20_vpc *vpc, uint32_t *hw, int pos, struct nv20_sreg src)
98 struct nv20_vertex_program *vp = vpc->vp;
103 sr |= (NV30_VP_SRC_REG_TYPE_TEMP << NV30_VP_SRC_REG_TYPE_SHIFT);
104 sr |= (src.index << NV30_VP_SRC_TEMP_SRC_SHIFT);
107 sr |= (NV30_VP_SRC_REG_TYPE_INPUT <<
108 NV30_VP_SRC_REG_TYPE_SHIFT);
109 vp->ir |= (1 << src.index);
110 hw[1] |= (src.index << NV30_VP_INST_INPUT_SRC_SHIFT);
113 sr |= (NV30_VP_SRC_REG_TYPE_CONST <<
114 NV30_VP_SRC_REG_TYPE_SHIFT);
115 assert(vpc->vpi->const_index == -1 ||
116 vpc->vpi->const_index == src.index);
117 vpc->vpi->const_index = src.index;
120 sr |= (NV30_VP_SRC_REG_TYPE_INPUT <<
121 NV30_VP_SRC_REG_TYPE_SHIFT);
128 sr |= NV30_VP_SRC_NEGATE;
131 hw[0] |= (1 << (21 + pos));
133 sr |= ((src.swz[0] << NV30_VP_SRC_SWZ_X_SHIFT) |
134 (src.swz[1] << NV30_VP_SRC_SWZ_Y_SHIFT) |
135 (src.swz[2] << NV30_VP_SRC_SWZ_Z_SHIFT) |
136 (src.swz[3] << NV30_VP_SRC_SWZ_W_SHIFT));
147 hw[1] |= ((sr & NV30_VP_SRC0_HIGH_MASK) >>
148 NV30_VP_SRC0_HIGH_SHIFT) << NV30_VP_INST_SRC0H_SHIFT;
149 hw[2] |= (sr & NV30_VP_SRC0_LOW_MASK) <<
150 NV30_VP_INST_SRC0L_SHIFT;
153 hw[2] |= sr << NV30_VP_INST_SRC1_SHIFT;
156 hw[2] |= ((sr & NV30_VP_SRC2_HIGH_MASK) >>
157 NV30_VP_SRC2_HIGH_SHIFT) << NV30_VP_INST_SRC2H_SHIFT;
158 hw[3] |= (sr & NV30_VP_SRC2_LOW_MASK) <<
159 NV30_VP_INST_SRC2L_SHIFT;
167 emit_dst(struct nv20_vpc *vpc, uint32_t *hw, int slot, struct nv20_sreg dst)
169 struct nv20_vertex_program *vp = vpc->vp;
173 hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
177 case NV30_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
178 case NV30_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
179 case NV30_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
180 case NV30_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
181 case NV30_VP_INST_DEST_FOGC : vp->or |= (1 << 4); break;
182 case NV30_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
183 case NV30_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
184 case NV30_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
185 case NV30_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
186 case NV30_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
187 case NV30_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
188 case NV30_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
189 case NV30_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
190 case NV30_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
195 hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
196 hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
198 /*XXX: no way this is entirely correct, someone needs to
199 * figure out what exactly it is.
209 nv20_vp_arith(struct nv20_vpc *vpc, int slot, int op,
210 struct nv20_sreg dst, int mask,
211 struct nv20_sreg s0, struct nv20_sreg s1,
214 struct nv20_vertex_program *vp = vpc->vp;
217 vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
218 vpc->vpi = &vp->insns[vp->nr_insns - 1];
219 memset(vpc->vpi, 0, sizeof(*vpc->vpi));
220 vpc->vpi->const_index = -1;
224 hw[0] |= (NV30_VP_INST_COND_TR << NV30_VP_INST_COND_SHIFT);
225 hw[0] |= ((0 << NV30_VP_INST_COND_SWZ_X_SHIFT) |
226 (1 << NV30_VP_INST_COND_SWZ_Y_SHIFT) |
227 (2 << NV30_VP_INST_COND_SWZ_Z_SHIFT) |
228 (3 << NV30_VP_INST_COND_SWZ_W_SHIFT));
230 hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
231 // hw[3] |= NV30_VP_INST_SCA_DEST_TEMP_MASK;
232 // hw[3] |= (mask << NV30_VP_INST_VEC_WRITEMASK_SHIFT);
234 if (dst.type == NV30SR_OUTPUT) {
236 hw[3] |= (mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
238 hw[3] |= (mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
241 hw[3] |= (mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
243 hw[3] |= (mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
246 emit_dst(vpc, hw, slot, dst);
247 emit_src(vpc, hw, 0, s0);
248 emit_src(vpc, hw, 1, s1);
249 emit_src(vpc, hw, 2, s2);
252 static INLINE struct nv20_sreg
253 tgsi_src(struct nv20_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
254 struct nv20_sreg src;
256 switch (fsrc->SrcRegister.File) {
257 case TGSI_FILE_INPUT:
258 src = nv20_sr(NV30SR_INPUT, fsrc->SrcRegister.Index);
260 case TGSI_FILE_CONSTANT:
261 src = constant(vpc, fsrc->SrcRegister.Index, 0, 0, 0, 0);
263 case TGSI_FILE_IMMEDIATE:
264 src = vpc->imm[fsrc->SrcRegister.Index];
266 case TGSI_FILE_TEMPORARY:
267 if (vpc->high_temp < fsrc->SrcRegister.Index)
268 vpc->high_temp = fsrc->SrcRegister.Index;
269 src = nv20_sr(NV30SR_TEMP, fsrc->SrcRegister.Index);
272 NOUVEAU_ERR("bad src file\n");
276 src.abs = fsrc->SrcRegisterExtMod.Absolute;
277 src.negate = fsrc->SrcRegister.Negate;
278 src.swz[0] = fsrc->SrcRegister.SwizzleX;
279 src.swz[1] = fsrc->SrcRegister.SwizzleY;
280 src.swz[2] = fsrc->SrcRegister.SwizzleZ;
281 src.swz[3] = fsrc->SrcRegister.SwizzleW;
285 static INLINE struct nv20_sreg
286 tgsi_dst(struct nv20_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
287 struct nv20_sreg dst;
289 switch (fdst->DstRegister.File) {
290 case TGSI_FILE_OUTPUT:
291 dst = nv20_sr(NV30SR_OUTPUT,
292 vpc->output_map[fdst->DstRegister.Index]);
295 case TGSI_FILE_TEMPORARY:
296 dst = nv20_sr(NV30SR_TEMP, fdst->DstRegister.Index);
297 if (vpc->high_temp < dst.index)
298 vpc->high_temp = dst.index;
301 NOUVEAU_ERR("bad dst file\n");
313 if (tgsi & TGSI_WRITEMASK_X) mask |= MASK_X;
314 if (tgsi & TGSI_WRITEMASK_Y) mask |= MASK_Y;
315 if (tgsi & TGSI_WRITEMASK_Z) mask |= MASK_Z;
316 if (tgsi & TGSI_WRITEMASK_W) mask |= MASK_W;
321 nv20_vertprog_parse_instruction(struct nv20_vpc *vpc,
322 const struct tgsi_full_instruction *finst)
324 struct nv20_sreg src[3], dst, tmp;
325 struct nv20_sreg none = nv20_sr(NV30SR_NONE, 0);
327 int ai = -1, ci = -1;
330 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
333 vpc->temp_temp_count = 0;
334 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
335 const struct tgsi_full_src_register *fsrc;
337 fsrc = &finst->FullSrcRegisters[i];
338 if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
339 src[i] = tgsi_src(vpc, fsrc);
343 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
344 const struct tgsi_full_src_register *fsrc;
346 fsrc = &finst->FullSrcRegisters[i];
347 switch (fsrc->SrcRegister.File) {
348 case TGSI_FILE_INPUT:
349 if (ai == -1 || ai == fsrc->SrcRegister.Index) {
350 ai = fsrc->SrcRegister.Index;
351 src[i] = tgsi_src(vpc, fsrc);
354 arith(vpc, 0, OP_MOV, src[i], MASK_ALL,
355 tgsi_src(vpc, fsrc), none, none);
358 /*XXX: index comparison is broken now that consts come from
359 * two different register files.
361 case TGSI_FILE_CONSTANT:
362 case TGSI_FILE_IMMEDIATE:
363 if (ci == -1 || ci == fsrc->SrcRegister.Index) {
364 ci = fsrc->SrcRegister.Index;
365 src[i] = tgsi_src(vpc, fsrc);
368 arith(vpc, 0, OP_MOV, src[i], MASK_ALL,
369 tgsi_src(vpc, fsrc), none, none);
372 case TGSI_FILE_TEMPORARY:
376 NOUVEAU_ERR("bad src file\n");
381 dst = tgsi_dst(vpc, &finst->FullDstRegisters[0]);
382 mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
384 switch (finst->Instruction.Opcode) {
385 case TGSI_OPCODE_ABS:
386 arith(vpc, 0, OP_MOV, dst, mask, abs(src[0]), none, none);
388 case TGSI_OPCODE_ADD:
389 arith(vpc, 0, OP_ADD, dst, mask, src[0], none, src[1]);
391 case TGSI_OPCODE_ARL:
392 arith(vpc, 0, OP_ARL, dst, mask, src[0], none, none);
394 case TGSI_OPCODE_DP3:
395 arith(vpc, 0, OP_DP3, dst, mask, src[0], src[1], none);
397 case TGSI_OPCODE_DP4:
398 arith(vpc, 0, OP_DP4, dst, mask, src[0], src[1], none);
400 case TGSI_OPCODE_DPH:
401 arith(vpc, 0, OP_DPH, dst, mask, src[0], src[1], none);
403 case TGSI_OPCODE_DST:
404 arith(vpc, 0, OP_DST, dst, mask, src[0], src[1], none);
406 case TGSI_OPCODE_EX2:
407 arith(vpc, 1, OP_EX2, dst, mask, none, none, src[0]);
409 case TGSI_OPCODE_EXP:
410 arith(vpc, 1, OP_EXP, dst, mask, none, none, src[0]);
412 case TGSI_OPCODE_FLR:
413 arith(vpc, 0, OP_FLR, dst, mask, src[0], none, none);
415 case TGSI_OPCODE_FRC:
416 arith(vpc, 0, OP_FRC, dst, mask, src[0], none, none);
418 case TGSI_OPCODE_LG2:
419 arith(vpc, 1, OP_LG2, dst, mask, none, none, src[0]);
421 case TGSI_OPCODE_LIT:
422 arith(vpc, 1, OP_LIT, dst, mask, none, none, src[0]);
424 case TGSI_OPCODE_LOG:
425 arith(vpc, 1, OP_LOG, dst, mask, none, none, src[0]);
427 case TGSI_OPCODE_MAD:
428 arith(vpc, 0, OP_MAD, dst, mask, src[0], src[1], src[2]);
430 case TGSI_OPCODE_MAX:
431 arith(vpc, 0, OP_MAX, dst, mask, src[0], src[1], none);
433 case TGSI_OPCODE_MIN:
434 arith(vpc, 0, OP_MIN, dst, mask, src[0], src[1], none);
436 case TGSI_OPCODE_MOV:
437 arith(vpc, 0, OP_MOV, dst, mask, src[0], none, none);
439 case TGSI_OPCODE_MUL:
440 arith(vpc, 0, OP_MUL, dst, mask, src[0], src[1], none);
442 case TGSI_OPCODE_POW:
444 arith(vpc, 1, OP_LG2, tmp, MASK_X, none, none,
445 swz(src[0], X, X, X, X));
446 arith(vpc, 0, OP_MUL, tmp, MASK_X, swz(tmp, X, X, X, X),
447 swz(src[1], X, X, X, X), none);
448 arith(vpc, 1, OP_EX2, dst, mask, none, none,
449 swz(tmp, X, X, X, X));
451 case TGSI_OPCODE_RCP:
452 arith(vpc, 1, OP_RCP, dst, mask, none, none, src[0]);
454 case TGSI_OPCODE_RET:
456 case TGSI_OPCODE_RSQ:
457 arith(vpc, 1, OP_RSQ, dst, mask, none, none, src[0]);
459 case TGSI_OPCODE_SGE:
460 arith(vpc, 0, OP_SGE, dst, mask, src[0], src[1], none);
462 case TGSI_OPCODE_SGT:
463 arith(vpc, 0, OP_SGT, dst, mask, src[0], src[1], none);
465 case TGSI_OPCODE_SLT:
466 arith(vpc, 0, OP_SLT, dst, mask, src[0], src[1], none);
468 case TGSI_OPCODE_SUB:
469 arith(vpc, 0, OP_ADD, dst, mask, src[0], none, neg(src[1]));
471 case TGSI_OPCODE_XPD:
473 arith(vpc, 0, OP_MUL, tmp, mask,
474 swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
475 arith(vpc, 0, OP_MAD, dst, (mask & ~MASK_W),
476 swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
480 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
488 nv20_vertprog_parse_decl_output(struct nv20_vpc *vpc,
489 const struct tgsi_full_declaration *fdec)
493 switch (fdec->Semantic.SemanticName) {
494 case TGSI_SEMANTIC_POSITION:
495 hw = NV30_VP_INST_DEST_POS;
497 case TGSI_SEMANTIC_COLOR:
498 if (fdec->Semantic.SemanticIndex == 0) {
499 hw = NV30_VP_INST_DEST_COL0;
501 if (fdec->Semantic.SemanticIndex == 1) {
502 hw = NV30_VP_INST_DEST_COL1;
504 NOUVEAU_ERR("bad colour semantic index\n");
508 case TGSI_SEMANTIC_BCOLOR:
509 if (fdec->Semantic.SemanticIndex == 0) {
510 hw = NV30_VP_INST_DEST_BFC0;
512 if (fdec->Semantic.SemanticIndex == 1) {
513 hw = NV30_VP_INST_DEST_BFC1;
515 NOUVEAU_ERR("bad bcolour semantic index\n");
519 case TGSI_SEMANTIC_FOG:
520 hw = NV30_VP_INST_DEST_FOGC;
522 case TGSI_SEMANTIC_PSIZE:
523 hw = NV30_VP_INST_DEST_PSZ;
525 case TGSI_SEMANTIC_GENERIC:
526 if (fdec->Semantic.SemanticIndex <= 7) {
527 hw = NV30_VP_INST_DEST_TC(fdec->Semantic.SemanticIndex);
529 NOUVEAU_ERR("bad generic semantic index\n");
534 NOUVEAU_ERR("bad output semantic\n");
538 vpc->output_map[fdec->DeclarationRange.First] = hw;
543 nv20_vertprog_prepare(struct nv20_vpc *vpc)
545 struct tgsi_parse_context p;
548 tgsi_parse_init(&p, vpc->vp->pipe.tokens);
549 while (!tgsi_parse_end_of_tokens(&p)) {
550 const union tgsi_full_token *tok = &p.FullToken;
552 tgsi_parse_token(&p);
553 switch(tok->Token.Type) {
554 case TGSI_TOKEN_TYPE_IMMEDIATE:
564 vpc->imm = CALLOC(nr_imm, sizeof(struct nv20_sreg));
572 nv20_vertprog_translate(struct nv20_context *nv20,
573 struct nv20_vertex_program *vp)
575 struct tgsi_parse_context parse;
576 struct nv20_vpc *vpc = NULL;
578 tgsi_dump(vp->pipe.tokens,0);
580 vpc = CALLOC(1, sizeof(struct nv20_vpc));
586 if (!nv20_vertprog_prepare(vpc)) {
591 tgsi_parse_init(&parse, vp->pipe.tokens);
593 while (!tgsi_parse_end_of_tokens(&parse)) {
594 tgsi_parse_token(&parse);
596 switch (parse.FullToken.Token.Type) {
597 case TGSI_TOKEN_TYPE_DECLARATION:
599 const struct tgsi_full_declaration *fdec;
600 fdec = &parse.FullToken.FullDeclaration;
601 switch (fdec->Declaration.File) {
602 case TGSI_FILE_OUTPUT:
603 if (!nv20_vertprog_parse_decl_output(vpc, fdec))
611 case TGSI_TOKEN_TYPE_IMMEDIATE:
613 const struct tgsi_full_immediate *imm;
615 imm = &parse.FullToken.FullImmediate;
616 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
617 assert(imm->Immediate.NrTokens == 4 + 1);
618 vpc->imm[vpc->nr_imm++] =
626 case TGSI_TOKEN_TYPE_INSTRUCTION:
628 const struct tgsi_full_instruction *finst;
629 finst = &parse.FullToken.FullInstruction;
630 if (!nv20_vertprog_parse_instruction(vpc, finst))
639 vp->insns[vp->nr_insns - 1].data[3] |= NV30_VP_INST_LAST;
640 vp->translated = TRUE;
642 tgsi_parse_free(&parse);
647 nv20_vertprog_validate(struct nv20_context *nv20)
649 struct pipe_screen *pscreen = nv20->pipe.screen;
650 struct nouveau_winsys *nvws = nv20->nvws;
651 struct nouveau_grobj *rankine = nv20->screen->rankine;
652 struct nv20_vertex_program *vp;
653 struct pipe_buffer *constbuf;
654 boolean upload_code = FALSE, upload_data = FALSE;
658 constbuf = nv20->constbuf[PIPE_SHADER_VERTEX];
660 /* Translate TGSI shader into hw bytecode */
661 if (!vp->translated) {
662 nv20_vertprog_translate(nv20, vp);
667 /* Allocate hw vtxprog exec slots */
669 struct nouveau_resource *heap = nv20->screen->vp_exec_heap;
670 struct nouveau_stateobj *so;
671 uint vplen = vp->nr_insns;
673 if (nvws->res_alloc(heap, vplen, vp, &vp->exec)) {
674 while (heap->next && heap->size < vplen) {
675 struct nv20_vertex_program *evict;
677 evict = heap->next->priv;
678 nvws->res_free(&evict->exec);
681 if (nvws->res_alloc(heap, vplen, vp, &vp->exec))
686 so_method(so, rankine, NV34TCL_VP_START_FROM_ID, 1);
687 so_data (so, vp->exec->start);
693 /* Allocate hw vtxprog const slots */
694 if (vp->nr_consts && !vp->data) {
695 struct nouveau_resource *heap = nv20->screen->vp_data_heap;
697 if (nvws->res_alloc(heap, vp->nr_consts, vp, &vp->data)) {
698 while (heap->next && heap->size < vp->nr_consts) {
699 struct nv20_vertex_program *evict;
701 evict = heap->next->priv;
702 nvws->res_free(&evict->data);
705 if (nvws->res_alloc(heap, vp->nr_consts, vp, &vp->data))
709 /*XXX: handle this some day */
710 assert(vp->data->start >= vp->data_start_min);
713 if (vp->data_start != vp->data->start)
717 /* If exec or data segments moved we need to patch the program to
718 * fixup offsets and register IDs.
720 if (vp->exec_start != vp->exec->start) {
721 for (i = 0; i < vp->nr_insns; i++) {
722 struct nv20_vertex_program_exec *vpi = &vp->insns[i];
724 if (vpi->has_branch_offset) {
729 vp->exec_start = vp->exec->start;
732 if (vp->nr_consts && vp->data_start != vp->data->start) {
733 for (i = 0; i < vp->nr_insns; i++) {
734 struct nv20_vertex_program_exec *vpi = &vp->insns[i];
736 if (vpi->const_index >= 0) {
737 vpi->data[1] &= ~NV30_VP_INST_CONST_SRC_MASK;
739 (vpi->const_index + vp->data->start) <<
740 NV30_VP_INST_CONST_SRC_SHIFT;
745 vp->data_start = vp->data->start;
748 /* Update + Upload constant values */
753 map = pipe_buffer_map(pscreen, constbuf,
754 PIPE_BUFFER_USAGE_CPU_READ);
757 for (i = 0; i < vp->nr_consts; i++) {
758 struct nv20_vertex_program_data *vpd = &vp->consts[i];
760 if (vpd->index >= 0) {
762 !memcmp(vpd->value, &map[vpd->index * 4],
765 memcpy(vpd->value, &map[vpd->index * 4],
769 BEGIN_RING(rankine, NV34TCL_VP_UPLOAD_CONST_ID, 5);
770 OUT_RING (i + vp->data->start);
771 OUT_RINGp ((uint32_t *)vpd->value, 4);
775 pipe_buffer_unmap(pscreen, constbuf);
781 for (i = 0; i < vp->nr_insns; i++) {
782 NOUVEAU_MSG("VP inst %d: 0x%08x 0x%08x 0x%08x 0x%08x\n",
783 i, vp->insns[i].data[0], vp->insns[i].data[1],
784 vp->insns[i].data[2], vp->insns[i].data[3]);
787 BEGIN_RING(rankine, NV34TCL_VP_UPLOAD_FROM_ID, 1);
788 OUT_RING (vp->exec->start);
789 for (i = 0; i < vp->nr_insns; i++) {
790 BEGIN_RING(rankine, NV34TCL_VP_UPLOAD_INST(0), 4);
791 OUT_RINGp (vp->insns[i].data, 4);
795 if (vp->so != nv20->state.hw[NV30_STATE_VERTPROG]) {
796 so_ref(vp->so, &nv20->state.hw[NV30_STATE_VERTPROG]);
804 nv20_vertprog_destroy(struct nv20_context *nv20, struct nv20_vertex_program *vp)
806 struct nouveau_winsys *nvws = nv20->screen->nvws;
808 vp->translated = FALSE;
822 nvws->res_free(&vp->exec);
824 nvws->res_free(&vp->data);
826 vp->data_start_min = 0;
829 so_ref(NULL, &vp->so);
832 struct nv20_state_entry nv20_state_vertprog = {
833 .validate = nv20_vertprog_validate,
835 .pipe = NV30_NEW_VERTPROG /*| NV30_NEW_UCP*/,
836 .hw = NV30_STATE_VERTPROG,