1 /**************************************************************************
3 * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "util/u_inlines.h"
30 #include "util/u_memory.h"
31 #include "util/u_string.h"
34 #include "brw_context.h"
35 #include "brw_screen.h"
36 #include "brw_winsys.h"
37 #include "brw_debug.h"
40 static const struct debug_named_value debug_names[] = {
41 { "tex", DEBUG_TEXTURE},
42 { "state", DEBUG_STATE},
43 { "ioctl", DEBUG_IOCTL},
44 { "blit", DEBUG_BLIT},
45 { "curbe", DEBUG_CURBE},
46 { "fall", DEBUG_FALLBACKS},
47 { "verb", DEBUG_VERBOSE},
48 { "bat", DEBUG_BATCH},
49 { "pix", DEBUG_PIXEL},
50 { "wins", DEBUG_WINSYS},
51 { "min", DEBUG_MIN_URB},
52 { "dis", DEBUG_DISASSEM},
53 { "sync", DEBUG_SYNC},
54 { "prim", DEBUG_PRIMS },
55 { "vert", DEBUG_VERTS },
57 { "san", DEBUG_SANITY },
58 { "sleep", DEBUG_SLEEP },
59 { "stats", DEBUG_STATS },
60 { "sing", DEBUG_SINGLE_THREAD },
61 { "thre", DEBUG_SINGLE_THREAD },
68 static const struct debug_named_value dump_names[] = {
70 { "state", DUMP_STATE},
71 { "batch", DUMP_BATCH},
87 brw_get_vendor(struct pipe_screen *screen)
89 return "VMware, Inc.";
93 brw_get_name(struct pipe_screen *screen)
95 static char buffer[128];
98 switch (brw_screen(screen)->chipset.pci_id) {
102 case PCI_CHIP_I965_Q:
105 case PCI_CHIP_I965_G_1:
106 chipset = "I965_G_1";
108 case PCI_CHIP_I946_GZ:
111 case PCI_CHIP_I965_GM:
114 case PCI_CHIP_I965_GME:
115 chipset = "I965_GME";
117 case PCI_CHIP_GM45_GM:
120 case PCI_CHIP_IGD_E_G:
146 util_snprintf(buffer, sizeof(buffer), "i965 (chipset: %s)", chipset);
151 brw_get_param(struct pipe_screen *screen, int param)
154 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
156 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
158 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
159 return 16; /* XXX correct? */
160 case PIPE_CAP_NPOT_TEXTURES:
162 case PIPE_CAP_TWO_SIDED_STENCIL:
166 case PIPE_CAP_ANISOTROPIC_FILTER:
168 case PIPE_CAP_POINT_SPRITE:
170 case PIPE_CAP_MAX_RENDER_TARGETS:
172 case PIPE_CAP_OCCLUSION_QUERY:
174 case PIPE_CAP_TEXTURE_SHADOW_MAP:
176 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
177 return BRW_MAX_TEXTURE_2D_LEVELS;
178 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
179 return BRW_MAX_TEXTURE_3D_LEVELS;
180 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
181 return BRW_MAX_TEXTURE_2D_LEVELS;
182 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
183 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
185 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
186 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
194 brw_get_paramf(struct pipe_screen *screen, int param)
197 case PIPE_CAP_MAX_LINE_WIDTH:
199 case PIPE_CAP_MAX_LINE_WIDTH_AA:
202 case PIPE_CAP_MAX_POINT_WIDTH:
204 case PIPE_CAP_MAX_POINT_WIDTH_AA:
207 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
210 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
219 brw_is_format_supported(struct pipe_screen *screen,
220 enum pipe_format format,
221 enum pipe_texture_target target,
225 static const enum pipe_format tex_supported[] = {
226 PIPE_FORMAT_L8_UNORM,
227 PIPE_FORMAT_I8_UNORM,
228 PIPE_FORMAT_A8_UNORM,
229 PIPE_FORMAT_L16_UNORM,
230 /*PIPE_FORMAT_I16_UNORM,*/
231 /*PIPE_FORMAT_A16_UNORM,*/
232 PIPE_FORMAT_L8A8_UNORM,
233 PIPE_FORMAT_B5G6R5_UNORM,
234 PIPE_FORMAT_B5G5R5A1_UNORM,
235 PIPE_FORMAT_B4G4R4A4_UNORM,
236 PIPE_FORMAT_B8G8R8X8_UNORM,
237 PIPE_FORMAT_B8G8R8A8_UNORM,
242 /*PIPE_FORMAT_FXT1_RGBA,*/
243 PIPE_FORMAT_DXT1_RGB,
244 PIPE_FORMAT_DXT1_RGBA,
245 PIPE_FORMAT_DXT3_RGBA,
246 PIPE_FORMAT_DXT5_RGBA,
248 PIPE_FORMAT_A8B8G8R8_SRGB,
249 PIPE_FORMAT_L8A8_SRGB,
251 PIPE_FORMAT_DXT1_SRGB,
253 PIPE_FORMAT_Z32_FLOAT,
254 PIPE_FORMAT_Z24X8_UNORM,
255 PIPE_FORMAT_Z24_UNORM_S8_USCALED,
256 PIPE_FORMAT_Z16_UNORM,
258 PIPE_FORMAT_R8G8_SNORM,
259 PIPE_FORMAT_R8G8B8A8_SNORM,
260 PIPE_FORMAT_NONE /* list terminator */
262 static const enum pipe_format render_supported[] = {
263 PIPE_FORMAT_B8G8R8X8_UNORM,
264 PIPE_FORMAT_B8G8R8A8_UNORM,
265 PIPE_FORMAT_B5G6R5_UNORM,
266 PIPE_FORMAT_NONE /* list terminator */
268 static const enum pipe_format depth_supported[] = {
269 PIPE_FORMAT_Z32_FLOAT,
270 PIPE_FORMAT_Z24X8_UNORM,
271 PIPE_FORMAT_Z24_UNORM_S8_USCALED,
272 PIPE_FORMAT_Z16_UNORM,
273 PIPE_FORMAT_NONE /* list terminator */
275 const enum pipe_format *list;
278 if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL)
279 list = depth_supported;
280 else if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET)
281 list = render_supported;
283 list = tex_supported;
285 for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
286 if (list[i] == format)
300 brw_fence_reference(struct pipe_screen *screen,
301 struct pipe_fence_handle **ptr,
302 struct pipe_fence_handle *fence)
307 brw_fence_signalled(struct pipe_screen *screen,
308 struct pipe_fence_handle *fence,
311 return 0; /* XXX shouldn't this be a boolean? */
315 brw_fence_finish(struct pipe_screen *screen,
316 struct pipe_fence_handle *fence,
329 brw_destroy_screen(struct pipe_screen *screen)
331 struct brw_screen *bscreen = brw_screen(screen);
334 bscreen->sws->destroy(bscreen->sws);
340 * Create a new brw_screen object
343 brw_create_screen(struct brw_winsys_screen *sws, uint pci_id)
345 struct brw_screen *bscreen;
346 struct brw_chipset chipset;
349 BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0);
350 BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0);
351 BRW_DEBUG |= DEBUG_STATS | DEBUG_MIN_URB | DEBUG_WM;
353 BRW_DUMP = debug_get_flags_option("BRW_DUMP", dump_names, 0);
356 memset(&chipset, 0, sizeof chipset);
358 chipset.pci_id = pci_id;
361 case PCI_CHIP_I965_G:
362 case PCI_CHIP_I965_Q:
363 case PCI_CHIP_I965_G_1:
364 case PCI_CHIP_I946_GZ:
365 case PCI_CHIP_I965_GM:
366 case PCI_CHIP_I965_GME:
367 chipset.is_965 = TRUE;
370 case PCI_CHIP_GM45_GM:
371 case PCI_CHIP_IGD_E_G:
376 chipset.is_g4x = TRUE;
381 chipset.is_igdng = TRUE;
385 debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
386 __FUNCTION__, pci_id);
391 bscreen = CALLOC_STRUCT(brw_screen);
395 bscreen->chipset = chipset;
397 bscreen->base.winsys = NULL;
398 bscreen->base.destroy = brw_destroy_screen;
399 bscreen->base.get_name = brw_get_name;
400 bscreen->base.get_vendor = brw_get_vendor;
401 bscreen->base.get_param = brw_get_param;
402 bscreen->base.get_paramf = brw_get_paramf;
403 bscreen->base.is_format_supported = brw_is_format_supported;
404 bscreen->base.context_create = brw_create_context;
405 bscreen->base.fence_reference = brw_fence_reference;
406 bscreen->base.fence_signalled = brw_fence_signalled;
407 bscreen->base.fence_finish = brw_fence_finish;
409 brw_screen_tex_init(bscreen);
410 brw_screen_tex_surface_init(bscreen);
411 brw_screen_buffer_init(bscreen);
413 bscreen->no_tiling = debug_get_option("BRW_NO_TILING", FALSE) != NULL;
416 return &bscreen->base;