src/gallium/drivers/i965/brw_screen.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "util/u_format.h"
  30 #include "util/u_inlines.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_string.h"
  33
  34 #include "brw_reg.h"
  35 #include "brw_context.h"
  36 #include "brw_screen.h"
  37 #include "brw_winsys.h"
  38 #include "brw_public.h"
  39 #include "brw_debug.h"
  40 #include "brw_resource.h"
  41
  42 #ifdef DEBUG
  43 static const struct debug_named_value debug_names[] = {
  44    { "tex",   DEBUG_TEXTURE, NULL },
  45    { "state", DEBUG_STATE, NULL },
  46    { "ioctl", DEBUG_IOCTL, NULL },
  47    { "blit",  DEBUG_BLIT, NULL },
  48    { "curbe", DEBUG_CURBE, NULL },
  49    { "fall",  DEBUG_FALLBACKS, NULL },
  50    { "verb",  DEBUG_VERBOSE, NULL },
  51    { "bat",   DEBUG_BATCH, NULL },
  52    { "pix",   DEBUG_PIXEL, NULL },
  53    { "wins",  DEBUG_WINSYS, NULL },
  54    { "min",   DEBUG_MIN_URB, NULL },
  55    { "dis",   DEBUG_DISASSEM, NULL },
  56    { "sync",  DEBUG_SYNC, NULL },
  57    { "prim",  DEBUG_PRIMS, NULL },
  58    { "vert",  DEBUG_VERTS, NULL },
  59    { "dma",   DEBUG_DMA, NULL },
  60    { "san",   DEBUG_SANITY, NULL },
  61    { "sleep", DEBUG_SLEEP, NULL },
  62    { "stats", DEBUG_STATS, NULL },
  63    { "sing",  DEBUG_SINGLE_THREAD, NULL },
  64    { "thre",  DEBUG_SINGLE_THREAD, NULL },
  65    { "wm",    DEBUG_WM, NULL },
  66    { "urb",   DEBUG_URB, NULL },
  67    { "vs",    DEBUG_VS, NULL },
  68    DEBUG_NAMED_VALUE_END
  69 };
  70
  71 static const struct debug_named_value dump_names[] = {
  72    { "asm",   DUMP_ASM, NULL },
  73    { "state", DUMP_STATE, NULL },
  74    { "batch", DUMP_BATCH, NULL },
  75    DEBUG_NAMED_VALUE_END
  76 };
  77
  78 int BRW_DEBUG = 0;
  79 int BRW_DUMP = 0;
  80
  81 #endif
  82
  83
  84 /*
  85  * Probe functions
  86  */
  87
  88
  89 static const char *
  90 brw_get_vendor(struct pipe_screen *screen)
  91 {
  92    return "VMware, Inc.";
  93 }
  94
  95 static const char *
  96 brw_get_name(struct pipe_screen *screen)
  97 {
  98    static char buffer[128];
  99    const char *chipset;
 100
 101    switch (brw_screen(screen)->pci_id) {
 102    case PCI_CHIP_I965_G:
 103       chipset = "I965_G";
 104       break;
 105    case PCI_CHIP_I965_Q:
 106       chipset = "I965_Q";
 107       break;
 108    case PCI_CHIP_I965_G_1:
 109       chipset = "I965_G_1";
 110       break;
 111    case PCI_CHIP_I946_GZ:
 112       chipset = "I946_GZ";
 113       break;
 114    case PCI_CHIP_I965_GM:
 115       chipset = "I965_GM";
 116       break;
 117    case PCI_CHIP_I965_GME:
 118       chipset = "I965_GME";
 119       break;
 120    case PCI_CHIP_GM45_GM:
 121       chipset = "GM45_GM";
 122       break;
 123    case PCI_CHIP_IGD_E_G:
 124       chipset = "IGD_E_G";
 125       break;
 126    case PCI_CHIP_Q45_G:
 127       chipset = "Q45_G";
 128       break;
 129    case PCI_CHIP_G45_G:
 130       chipset = "G45_G";
 131       break;
 132    case PCI_CHIP_G41_G:
 133       chipset = "G41_G";
 134       break;
 135    case PCI_CHIP_B43_G:
 136       chipset = "B43_G";
 137       break;
 138    case PCI_CHIP_ILD_G:
 139       chipset = "ILD_G";
 140       break;
 141    case PCI_CHIP_ILM_G:
 142       chipset = "ILM_G";
 143       break;
 144    default:
 145       chipset = "unknown";
 146       break;
 147    }
 148
 149    util_snprintf(buffer, sizeof(buffer), "i965 (chipset: %s)", chipset);
 150    return buffer;
 151 }
 152
 153 static int
 154 brw_get_param(struct pipe_screen *screen, enum pipe_cap param)
 155 {
 156    switch (param) {
 157    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 158       return 8;
 159    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
 160       return 8;
 161    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 162       return 16; /* XXX correct? */
 163    case PIPE_CAP_NPOT_TEXTURES:
 164       return 1;
 165    case PIPE_CAP_TWO_SIDED_STENCIL:
 166       return 1;
 167    case PIPE_CAP_GLSL:
 168       return 0;
 169    case PIPE_CAP_ANISOTROPIC_FILTER:
 170       return 0;
 171    case PIPE_CAP_POINT_SPRITE:
 172       return 0;
 173    case PIPE_CAP_MAX_RENDER_TARGETS:
 174       return 1;
 175    case PIPE_CAP_OCCLUSION_QUERY:
 176       return 0;
 177    case PIPE_CAP_TIMER_QUERY:
 178       return 0;
 179    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 180       return 1;
 181    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 182       return BRW_MAX_TEXTURE_2D_LEVELS;
 183    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 184       return BRW_MAX_TEXTURE_3D_LEVELS;
 185    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 186       return BRW_MAX_TEXTURE_2D_LEVELS;
 187    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 188    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 189       return 1;
 190    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 191    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 192       return 0;
 193    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 194       /* disable for now */
 195       return 0;
 196    default:
 197       return 0;
 198    }
 199 }
 200
 201 static int
 202 brw_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap param)
 203 {
 204    switch(shader) {
 205    case PIPE_SHADER_VERTEX:
 206    case PIPE_SHADER_FRAGMENT:
 207    case PIPE_SHADER_GEOMETRY:
 208       break;
 209    default:
 210       return 0;
 211    }
 212
 213    /* XXX: these are just shader model 4.0 values, fix this! */
 214    switch(param) {
 215       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 216          return 65536;
 217       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 218          return 65536;
 219       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 220          return 65536;
 221       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 222          return 65536;
 223       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 224          return 65536;
 225       case PIPE_SHADER_CAP_MAX_INPUTS:
 226          return 32;
 227       case PIPE_SHADER_CAP_MAX_CONSTS:
 228          return 4096;
 229       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 230          return PIPE_MAX_CONSTANT_BUFFERS;
 231       case PIPE_SHADER_CAP_MAX_TEMPS:
 232          return 4096;
 233       case PIPE_SHADER_CAP_MAX_ADDRS:
 234          return 0;
 235       case PIPE_SHADER_CAP_MAX_PREDS:
 236          return 0;
 237       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 238          return 1;
 239       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 240       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 241       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 242       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 243           return 1;
 244       case PIPE_SHADER_CAP_SUBROUTINES:
 245           return 1;
 246       default:
 247          assert(0);
 248          return 0;
 249       }
 250 }
 251
 252 static float
 253 brw_get_paramf(struct pipe_screen *screen, enum pipe_cap param)
 254 {
 255    switch (param) {
 256    case PIPE_CAP_MAX_LINE_WIDTH:
 257       /* fall-through */
 258    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 259       return 7.5;
 260
 261    case PIPE_CAP_MAX_POINT_WIDTH:
 262       /* fall-through */
 263    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 264       return 255.0;
 265
 266    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 267       return 4.0;
 268
 269    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 270       return 16.0;
 271
 272    default:
 273       return 0;
 274    }
 275 }
 276
 277 static boolean
 278 brw_is_format_supported(struct pipe_screen *screen,
 279                          enum pipe_format format,
 280                          enum pipe_texture_target target,
 281                          unsigned sample_count,
 282                          unsigned tex_usage)
 283 {
 284    static const enum pipe_format tex_supported[] = {
 285       PIPE_FORMAT_L8_UNORM,
 286       PIPE_FORMAT_I8_UNORM,
 287       PIPE_FORMAT_A8_UNORM,
 288       PIPE_FORMAT_L16_UNORM,
 289       /*PIPE_FORMAT_I16_UNORM,*/
 290       /*PIPE_FORMAT_A16_UNORM,*/
 291       PIPE_FORMAT_L8A8_UNORM,
 292       PIPE_FORMAT_B5G6R5_UNORM,
 293       PIPE_FORMAT_B5G5R5A1_UNORM,
 294       PIPE_FORMAT_B4G4R4A4_UNORM,
 295       PIPE_FORMAT_B8G8R8X8_UNORM,
 296       PIPE_FORMAT_B8G8R8A8_UNORM,
 297       /* video */
 298       PIPE_FORMAT_UYVY,
 299       PIPE_FORMAT_YUYV,
 300       /* compressed */
 301       /*PIPE_FORMAT_FXT1_RGBA,*/
 302       PIPE_FORMAT_DXT1_RGB,
 303       PIPE_FORMAT_DXT1_RGBA,
 304       PIPE_FORMAT_DXT3_RGBA,
 305       PIPE_FORMAT_DXT5_RGBA,
 306       /* sRGB */
 307       PIPE_FORMAT_A8B8G8R8_SRGB,
 308       PIPE_FORMAT_L8A8_SRGB,
 309       PIPE_FORMAT_L8_SRGB,
 310       PIPE_FORMAT_DXT1_SRGB,
 311       /* depth */
 312       PIPE_FORMAT_Z32_FLOAT,
 313       PIPE_FORMAT_Z24X8_UNORM,
 314       PIPE_FORMAT_Z24_UNORM_S8_USCALED,
 315       PIPE_FORMAT_Z16_UNORM,
 316       /* signed */
 317       PIPE_FORMAT_R8G8_SNORM,
 318       PIPE_FORMAT_R8G8B8A8_SNORM,
 319       PIPE_FORMAT_NONE  /* list terminator */
 320    };
 321    static const enum pipe_format render_supported[] = {
 322       PIPE_FORMAT_B8G8R8X8_UNORM,
 323       PIPE_FORMAT_B8G8R8A8_UNORM,
 324       PIPE_FORMAT_B5G6R5_UNORM,
 325       PIPE_FORMAT_NONE  /* list terminator */
 326    };
 327    static const enum pipe_format depth_supported[] = {
 328       PIPE_FORMAT_Z32_FLOAT,
 329       PIPE_FORMAT_Z24X8_UNORM,
 330       PIPE_FORMAT_Z24_UNORM_S8_USCALED,
 331       PIPE_FORMAT_Z16_UNORM,
 332       PIPE_FORMAT_NONE  /* list terminator */
 333    };
 334    const enum pipe_format *list;
 335    uint i;
 336
 337    if (!util_format_is_supported(format, tex_usage))
 338       return FALSE;
 339
 340    if (sample_count > 1)
 341       return FALSE;
 342
 343    if (tex_usage & PIPE_BIND_DEPTH_STENCIL)
 344       list = depth_supported;
 345    else if (tex_usage & PIPE_BIND_RENDER_TARGET)
 346       list = render_supported;
 347    else
 348       list = tex_supported;
 349
 350    for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
 351       if (list[i] == format)
 352          return TRUE;
 353    }
 354
 355    return FALSE;
 356 }
 357
 358
 359 /*
 360  * Fence functions
 361  */
 362
 363
 364 static void
 365 brw_fence_reference(struct pipe_screen *screen,
 366                      struct pipe_fence_handle **ptr,
 367                      struct pipe_fence_handle *fence)
 368 {
 369 }
 370
 371 static boolean
 372 brw_fence_signalled(struct pipe_screen *screen,
 373                      struct pipe_fence_handle *fence)
 374 {
 375    return TRUE;
 376 }
 377
 378 static boolean
 379 brw_fence_finish(struct pipe_screen *screen,
 380                  struct pipe_fence_handle *fence,
 381                  uint64_t timeout)
 382 {
 383    return TRUE;
 384 }
 385
 386
 387 /*
 388  * Generic functions
 389  */
 390
 391
 392 static void
 393 brw_destroy_screen(struct pipe_screen *screen)
 394 {
 395    struct brw_screen *bscreen = brw_screen(screen);
 396
 397    if (bscreen->sws)
 398       bscreen->sws->destroy(bscreen->sws);
 399
 400    FREE(bscreen);
 401 }
 402
 403 /**
 404  * Create a new brw_screen object
 405  */
 406 struct pipe_screen *
 407 brw_screen_create(struct brw_winsys_screen *sws)
 408 {
 409    struct brw_screen *bscreen;
 410 #ifdef DEBUG
 411    BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0);
 412    BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0);
 413    BRW_DEBUG |= DEBUG_STATS | DEBUG_MIN_URB | DEBUG_WM;
 414
 415    BRW_DUMP = debug_get_flags_option("BRW_DUMP", dump_names, 0);
 416 #endif
 417
 418    bscreen = CALLOC_STRUCT(brw_screen);
 419    if (!bscreen)
 420       return NULL;
 421
 422    bscreen->pci_id = sws->pci_id;
 423    if (IS_GEN6(sws->pci_id)) {
 424        bscreen->gen = 6;
 425        bscreen->needs_ff_sync = TRUE;
 426    } else if (IS_GEN5(sws->pci_id)) {
 427        bscreen->gen = 5;
 428        bscreen->needs_ff_sync = TRUE;
 429    } else if (IS_965(sws->pci_id)) {
 430        bscreen->gen = 4;
 431        if (IS_G4X(sws->pci_id)) {
 432            bscreen->is_g4x = true;
 433        }
 434    } else {
 435       debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
 436                    __FUNCTION__, sws->pci_id);
 437       free(bscreen);
 438       return NULL;
 439    }
 440
 441    sws->gen = bscreen->gen;
 442    bscreen->sws = sws;
 443    bscreen->base.winsys = NULL;
 444    bscreen->base.destroy = brw_destroy_screen;
 445    bscreen->base.get_name = brw_get_name;
 446    bscreen->base.get_vendor = brw_get_vendor;
 447    bscreen->base.get_param = brw_get_param;
 448    bscreen->base.get_shader_param = brw_get_shader_param;
 449    bscreen->base.get_paramf = brw_get_paramf;
 450    bscreen->base.is_format_supported = brw_is_format_supported;
 451    bscreen->base.context_create = brw_create_context;
 452    bscreen->base.fence_reference = brw_fence_reference;
 453    bscreen->base.fence_signalled = brw_fence_signalled;
 454    bscreen->base.fence_finish = brw_fence_finish;
 455
 456    brw_init_screen_resource_functions(bscreen);
 457
 458    bscreen->no_tiling = debug_get_option("BRW_NO_TILING", FALSE) != NULL;
 459
 460
 461    return &bscreen->base;
 462 }