1 /**************************************************************************
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
29 #ifndef SPU_TGSI_EXEC_H
30 #define SPU_TGSI_EXEC_H
32 #include "pipe/p_compiler.h"
33 #include "pipe/p_state.h"
35 #if defined __cplusplus
40 #define NUM_CHANNELS 4 /* R,G,B,A */
41 #define QUAD_SIZE 4 /* 4 pixel/quad */
45 #define TGSI_EXEC_NUM_TEMPS 128
46 #define TGSI_EXEC_NUM_IMMEDIATES 256
49 * Locations of various utility registers (_I = Index, _C = Channel)
51 #define TGSI_EXEC_TEMP_00000000_IDX (TGSI_EXEC_NUM_TEMPS + 0)
52 #define TGSI_EXEC_TEMP_00000000_CHAN 0
54 #define TGSI_EXEC_TEMP_7FFFFFFF_IDX (TGSI_EXEC_NUM_TEMPS + 0)
55 #define TGSI_EXEC_TEMP_7FFFFFFF_CHAN 1
57 #define TGSI_EXEC_TEMP_80000000_IDX (TGSI_EXEC_NUM_TEMPS + 0)
58 #define TGSI_EXEC_TEMP_80000000_CHAN 2
60 #define TGSI_EXEC_TEMP_FFFFFFFF_IDX (TGSI_EXEC_NUM_TEMPS + 0)
61 #define TGSI_EXEC_TEMP_FFFFFFFF_CHAN 3
63 #define TGSI_EXEC_TEMP_ONE_IDX (TGSI_EXEC_NUM_TEMPS + 1)
64 #define TGSI_EXEC_TEMP_ONE_CHAN 0
66 #define TGSI_EXEC_TEMP_TWO_IDX (TGSI_EXEC_NUM_TEMPS + 1)
67 #define TGSI_EXEC_TEMP_TWO_CHAN 1
69 #define TGSI_EXEC_TEMP_128_IDX (TGSI_EXEC_NUM_TEMPS + 1)
70 #define TGSI_EXEC_TEMP_128_CHAN 2
72 #define TGSI_EXEC_TEMP_MINUS_128_IDX (TGSI_EXEC_NUM_TEMPS + 1)
73 #define TGSI_EXEC_TEMP_MINUS_128_CHAN 3
75 #define TGSI_EXEC_TEMP_KILMASK_IDX (TGSI_EXEC_NUM_TEMPS + 2)
76 #define TGSI_EXEC_TEMP_KILMASK_CHAN 0
78 #define TGSI_EXEC_TEMP_OUTPUT_IDX (TGSI_EXEC_NUM_TEMPS + 2)
79 #define TGSI_EXEC_TEMP_OUTPUT_CHAN 1
81 #define TGSI_EXEC_TEMP_PRIMITIVE_IDX (TGSI_EXEC_NUM_TEMPS + 2)
82 #define TGSI_EXEC_TEMP_PRIMITIVE_CHAN 2
84 /* NVIDIA condition code (CC) vector
86 #define TGSI_EXEC_CC_GT 0x01
87 #define TGSI_EXEC_CC_EQ 0x02
88 #define TGSI_EXEC_CC_LT 0x04
89 #define TGSI_EXEC_CC_UN 0x08
91 #define TGSI_EXEC_CC_X_MASK 0x000000ff
92 #define TGSI_EXEC_CC_X_SHIFT 0
93 #define TGSI_EXEC_CC_Y_MASK 0x0000ff00
94 #define TGSI_EXEC_CC_Y_SHIFT 8
95 #define TGSI_EXEC_CC_Z_MASK 0x00ff0000
96 #define TGSI_EXEC_CC_Z_SHIFT 16
97 #define TGSI_EXEC_CC_W_MASK 0xff000000
98 #define TGSI_EXEC_CC_W_SHIFT 24
100 #define TGSI_EXEC_TEMP_CC_IDX (TGSI_EXEC_NUM_TEMPS + 2)
101 #define TGSI_EXEC_TEMP_CC_CHAN 3
103 #define TGSI_EXEC_TEMP_THREE_IDX (TGSI_EXEC_NUM_TEMPS + 3)
104 #define TGSI_EXEC_TEMP_THREE_CHAN 0
106 #define TGSI_EXEC_TEMP_HALF_IDX (TGSI_EXEC_NUM_TEMPS + 3)
107 #define TGSI_EXEC_TEMP_HALF_CHAN 1
109 /* execution mask, each value is either 0 or ~0 */
110 #define TGSI_EXEC_MASK_IDX (TGSI_EXEC_NUM_TEMPS + 3)
111 #define TGSI_EXEC_MASK_CHAN 2
113 /* 4 register buffer for various purposes */
114 #define TGSI_EXEC_TEMP_R0 (TGSI_EXEC_NUM_TEMPS + 4)
115 #define TGSI_EXEC_NUM_TEMP_R 4
117 #define TGSI_EXEC_TEMP_ADDR (TGSI_EXEC_NUM_TEMPS + 8)
118 #define TGSI_EXEC_NUM_ADDRS 1
120 /* predicate register */
121 #define TGSI_EXEC_TEMP_P0 (TGSI_EXEC_NUM_TEMPS + 9)
122 #define TGSI_EXEC_NUM_PREDS 1
124 #define TGSI_EXEC_NUM_TEMP_EXTRAS 10
128 #define TGSI_EXEC_MAX_NESTING 32
129 #define TGSI_EXEC_MAX_COND_NESTING TGSI_EXEC_MAX_NESTING
130 #define TGSI_EXEC_MAX_LOOP_NESTING TGSI_EXEC_MAX_NESTING
131 #define TGSI_EXEC_MAX_SWITCH_NESTING TGSI_EXEC_MAX_NESTING
132 #define TGSI_EXEC_MAX_CALL_NESTING TGSI_EXEC_MAX_NESTING
134 /* The maximum number of input attributes per vertex. For 2D
135 * input register files, this is the stride between two 1D
138 #define TGSI_EXEC_MAX_INPUT_ATTRIBS 17
140 /* The maximum number of constant vectors per constant buffer.
142 #define TGSI_EXEC_MAX_CONST_BUFFER 4096
144 /* The maximum number of vertices per primitive */
145 #define TGSI_MAX_PRIM_VERTICES 6
147 /* The maximum number of primitives to be generated */
148 #define TGSI_MAX_PRIMITIVES 64
150 /* The maximum total number of vertices */
151 #define TGSI_MAX_TOTAL_VERTICES (TGSI_MAX_PRIM_VERTICES * TGSI_MAX_PRIMITIVES * PIPE_MAX_ATTRIBS)
154 #if defined __cplusplus
158 #endif /* TGSI_EXEC_H */