1 /**************************************************************************
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
113 micro_clamp(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src0,
115 const union tgsi_exec_channel *src1,
116 const union tgsi_exec_channel *src2)
118 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
119 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
120 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
121 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
125 micro_cmp(union tgsi_exec_channel *dst,
126 const union tgsi_exec_channel *src0,
127 const union tgsi_exec_channel *src1,
128 const union tgsi_exec_channel *src2)
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
137 micro_cnd(union tgsi_exec_channel *dst,
138 const union tgsi_exec_channel *src0,
139 const union tgsi_exec_channel *src1,
140 const union tgsi_exec_channel *src2)
142 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
143 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
144 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
145 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
149 micro_cos(union tgsi_exec_channel *dst,
150 const union tgsi_exec_channel *src)
152 dst->f[0] = cosf(src->f[0]);
153 dst->f[1] = cosf(src->f[1]);
154 dst->f[2] = cosf(src->f[2]);
155 dst->f[3] = cosf(src->f[3]);
159 micro_ddx(union tgsi_exec_channel *dst,
160 const union tgsi_exec_channel *src)
165 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
169 micro_ddy(union tgsi_exec_channel *dst,
170 const union tgsi_exec_channel *src)
175 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
179 micro_exp2(union tgsi_exec_channel *dst,
180 const union tgsi_exec_channel *src)
183 dst->f[0] = util_fast_exp2(src->f[0]);
184 dst->f[1] = util_fast_exp2(src->f[1]);
185 dst->f[2] = util_fast_exp2(src->f[2]);
186 dst->f[3] = util_fast_exp2(src->f[3]);
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
191 union tgsi_exec_channel clamped;
193 for (i = 0; i < 4; i++) {
194 if (src->f[i] > 127.99999f) {
195 clamped.f[i] = 127.99999f;
196 } else if (src->f[i] < -126.99999f) {
197 clamped.f[i] = -126.99999f;
199 clamped.f[i] = src->f[i];
205 dst->f[0] = powf(2.0f, src->f[0]);
206 dst->f[1] = powf(2.0f, src->f[1]);
207 dst->f[2] = powf(2.0f, src->f[2]);
208 dst->f[3] = powf(2.0f, src->f[3]);
209 #endif /* FAST_MATH */
213 micro_flr(union tgsi_exec_channel *dst,
214 const union tgsi_exec_channel *src)
216 dst->f[0] = floorf(src->f[0]);
217 dst->f[1] = floorf(src->f[1]);
218 dst->f[2] = floorf(src->f[2]);
219 dst->f[3] = floorf(src->f[3]);
223 micro_frc(union tgsi_exec_channel *dst,
224 const union tgsi_exec_channel *src)
226 dst->f[0] = src->f[0] - floorf(src->f[0]);
227 dst->f[1] = src->f[1] - floorf(src->f[1]);
228 dst->f[2] = src->f[2] - floorf(src->f[2]);
229 dst->f[3] = src->f[3] - floorf(src->f[3]);
233 micro_iabs(union tgsi_exec_channel *dst,
234 const union tgsi_exec_channel *src)
236 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
237 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
238 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
239 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
243 micro_ineg(union tgsi_exec_channel *dst,
244 const union tgsi_exec_channel *src)
246 dst->i[0] = -src->i[0];
247 dst->i[1] = -src->i[1];
248 dst->i[2] = -src->i[2];
249 dst->i[3] = -src->i[3];
253 micro_lg2(union tgsi_exec_channel *dst,
254 const union tgsi_exec_channel *src)
257 dst->f[0] = util_fast_log2(src->f[0]);
258 dst->f[1] = util_fast_log2(src->f[1]);
259 dst->f[2] = util_fast_log2(src->f[2]);
260 dst->f[3] = util_fast_log2(src->f[3]);
262 dst->f[0] = logf(src->f[0]) * 1.442695f;
263 dst->f[1] = logf(src->f[1]) * 1.442695f;
264 dst->f[2] = logf(src->f[2]) * 1.442695f;
265 dst->f[3] = logf(src->f[3]) * 1.442695f;
270 micro_lrp(union tgsi_exec_channel *dst,
271 const union tgsi_exec_channel *src0,
272 const union tgsi_exec_channel *src1,
273 const union tgsi_exec_channel *src2)
275 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
276 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
277 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
278 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
282 micro_mad(union tgsi_exec_channel *dst,
283 const union tgsi_exec_channel *src0,
284 const union tgsi_exec_channel *src1,
285 const union tgsi_exec_channel *src2)
287 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
288 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
289 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
290 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
294 micro_mov(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
297 dst->u[0] = src->u[0];
298 dst->u[1] = src->u[1];
299 dst->u[2] = src->u[2];
300 dst->u[3] = src->u[3];
304 micro_rcp(union tgsi_exec_channel *dst,
305 const union tgsi_exec_channel *src)
307 #if 0 /* for debugging */
308 assert(src->f[0] != 0.0f);
309 assert(src->f[1] != 0.0f);
310 assert(src->f[2] != 0.0f);
311 assert(src->f[3] != 0.0f);
313 dst->f[0] = 1.0f / src->f[0];
314 dst->f[1] = 1.0f / src->f[1];
315 dst->f[2] = 1.0f / src->f[2];
316 dst->f[3] = 1.0f / src->f[3];
320 micro_rnd(union tgsi_exec_channel *dst,
321 const union tgsi_exec_channel *src)
323 dst->f[0] = floorf(src->f[0] + 0.5f);
324 dst->f[1] = floorf(src->f[1] + 0.5f);
325 dst->f[2] = floorf(src->f[2] + 0.5f);
326 dst->f[3] = floorf(src->f[3] + 0.5f);
330 micro_rsq(union tgsi_exec_channel *dst,
331 const union tgsi_exec_channel *src)
333 #if 0 /* for debugging */
334 assert(src->f[0] != 0.0f);
335 assert(src->f[1] != 0.0f);
336 assert(src->f[2] != 0.0f);
337 assert(src->f[3] != 0.0f);
339 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
340 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
341 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
342 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
346 micro_seq(union tgsi_exec_channel *dst,
347 const union tgsi_exec_channel *src0,
348 const union tgsi_exec_channel *src1)
350 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
351 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
352 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
353 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
357 micro_sge(union tgsi_exec_channel *dst,
358 const union tgsi_exec_channel *src0,
359 const union tgsi_exec_channel *src1)
361 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
362 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
363 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
364 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
368 micro_sgn(union tgsi_exec_channel *dst,
369 const union tgsi_exec_channel *src)
371 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
372 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
373 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
374 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
378 micro_sgt(union tgsi_exec_channel *dst,
379 const union tgsi_exec_channel *src0,
380 const union tgsi_exec_channel *src1)
382 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
383 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
384 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
385 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
389 micro_sin(union tgsi_exec_channel *dst,
390 const union tgsi_exec_channel *src)
392 dst->f[0] = sinf(src->f[0]);
393 dst->f[1] = sinf(src->f[1]);
394 dst->f[2] = sinf(src->f[2]);
395 dst->f[3] = sinf(src->f[3]);
399 micro_sle(union tgsi_exec_channel *dst,
400 const union tgsi_exec_channel *src0,
401 const union tgsi_exec_channel *src1)
403 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
404 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
405 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
406 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
410 micro_slt(union tgsi_exec_channel *dst,
411 const union tgsi_exec_channel *src0,
412 const union tgsi_exec_channel *src1)
414 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
415 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
416 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
417 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
421 micro_sne(union tgsi_exec_channel *dst,
422 const union tgsi_exec_channel *src0,
423 const union tgsi_exec_channel *src1)
425 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
426 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
427 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
428 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
432 micro_sfl(union tgsi_exec_channel *dst)
441 micro_str(union tgsi_exec_channel *dst)
450 micro_trunc(union tgsi_exec_channel *dst,
451 const union tgsi_exec_channel *src)
453 dst->f[0] = (float)(int)src->f[0];
454 dst->f[1] = (float)(int)src->f[1];
455 dst->f[2] = (float)(int)src->f[2];
456 dst->f[3] = (float)(int)src->f[3];
465 enum tgsi_exec_datatype {
466 TGSI_EXEC_DATA_FLOAT,
472 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
474 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
475 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
476 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
477 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
478 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
479 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
482 /** The execution mask depends on the conditional mask and the loop mask */
483 #define UPDATE_EXEC_MASK(MACH) \
484 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
487 static const union tgsi_exec_channel ZeroVec =
488 { { 0.0, 0.0, 0.0, 0.0 } };
490 static const union tgsi_exec_channel OneVec = {
491 {1.0f, 1.0f, 1.0f, 1.0f}
494 static const union tgsi_exec_channel P128Vec = {
495 {128.0f, 128.0f, 128.0f, 128.0f}
498 static const union tgsi_exec_channel M128Vec = {
499 {-128.0f, -128.0f, -128.0f, -128.0f}
504 * Assert that none of the float values in 'chan' are infinite or NaN.
505 * NaN and Inf may occur normally during program execution and should
506 * not lead to crashes, etc. But when debugging, it's helpful to catch
510 check_inf_or_nan(const union tgsi_exec_channel *chan)
512 assert(!util_is_inf_or_nan((chan)->f[0]));
513 assert(!util_is_inf_or_nan((chan)->f[1]));
514 assert(!util_is_inf_or_nan((chan)->f[2]));
515 assert(!util_is_inf_or_nan((chan)->f[3]));
521 print_chan(const char *msg, const union tgsi_exec_channel *chan)
523 debug_printf("%s = {%f, %f, %f, %f}\n",
524 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
531 print_temp(const struct tgsi_exec_machine *mach, uint index)
533 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
535 debug_printf("Temp[%u] =\n", index);
536 for (i = 0; i < 4; i++) {
537 debug_printf(" %c: { %f, %f, %f, %f }\n",
549 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
552 const unsigned *buf_sizes)
556 for (i = 0; i < num_bufs; i++) {
557 mach->Consts[i] = bufs[i];
558 mach->ConstsSize[i] = buf_sizes[i];
564 * Check if there's a potential src/dst register data dependency when
565 * using SOA execution.
568 * This would expand into:
573 * The second instruction will have the wrong value for t0 if executed as-is.
576 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
580 uint writemask = inst->Dst[0].Register.WriteMask;
581 if (writemask == TGSI_WRITEMASK_X ||
582 writemask == TGSI_WRITEMASK_Y ||
583 writemask == TGSI_WRITEMASK_Z ||
584 writemask == TGSI_WRITEMASK_W ||
585 writemask == TGSI_WRITEMASK_NONE) {
586 /* no chance of data dependency */
590 /* loop over src regs */
591 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
592 if ((inst->Src[i].Register.File ==
593 inst->Dst[0].Register.File) &&
594 ((inst->Src[i].Register.Index ==
595 inst->Dst[0].Register.Index) ||
596 inst->Src[i].Register.Indirect ||
597 inst->Dst[0].Register.Indirect)) {
598 /* loop over dest channels */
599 uint channelsWritten = 0x0;
600 for (chan = 0; chan < NUM_CHANNELS; chan++) {
601 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
602 /* check if we're reading a channel that's been written */
603 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
604 if (channelsWritten & (1 << swizzle)) {
608 channelsWritten |= (1 << chan);
618 * Initialize machine state by expanding tokens to full instructions,
619 * allocating temporary storage, setting up constants, etc.
620 * After this, we can call tgsi_exec_machine_run() many times.
623 tgsi_exec_machine_bind_shader(
624 struct tgsi_exec_machine *mach,
625 const struct tgsi_token *tokens,
627 struct tgsi_sampler **samplers)
630 struct tgsi_parse_context parse;
631 struct tgsi_full_instruction *instructions;
632 struct tgsi_full_declaration *declarations;
633 uint maxInstructions = 10, numInstructions = 0;
634 uint maxDeclarations = 10, numDeclarations = 0;
637 tgsi_dump(tokens, 0);
646 mach->Tokens = tokens;
647 mach->Samplers = samplers;
650 /* unbind and free all */
651 if (mach->Declarations) {
652 FREE( mach->Declarations );
654 mach->Declarations = NULL;
655 mach->NumDeclarations = 0;
657 if (mach->Instructions) {
658 FREE( mach->Instructions );
660 mach->Instructions = NULL;
661 mach->NumInstructions = 0;
666 k = tgsi_parse_init (&parse, mach->Tokens);
667 if (k != TGSI_PARSE_OK) {
668 debug_printf( "Problem parsing!\n" );
672 mach->Processor = parse.FullHeader.Processor.Processor;
675 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
676 !mach->UsedGeometryShader) {
677 struct tgsi_exec_vector *inputs =
678 align_malloc(sizeof(struct tgsi_exec_vector) *
679 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS,
681 struct tgsi_exec_vector *outputs =
682 align_malloc(sizeof(struct tgsi_exec_vector) *
683 TGSI_MAX_TOTAL_VERTICES, 16);
692 align_free(mach->Inputs);
693 align_free(mach->Outputs);
695 mach->Inputs = inputs;
696 mach->Outputs = outputs;
697 mach->UsedGeometryShader = TRUE;
700 declarations = (struct tgsi_full_declaration *)
701 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
707 instructions = (struct tgsi_full_instruction *)
708 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
711 FREE( declarations );
715 while( !tgsi_parse_end_of_tokens( &parse ) ) {
718 tgsi_parse_token( &parse );
719 switch( parse.FullToken.Token.Type ) {
720 case TGSI_TOKEN_TYPE_DECLARATION:
721 /* save expanded declaration */
722 if (numDeclarations == maxDeclarations) {
723 declarations = REALLOC(declarations,
725 * sizeof(struct tgsi_full_declaration),
726 (maxDeclarations + 10)
727 * sizeof(struct tgsi_full_declaration));
728 maxDeclarations += 10;
730 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
732 for (reg = parse.FullToken.FullDeclaration.Range.First;
733 reg <= parse.FullToken.FullDeclaration.Range.Last;
738 if (parse.FullToken.FullDeclaration.Declaration.File ==
739 TGSI_FILE_IMMEDIATE_ARRAY) {
741 struct tgsi_full_declaration *decl =
742 &parse.FullToken.FullDeclaration;
743 debug_assert(decl->Range.Last < TGSI_EXEC_NUM_IMMEDIATES);
744 for (reg = decl->Range.First; reg <= decl->Range.Last; ++reg) {
745 for( i = 0; i < 4; i++ ) {
746 int idx = reg * 4 + i;
747 mach->ImmArray[reg][i] = decl->ImmediateData.u[idx].Float;
751 memcpy(declarations + numDeclarations,
752 &parse.FullToken.FullDeclaration,
753 sizeof(declarations[0]));
757 case TGSI_TOKEN_TYPE_IMMEDIATE:
759 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
761 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
763 for( i = 0; i < size; i++ ) {
764 mach->Imms[mach->ImmLimit][i] =
765 parse.FullToken.FullImmediate.u[i].Float;
771 case TGSI_TOKEN_TYPE_INSTRUCTION:
773 /* save expanded instruction */
774 if (numInstructions == maxInstructions) {
775 instructions = REALLOC(instructions,
777 * sizeof(struct tgsi_full_instruction),
778 (maxInstructions + 10)
779 * sizeof(struct tgsi_full_instruction));
780 maxInstructions += 10;
783 memcpy(instructions + numInstructions,
784 &parse.FullToken.FullInstruction,
785 sizeof(instructions[0]));
790 case TGSI_TOKEN_TYPE_PROPERTY:
797 tgsi_parse_free (&parse);
799 if (mach->Declarations) {
800 FREE( mach->Declarations );
802 mach->Declarations = declarations;
803 mach->NumDeclarations = numDeclarations;
805 if (mach->Instructions) {
806 FREE( mach->Instructions );
808 mach->Instructions = instructions;
809 mach->NumInstructions = numInstructions;
813 struct tgsi_exec_machine *
814 tgsi_exec_machine_create( void )
816 struct tgsi_exec_machine *mach;
819 mach = align_malloc( sizeof *mach, 16 );
823 memset(mach, 0, sizeof(*mach));
825 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
826 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
827 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
829 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
830 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
831 if (!mach->Inputs || !mach->Outputs)
834 /* Setup constants needed by the SSE2 executor. */
835 for( i = 0; i < 4; i++ ) {
836 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
837 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
838 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
839 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
840 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
841 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
842 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
843 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
844 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
845 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
849 /* silence warnings */
858 align_free(mach->Inputs);
859 align_free(mach->Outputs);
867 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
870 if (mach->Instructions)
871 FREE(mach->Instructions);
872 if (mach->Declarations)
873 FREE(mach->Declarations);
875 align_free(mach->Inputs);
876 align_free(mach->Outputs);
883 micro_add(union tgsi_exec_channel *dst,
884 const union tgsi_exec_channel *src0,
885 const union tgsi_exec_channel *src1)
887 dst->f[0] = src0->f[0] + src1->f[0];
888 dst->f[1] = src0->f[1] + src1->f[1];
889 dst->f[2] = src0->f[2] + src1->f[2];
890 dst->f[3] = src0->f[3] + src1->f[3];
895 union tgsi_exec_channel *dst,
896 const union tgsi_exec_channel *src0,
897 const union tgsi_exec_channel *src1 )
899 if (src1->f[0] != 0) {
900 dst->f[0] = src0->f[0] / src1->f[0];
902 if (src1->f[1] != 0) {
903 dst->f[1] = src0->f[1] / src1->f[1];
905 if (src1->f[2] != 0) {
906 dst->f[2] = src0->f[2] / src1->f[2];
908 if (src1->f[3] != 0) {
909 dst->f[3] = src0->f[3] / src1->f[3];
914 micro_rcc(union tgsi_exec_channel *dst,
915 const union tgsi_exec_channel *src)
919 for (i = 0; i < 4; i++) {
920 float recip = 1.0f / src->f[i];
923 if (recip > 1.884467e+019f) {
924 dst->f[i] = 1.884467e+019f;
926 else if (recip < 5.42101e-020f) {
927 dst->f[i] = 5.42101e-020f;
934 if (recip < -1.884467e+019f) {
935 dst->f[i] = -1.884467e+019f;
937 else if (recip > -5.42101e-020f) {
938 dst->f[i] = -5.42101e-020f;
949 union tgsi_exec_channel *dst,
950 const union tgsi_exec_channel *src0,
951 const union tgsi_exec_channel *src1,
952 const union tgsi_exec_channel *src2,
953 const union tgsi_exec_channel *src3 )
955 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
956 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
957 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
958 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
962 micro_max(union tgsi_exec_channel *dst,
963 const union tgsi_exec_channel *src0,
964 const union tgsi_exec_channel *src1)
966 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
967 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
968 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
969 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
973 micro_min(union tgsi_exec_channel *dst,
974 const union tgsi_exec_channel *src0,
975 const union tgsi_exec_channel *src1)
977 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
978 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
979 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
980 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
984 micro_mul(union tgsi_exec_channel *dst,
985 const union tgsi_exec_channel *src0,
986 const union tgsi_exec_channel *src1)
988 dst->f[0] = src0->f[0] * src1->f[0];
989 dst->f[1] = src0->f[1] * src1->f[1];
990 dst->f[2] = src0->f[2] * src1->f[2];
991 dst->f[3] = src0->f[3] * src1->f[3];
996 union tgsi_exec_channel *dst,
997 const union tgsi_exec_channel *src )
999 dst->f[0] = -src->f[0];
1000 dst->f[1] = -src->f[1];
1001 dst->f[2] = -src->f[2];
1002 dst->f[3] = -src->f[3];
1007 union tgsi_exec_channel *dst,
1008 const union tgsi_exec_channel *src0,
1009 const union tgsi_exec_channel *src1 )
1012 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1013 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1014 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1015 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1017 dst->f[0] = powf( src0->f[0], src1->f[0] );
1018 dst->f[1] = powf( src0->f[1], src1->f[1] );
1019 dst->f[2] = powf( src0->f[2], src1->f[2] );
1020 dst->f[3] = powf( src0->f[3], src1->f[3] );
1025 micro_sub(union tgsi_exec_channel *dst,
1026 const union tgsi_exec_channel *src0,
1027 const union tgsi_exec_channel *src1)
1029 dst->f[0] = src0->f[0] - src1->f[0];
1030 dst->f[1] = src0->f[1] - src1->f[1];
1031 dst->f[2] = src0->f[2] - src1->f[2];
1032 dst->f[3] = src0->f[3] - src1->f[3];
1036 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1039 const union tgsi_exec_channel *index,
1040 const union tgsi_exec_channel *index2D,
1041 union tgsi_exec_channel *chan)
1045 assert(swizzle < 4);
1048 case TGSI_FILE_CONSTANT:
1049 for (i = 0; i < QUAD_SIZE; i++) {
1050 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1051 assert(mach->Consts[index2D->i[i]]);
1053 if (index->i[i] < 0) {
1056 /* NOTE: copying the const value as a uint instead of float */
1057 const uint constbuf = index2D->i[i];
1058 const uint *buf = (const uint *)mach->Consts[constbuf];
1059 const int pos = index->i[i] * 4 + swizzle;
1060 /* const buffer bounds check */
1061 if (pos < 0 || pos >= mach->ConstsSize[constbuf]) {
1063 /* Debug: print warning */
1064 static int count = 0;
1066 debug_printf("TGSI Exec: const buffer index %d"
1067 " out of bounds\n", pos);
1072 chan->u[i] = buf[pos];
1077 case TGSI_FILE_INPUT:
1078 for (i = 0; i < QUAD_SIZE; i++) {
1080 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1081 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1082 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1083 index2D->i[i], index->i[i]);
1085 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1087 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1088 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1092 case TGSI_FILE_SYSTEM_VALUE:
1093 /* XXX no swizzling at this point. Will be needed if we put
1094 * gl_FragCoord, for example, in a sys value register.
1096 for (i = 0; i < QUAD_SIZE; i++) {
1097 chan->f[i] = mach->SystemValue[index->i[i]][0];
1101 case TGSI_FILE_TEMPORARY:
1102 for (i = 0; i < QUAD_SIZE; i++) {
1103 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1104 assert(index2D->i[i] == 0);
1106 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1110 case TGSI_FILE_TEMPORARY_ARRAY:
1111 for (i = 0; i < QUAD_SIZE; i++) {
1112 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1113 assert(index2D->i[i] < TGSI_EXEC_NUM_TEMP_ARRAYS);
1116 mach->TempArray[index2D->i[i]][index->i[i]].xyzw[swizzle].u[i];
1120 case TGSI_FILE_IMMEDIATE:
1121 for (i = 0; i < QUAD_SIZE; i++) {
1122 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1123 assert(index2D->i[i] == 0);
1125 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1129 case TGSI_FILE_IMMEDIATE_ARRAY:
1130 for (i = 0; i < QUAD_SIZE; i++) {
1131 assert(index2D->i[i] == 0);
1133 chan->f[i] = mach->ImmArray[index->i[i]][swizzle];
1137 case TGSI_FILE_ADDRESS:
1138 for (i = 0; i < QUAD_SIZE; i++) {
1139 assert(index->i[i] >= 0);
1140 assert(index2D->i[i] == 0);
1142 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1146 case TGSI_FILE_PREDICATE:
1147 for (i = 0; i < QUAD_SIZE; i++) {
1148 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1149 assert(index2D->i[i] == 0);
1151 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1155 case TGSI_FILE_OUTPUT:
1156 /* vertex/fragment output vars can be read too */
1157 for (i = 0; i < QUAD_SIZE; i++) {
1158 assert(index->i[i] >= 0);
1159 assert(index2D->i[i] == 0);
1161 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1167 for (i = 0; i < QUAD_SIZE; i++) {
1174 fetch_source(const struct tgsi_exec_machine *mach,
1175 union tgsi_exec_channel *chan,
1176 const struct tgsi_full_src_register *reg,
1177 const uint chan_index,
1178 enum tgsi_exec_datatype src_datatype)
1180 union tgsi_exec_channel index;
1181 union tgsi_exec_channel index2D;
1184 /* We start with a direct index into a register file.
1188 * file = Register.File
1189 * [1] = Register.Index
1194 index.i[3] = reg->Register.Index;
1196 /* There is an extra source register that indirectly subscripts
1197 * a register file. The direct index now becomes an offset
1198 * that is being added to the indirect register.
1202 * ind = Indirect.File
1203 * [2] = Indirect.Index
1204 * .x = Indirect.SwizzleX
1206 if (reg->Register.Indirect) {
1207 union tgsi_exec_channel index2;
1208 union tgsi_exec_channel indir_index;
1209 const uint execmask = mach->ExecMask;
1212 /* which address register (always zero now) */
1216 index2.i[3] = reg->Indirect.Index;
1217 assert(reg->Indirect.File == TGSI_FILE_ADDRESS);
1218 /* get current value of address register[swizzle] */
1219 swizzle = tgsi_util_get_src_register_swizzle( ®->Indirect, CHAN_X );
1220 fetch_src_file_channel(mach,
1227 /* add value of address register to the offset */
1228 index.i[0] += indir_index.i[0];
1229 index.i[1] += indir_index.i[1];
1230 index.i[2] += indir_index.i[2];
1231 index.i[3] += indir_index.i[3];
1233 /* for disabled execution channels, zero-out the index to
1234 * avoid using a potential garbage value.
1236 for (i = 0; i < QUAD_SIZE; i++) {
1237 if ((execmask & (1 << i)) == 0)
1242 /* There is an extra source register that is a second
1243 * subscript to a register file. Effectively it means that
1244 * the register file is actually a 2D array of registers.
1248 * [3] = Dimension.Index
1250 if (reg->Register.Dimension) {
1254 index2D.i[3] = reg->Dimension.Index;
1256 /* Again, the second subscript index can be addressed indirectly
1257 * identically to the first one.
1258 * Nothing stops us from indirectly addressing the indirect register,
1259 * but there is no need for that, so we won't exercise it.
1261 * file[ind[4].y+3][1],
1263 * ind = DimIndirect.File
1264 * [4] = DimIndirect.Index
1265 * .y = DimIndirect.SwizzleX
1267 if (reg->Dimension.Indirect) {
1268 union tgsi_exec_channel index2;
1269 union tgsi_exec_channel indir_index;
1270 const uint execmask = mach->ExecMask;
1276 index2.i[3] = reg->DimIndirect.Index;
1278 swizzle = tgsi_util_get_src_register_swizzle( ®->DimIndirect, CHAN_X );
1279 fetch_src_file_channel(mach,
1280 reg->DimIndirect.File,
1286 index2D.i[0] += indir_index.i[0];
1287 index2D.i[1] += indir_index.i[1];
1288 index2D.i[2] += indir_index.i[2];
1289 index2D.i[3] += indir_index.i[3];
1291 /* for disabled execution channels, zero-out the index to
1292 * avoid using a potential garbage value.
1294 for (i = 0; i < QUAD_SIZE; i++) {
1295 if ((execmask & (1 << i)) == 0) {
1301 /* If by any chance there was a need for a 3D array of register
1302 * files, we would have to check whether Dimension is followed
1303 * by a dimension register and continue the saga.
1312 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1313 fetch_src_file_channel(mach,
1320 if (reg->Register.Absolute) {
1321 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1322 micro_abs(chan, chan);
1324 micro_iabs(chan, chan);
1328 if (reg->Register.Negate) {
1329 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1330 micro_neg(chan, chan);
1332 micro_ineg(chan, chan);
1338 store_dest(struct tgsi_exec_machine *mach,
1339 const union tgsi_exec_channel *chan,
1340 const struct tgsi_full_dst_register *reg,
1341 const struct tgsi_full_instruction *inst,
1343 enum tgsi_exec_datatype dst_datatype)
1346 union tgsi_exec_channel null;
1347 union tgsi_exec_channel *dst;
1348 union tgsi_exec_channel index2D;
1349 uint execmask = mach->ExecMask;
1350 int offset = 0; /* indirection offset */
1354 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1355 check_inf_or_nan(chan);
1358 /* There is an extra source register that indirectly subscripts
1359 * a register file. The direct index now becomes an offset
1360 * that is being added to the indirect register.
1364 * ind = Indirect.File
1365 * [2] = Indirect.Index
1366 * .x = Indirect.SwizzleX
1368 if (reg->Register.Indirect) {
1369 union tgsi_exec_channel index;
1370 union tgsi_exec_channel indir_index;
1373 /* which address register (always zero for now) */
1377 index.i[3] = reg->Indirect.Index;
1379 /* get current value of address register[swizzle] */
1380 swizzle = tgsi_util_get_src_register_swizzle( ®->Indirect, CHAN_X );
1382 /* fetch values from the address/indirection register */
1383 fetch_src_file_channel(mach,
1390 /* save indirection offset */
1391 offset = indir_index.i[0];
1394 /* There is an extra source register that is a second
1395 * subscript to a register file. Effectively it means that
1396 * the register file is actually a 2D array of registers.
1400 * [3] = Dimension.Index
1402 if (reg->Register.Dimension) {
1406 index2D.i[3] = reg->Dimension.Index;
1408 /* Again, the second subscript index can be addressed indirectly
1409 * identically to the first one.
1410 * Nothing stops us from indirectly addressing the indirect register,
1411 * but there is no need for that, so we won't exercise it.
1413 * file[ind[4].y+3][1],
1415 * ind = DimIndirect.File
1416 * [4] = DimIndirect.Index
1417 * .y = DimIndirect.SwizzleX
1419 if (reg->Dimension.Indirect) {
1420 union tgsi_exec_channel index2;
1421 union tgsi_exec_channel indir_index;
1422 const uint execmask = mach->ExecMask;
1429 index2.i[3] = reg->DimIndirect.Index;
1431 swizzle = tgsi_util_get_src_register_swizzle( ®->DimIndirect, CHAN_X );
1432 fetch_src_file_channel(mach,
1433 reg->DimIndirect.File,
1439 index2D.i[0] += indir_index.i[0];
1440 index2D.i[1] += indir_index.i[1];
1441 index2D.i[2] += indir_index.i[2];
1442 index2D.i[3] += indir_index.i[3];
1444 /* for disabled execution channels, zero-out the index to
1445 * avoid using a potential garbage value.
1447 for (i = 0; i < QUAD_SIZE; i++) {
1448 if ((execmask & (1 << i)) == 0) {
1454 /* If by any chance there was a need for a 3D array of register
1455 * files, we would have to check whether Dimension is followed
1456 * by a dimension register and continue the saga.
1465 switch (reg->Register.File) {
1466 case TGSI_FILE_NULL:
1470 case TGSI_FILE_OUTPUT:
1471 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1472 + reg->Register.Index;
1473 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1475 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1476 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1477 for (i = 0; i < QUAD_SIZE; i++)
1478 if (execmask & (1 << i))
1479 fprintf(stderr, "%f, ", chan->f[i]);
1480 fprintf(stderr, ")\n");
1485 case TGSI_FILE_TEMPORARY:
1486 index = reg->Register.Index;
1487 assert( index < TGSI_EXEC_NUM_TEMPS );
1488 dst = &mach->Temps[offset + index].xyzw[chan_index];
1491 case TGSI_FILE_TEMPORARY_ARRAY:
1492 index = reg->Register.Index;
1493 assert( index < TGSI_EXEC_NUM_TEMPS );
1494 assert( index2D.i[0] < TGSI_EXEC_NUM_TEMP_ARRAYS );
1495 /* XXX we use index2D.i[0] here but somehow we might
1496 * end up with someone trying to store indirectly in
1497 * different buffers */
1498 dst = &mach->TempArray[index2D.i[0]][offset + index].xyzw[chan_index];
1501 case TGSI_FILE_ADDRESS:
1502 index = reg->Register.Index;
1503 dst = &mach->Addrs[index].xyzw[chan_index];
1506 case TGSI_FILE_PREDICATE:
1507 index = reg->Register.Index;
1508 assert(index < TGSI_EXEC_NUM_PREDS);
1509 dst = &mach->Predicates[index].xyzw[chan_index];
1517 if (inst->Instruction.Predicate) {
1519 union tgsi_exec_channel *pred;
1521 switch (chan_index) {
1523 swizzle = inst->Predicate.SwizzleX;
1526 swizzle = inst->Predicate.SwizzleY;
1529 swizzle = inst->Predicate.SwizzleZ;
1532 swizzle = inst->Predicate.SwizzleW;
1539 assert(inst->Predicate.Index == 0);
1541 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1543 if (inst->Predicate.Negate) {
1544 for (i = 0; i < QUAD_SIZE; i++) {
1546 execmask &= ~(1 << i);
1550 for (i = 0; i < QUAD_SIZE; i++) {
1552 execmask &= ~(1 << i);
1558 switch (inst->Instruction.Saturate) {
1560 for (i = 0; i < QUAD_SIZE; i++)
1561 if (execmask & (1 << i))
1562 dst->i[i] = chan->i[i];
1565 case TGSI_SAT_ZERO_ONE:
1566 for (i = 0; i < QUAD_SIZE; i++)
1567 if (execmask & (1 << i)) {
1568 if (chan->f[i] < 0.0f)
1570 else if (chan->f[i] > 1.0f)
1573 dst->i[i] = chan->i[i];
1577 case TGSI_SAT_MINUS_PLUS_ONE:
1578 for (i = 0; i < QUAD_SIZE; i++)
1579 if (execmask & (1 << i)) {
1580 if (chan->f[i] < -1.0f)
1582 else if (chan->f[i] > 1.0f)
1585 dst->i[i] = chan->i[i];
1594 #define FETCH(VAL,INDEX,CHAN)\
1595 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1599 * Execute ARB-style KIL which is predicated by a src register.
1600 * Kill fragment if any of the four values is less than zero.
1603 exec_kil(struct tgsi_exec_machine *mach,
1604 const struct tgsi_full_instruction *inst)
1608 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1609 union tgsi_exec_channel r[1];
1611 /* This mask stores component bits that were already tested. */
1614 for (chan_index = 0; chan_index < 4; chan_index++)
1619 /* unswizzle channel */
1620 swizzle = tgsi_util_get_full_src_register_swizzle (
1624 /* check if the component has not been already tested */
1625 if (uniquemask & (1 << swizzle))
1627 uniquemask |= 1 << swizzle;
1629 FETCH(&r[0], 0, chan_index);
1630 for (i = 0; i < 4; i++)
1631 if (r[0].f[i] < 0.0f)
1635 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1639 * Execute NVIDIA-style KIL which is predicated by a condition code.
1640 * Kill fragment if the condition code is TRUE.
1643 exec_kilp(struct tgsi_exec_machine *mach,
1644 const struct tgsi_full_instruction *inst)
1646 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1648 /* "unconditional" kil */
1649 kilmask = mach->ExecMask;
1650 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1654 emit_vertex(struct tgsi_exec_machine *mach)
1656 /* FIXME: check for exec mask correctly
1658 for (i = 0; i < QUAD_SIZE; ++i) {
1659 if ((mach->ExecMask & (1 << i)))
1661 if (mach->ExecMask) {
1662 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1663 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1668 emit_primitive(struct tgsi_exec_machine *mach)
1670 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1671 /* FIXME: check for exec mask correctly
1673 for (i = 0; i < QUAD_SIZE; ++i) {
1674 if ((mach->ExecMask & (1 << i)))
1676 if (mach->ExecMask) {
1678 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1679 mach->Primitives[*prim_count] = 0;
1684 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1686 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1688 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1689 if (emitted_verts) {
1690 emit_primitive(mach);
1697 * Fetch four texture samples using STR texture coordinates.
1700 fetch_texel( struct tgsi_sampler *sampler,
1701 const union tgsi_exec_channel *s,
1702 const union tgsi_exec_channel *t,
1703 const union tgsi_exec_channel *p,
1704 const union tgsi_exec_channel *c0,
1705 enum tgsi_sampler_control control,
1706 union tgsi_exec_channel *r,
1707 union tgsi_exec_channel *g,
1708 union tgsi_exec_channel *b,
1709 union tgsi_exec_channel *a )
1712 float rgba[NUM_CHANNELS][QUAD_SIZE];
1714 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, control, rgba);
1716 for (j = 0; j < 4; j++) {
1717 r->f[j] = rgba[0][j];
1718 g->f[j] = rgba[1][j];
1719 b->f[j] = rgba[2][j];
1720 a->f[j] = rgba[3][j];
1725 #define TEX_MODIFIER_NONE 0
1726 #define TEX_MODIFIER_PROJECTED 1
1727 #define TEX_MODIFIER_LOD_BIAS 2
1728 #define TEX_MODIFIER_EXPLICIT_LOD 3
1732 exec_tex(struct tgsi_exec_machine *mach,
1733 const struct tgsi_full_instruction *inst,
1736 const uint unit = inst->Src[1].Register.Index;
1737 union tgsi_exec_channel r[4];
1738 const union tgsi_exec_channel *lod = &ZeroVec;
1739 enum tgsi_sampler_control control;
1742 if (modifier != TEX_MODIFIER_NONE) {
1743 FETCH(&r[3], 0, CHAN_W);
1744 if (modifier != TEX_MODIFIER_PROJECTED) {
1749 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1750 control = tgsi_sampler_lod_explicit;
1752 control = tgsi_sampler_lod_bias;
1755 switch (inst->Texture.Texture) {
1756 case TGSI_TEXTURE_1D:
1757 case TGSI_TEXTURE_SHADOW1D:
1758 FETCH(&r[0], 0, CHAN_X);
1760 if (modifier == TEX_MODIFIER_PROJECTED) {
1761 micro_div(&r[0], &r[0], &r[3]);
1764 fetch_texel(mach->Samplers[unit],
1765 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
1767 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1770 case TGSI_TEXTURE_2D:
1771 case TGSI_TEXTURE_RECT:
1772 case TGSI_TEXTURE_SHADOW2D:
1773 case TGSI_TEXTURE_SHADOWRECT:
1774 FETCH(&r[0], 0, CHAN_X);
1775 FETCH(&r[1], 0, CHAN_Y);
1776 FETCH(&r[2], 0, CHAN_Z);
1778 if (modifier == TEX_MODIFIER_PROJECTED) {
1779 micro_div(&r[0], &r[0], &r[3]);
1780 micro_div(&r[1], &r[1], &r[3]);
1781 micro_div(&r[2], &r[2], &r[3]);
1784 fetch_texel(mach->Samplers[unit],
1785 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1787 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1790 case TGSI_TEXTURE_1D_ARRAY:
1791 FETCH(&r[0], 0, CHAN_X);
1792 FETCH(&r[1], 0, CHAN_Y);
1794 if (modifier == TEX_MODIFIER_PROJECTED) {
1795 micro_div(&r[0], &r[0], &r[3]);
1798 fetch_texel(mach->Samplers[unit],
1799 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1801 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1804 case TGSI_TEXTURE_2D_ARRAY:
1805 FETCH(&r[0], 0, CHAN_X);
1806 FETCH(&r[1], 0, CHAN_Y);
1807 FETCH(&r[2], 0, CHAN_Z);
1809 if (modifier == TEX_MODIFIER_PROJECTED) {
1810 micro_div(&r[0], &r[0], &r[3]);
1811 micro_div(&r[1], &r[1], &r[3]);
1814 fetch_texel(mach->Samplers[unit],
1815 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1817 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1820 case TGSI_TEXTURE_3D:
1821 case TGSI_TEXTURE_CUBE:
1822 FETCH(&r[0], 0, CHAN_X);
1823 FETCH(&r[1], 0, CHAN_Y);
1824 FETCH(&r[2], 0, CHAN_Z);
1826 if (modifier == TEX_MODIFIER_PROJECTED) {
1827 micro_div(&r[0], &r[0], &r[3]);
1828 micro_div(&r[1], &r[1], &r[3]);
1829 micro_div(&r[2], &r[2], &r[3]);
1832 fetch_texel(mach->Samplers[unit],
1833 &r[0], &r[1], &r[2], lod,
1835 &r[0], &r[1], &r[2], &r[3]);
1843 debug_printf("fetch r: %g %g %g %g\n",
1844 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1845 debug_printf("fetch g: %g %g %g %g\n",
1846 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1847 debug_printf("fetch b: %g %g %g %g\n",
1848 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1849 debug_printf("fetch a: %g %g %g %g\n",
1850 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1853 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1854 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1855 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1861 exec_txd(struct tgsi_exec_machine *mach,
1862 const struct tgsi_full_instruction *inst)
1864 const uint unit = inst->Src[3].Register.Index;
1865 union tgsi_exec_channel r[4];
1869 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1872 switch (inst->Texture.Texture) {
1873 case TGSI_TEXTURE_1D:
1874 case TGSI_TEXTURE_SHADOW1D:
1876 FETCH(&r[0], 0, CHAN_X);
1878 fetch_texel(mach->Samplers[unit],
1879 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1880 tgsi_sampler_lod_bias,
1881 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1884 case TGSI_TEXTURE_2D:
1885 case TGSI_TEXTURE_RECT:
1886 case TGSI_TEXTURE_SHADOW2D:
1887 case TGSI_TEXTURE_SHADOWRECT:
1889 FETCH(&r[0], 0, CHAN_X);
1890 FETCH(&r[1], 0, CHAN_Y);
1891 FETCH(&r[2], 0, CHAN_Z);
1893 fetch_texel(mach->Samplers[unit],
1894 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
1895 tgsi_sampler_lod_bias,
1896 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1899 case TGSI_TEXTURE_3D:
1900 case TGSI_TEXTURE_CUBE:
1902 FETCH(&r[0], 0, CHAN_X);
1903 FETCH(&r[1], 0, CHAN_Y);
1904 FETCH(&r[2], 0, CHAN_Z);
1906 fetch_texel(mach->Samplers[unit],
1907 &r[0], &r[1], &r[2], &ZeroVec,
1908 tgsi_sampler_lod_bias,
1909 &r[0], &r[1], &r[2], &r[3]);
1916 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1917 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1918 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1926 exec_sample(struct tgsi_exec_machine *mach,
1927 const struct tgsi_full_instruction *inst,
1930 const uint resource_unit = inst->Src[1].Register.Index;
1931 const uint sampler_unit = inst->Src[2].Register.Index;
1932 union tgsi_exec_channel r[4];
1933 const union tgsi_exec_channel *lod = &ZeroVec;
1934 enum tgsi_sampler_control control;
1937 if (modifier != TEX_MODIFIER_NONE) {
1938 if (modifier == TEX_MODIFIER_LOD_BIAS)
1939 FETCH(&r[3], 3, CHAN_X);
1940 else /*TEX_MODIFIER_LOD*/
1941 FETCH(&r[3], 0, CHAN_W);
1943 if (modifier != TEX_MODIFIER_PROJECTED) {
1948 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1949 control = tgsi_sampler_lod_explicit;
1951 control = tgsi_sampler_lod_bias;
1954 switch (mach->Resources[resource_unit].Resource) {
1955 case TGSI_TEXTURE_1D:
1956 case TGSI_TEXTURE_SHADOW1D:
1957 FETCH(&r[0], 0, CHAN_X);
1959 if (modifier == TEX_MODIFIER_PROJECTED) {
1960 micro_div(&r[0], &r[0], &r[3]);
1963 fetch_texel(mach->Samplers[sampler_unit],
1964 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
1966 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1969 case TGSI_TEXTURE_2D:
1970 case TGSI_TEXTURE_RECT:
1971 case TGSI_TEXTURE_SHADOW2D:
1972 case TGSI_TEXTURE_SHADOWRECT:
1973 FETCH(&r[0], 0, CHAN_X);
1974 FETCH(&r[1], 0, CHAN_Y);
1975 FETCH(&r[2], 0, CHAN_Z);
1977 if (modifier == TEX_MODIFIER_PROJECTED) {
1978 micro_div(&r[0], &r[0], &r[3]);
1979 micro_div(&r[1], &r[1], &r[3]);
1980 micro_div(&r[2], &r[2], &r[3]);
1983 fetch_texel(mach->Samplers[sampler_unit],
1984 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1986 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1989 case TGSI_TEXTURE_3D:
1990 case TGSI_TEXTURE_CUBE:
1991 FETCH(&r[0], 0, CHAN_X);
1992 FETCH(&r[1], 0, CHAN_Y);
1993 FETCH(&r[2], 0, CHAN_Z);
1995 if (modifier == TEX_MODIFIER_PROJECTED) {
1996 micro_div(&r[0], &r[0], &r[3]);
1997 micro_div(&r[1], &r[1], &r[3]);
1998 micro_div(&r[2], &r[2], &r[3]);
2001 fetch_texel(mach->Samplers[sampler_unit],
2002 &r[0], &r[1], &r[2], lod,
2004 &r[0], &r[1], &r[2], &r[3]);
2011 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2012 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2013 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2019 exec_sample_d(struct tgsi_exec_machine *mach,
2020 const struct tgsi_full_instruction *inst)
2022 const uint resource_unit = inst->Src[1].Register.Index;
2023 const uint sampler_unit = inst->Src[2].Register.Index;
2024 union tgsi_exec_channel r[4];
2027 * XXX: This is fake SAMPLE_D -- the derivatives are not taken into account, yet.
2030 switch (mach->Resources[resource_unit].Resource) {
2031 case TGSI_TEXTURE_1D:
2032 case TGSI_TEXTURE_SHADOW1D:
2034 FETCH(&r[0], 0, CHAN_X);
2036 fetch_texel(mach->Samplers[sampler_unit],
2037 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
2038 tgsi_sampler_lod_bias,
2039 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2042 case TGSI_TEXTURE_2D:
2043 case TGSI_TEXTURE_RECT:
2044 case TGSI_TEXTURE_SHADOW2D:
2045 case TGSI_TEXTURE_SHADOWRECT:
2047 FETCH(&r[0], 0, CHAN_X);
2048 FETCH(&r[1], 0, CHAN_Y);
2049 FETCH(&r[2], 0, CHAN_Z);
2051 fetch_texel(mach->Samplers[sampler_unit],
2052 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
2053 tgsi_sampler_lod_bias,
2054 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2057 case TGSI_TEXTURE_3D:
2058 case TGSI_TEXTURE_CUBE:
2060 FETCH(&r[0], 0, CHAN_X);
2061 FETCH(&r[1], 0, CHAN_Y);
2062 FETCH(&r[2], 0, CHAN_Z);
2064 fetch_texel(mach->Samplers[sampler_unit],
2065 &r[0], &r[1], &r[2], &ZeroVec,
2066 tgsi_sampler_lod_bias,
2067 &r[0], &r[1], &r[2], &r[3]);
2074 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2075 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2076 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2083 * Evaluate a constant-valued coefficient at the position of the
2088 struct tgsi_exec_machine *mach,
2094 for( i = 0; i < QUAD_SIZE; i++ ) {
2095 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2100 * Evaluate a linear-valued coefficient at the position of the
2105 struct tgsi_exec_machine *mach,
2109 const float x = mach->QuadPos.xyzw[0].f[0];
2110 const float y = mach->QuadPos.xyzw[1].f[0];
2111 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2112 const float dady = mach->InterpCoefs[attrib].dady[chan];
2113 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2114 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2115 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2116 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2117 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2121 * Evaluate a perspective-valued coefficient at the position of the
2125 eval_perspective_coef(
2126 struct tgsi_exec_machine *mach,
2130 const float x = mach->QuadPos.xyzw[0].f[0];
2131 const float y = mach->QuadPos.xyzw[1].f[0];
2132 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2133 const float dady = mach->InterpCoefs[attrib].dady[chan];
2134 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2135 const float *w = mach->QuadPos.xyzw[3].f;
2136 /* divide by W here */
2137 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2138 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2139 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2140 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2144 typedef void (* eval_coef_func)(
2145 struct tgsi_exec_machine *mach,
2150 exec_declaration(struct tgsi_exec_machine *mach,
2151 const struct tgsi_full_declaration *decl)
2153 if (decl->Declaration.File == TGSI_FILE_RESOURCE) {
2154 mach->Resources[decl->Range.First] = decl->Resource;
2158 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2159 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2160 uint first, last, mask;
2162 first = decl->Range.First;
2163 last = decl->Range.Last;
2164 mask = decl->Declaration.UsageMask;
2166 /* XXX we could remove this special-case code since
2167 * mach->InterpCoefs[first].a0 should already have the
2168 * front/back-face value. But we should first update the
2169 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2170 * Then, we could remove the tgsi_exec_machine::Face field.
2172 /* XXX make FACE a system value */
2173 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2176 assert(decl->Semantic.Index == 0);
2177 assert(first == last);
2179 for (i = 0; i < QUAD_SIZE; i++) {
2180 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2183 eval_coef_func eval;
2186 switch (decl->Declaration.Interpolate) {
2187 case TGSI_INTERPOLATE_CONSTANT:
2188 eval = eval_constant_coef;
2191 case TGSI_INTERPOLATE_LINEAR:
2192 eval = eval_linear_coef;
2195 case TGSI_INTERPOLATE_PERSPECTIVE:
2196 eval = eval_perspective_coef;
2204 for (j = 0; j < NUM_CHANNELS; j++) {
2205 if (mask & (1 << j)) {
2206 for (i = first; i <= last; i++) {
2215 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2216 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2221 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2224 exec_vector(struct tgsi_exec_machine *mach,
2225 const struct tgsi_full_instruction *inst,
2227 enum tgsi_exec_datatype dst_datatype)
2231 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2232 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2233 union tgsi_exec_channel dst;
2236 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2241 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2242 const union tgsi_exec_channel *src);
2245 exec_scalar_unary(struct tgsi_exec_machine *mach,
2246 const struct tgsi_full_instruction *inst,
2248 enum tgsi_exec_datatype dst_datatype,
2249 enum tgsi_exec_datatype src_datatype)
2252 union tgsi_exec_channel src;
2253 union tgsi_exec_channel dst;
2255 fetch_source(mach, &src, &inst->Src[0], CHAN_X, src_datatype);
2257 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2258 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2259 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2265 exec_vector_unary(struct tgsi_exec_machine *mach,
2266 const struct tgsi_full_instruction *inst,
2268 enum tgsi_exec_datatype dst_datatype,
2269 enum tgsi_exec_datatype src_datatype)
2272 struct tgsi_exec_vector dst;
2274 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2275 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2276 union tgsi_exec_channel src;
2278 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2279 op(&dst.xyzw[chan], &src);
2282 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2283 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2284 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2289 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2290 const union tgsi_exec_channel *src0,
2291 const union tgsi_exec_channel *src1);
2294 exec_scalar_binary(struct tgsi_exec_machine *mach,
2295 const struct tgsi_full_instruction *inst,
2297 enum tgsi_exec_datatype dst_datatype,
2298 enum tgsi_exec_datatype src_datatype)
2301 union tgsi_exec_channel src[2];
2302 union tgsi_exec_channel dst;
2304 fetch_source(mach, &src[0], &inst->Src[0], CHAN_X, src_datatype);
2305 fetch_source(mach, &src[1], &inst->Src[1], CHAN_Y, src_datatype);
2306 op(&dst, &src[0], &src[1]);
2307 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2308 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2309 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2315 exec_vector_binary(struct tgsi_exec_machine *mach,
2316 const struct tgsi_full_instruction *inst,
2318 enum tgsi_exec_datatype dst_datatype,
2319 enum tgsi_exec_datatype src_datatype)
2322 struct tgsi_exec_vector dst;
2324 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2325 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2326 union tgsi_exec_channel src[2];
2328 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2329 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2330 op(&dst.xyzw[chan], &src[0], &src[1]);
2333 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2334 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2335 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2340 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2341 const union tgsi_exec_channel *src0,
2342 const union tgsi_exec_channel *src1,
2343 const union tgsi_exec_channel *src2);
2346 exec_vector_trinary(struct tgsi_exec_machine *mach,
2347 const struct tgsi_full_instruction *inst,
2348 micro_trinary_op op,
2349 enum tgsi_exec_datatype dst_datatype,
2350 enum tgsi_exec_datatype src_datatype)
2353 struct tgsi_exec_vector dst;
2355 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2356 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2357 union tgsi_exec_channel src[3];
2359 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2360 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2361 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2362 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2365 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2366 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2367 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2373 exec_dp3(struct tgsi_exec_machine *mach,
2374 const struct tgsi_full_instruction *inst)
2377 union tgsi_exec_channel arg[3];
2379 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2380 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2381 micro_mul(&arg[2], &arg[0], &arg[1]);
2383 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2384 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2385 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2386 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2389 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2390 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2391 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2397 exec_dp4(struct tgsi_exec_machine *mach,
2398 const struct tgsi_full_instruction *inst)
2401 union tgsi_exec_channel arg[3];
2403 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2404 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2405 micro_mul(&arg[2], &arg[0], &arg[1]);
2407 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2408 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2409 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2410 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2413 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2414 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2415 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2421 exec_dp2a(struct tgsi_exec_machine *mach,
2422 const struct tgsi_full_instruction *inst)
2425 union tgsi_exec_channel arg[3];
2427 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2428 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2429 micro_mul(&arg[2], &arg[0], &arg[1]);
2431 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2432 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2433 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2435 fetch_source(mach, &arg[1], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2436 micro_add(&arg[0], &arg[0], &arg[1]);
2438 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2439 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2440 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2446 exec_dph(struct tgsi_exec_machine *mach,
2447 const struct tgsi_full_instruction *inst)
2450 union tgsi_exec_channel arg[3];
2452 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2453 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2454 micro_mul(&arg[2], &arg[0], &arg[1]);
2456 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2457 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2458 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2460 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2461 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2462 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2464 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2465 micro_add(&arg[0], &arg[0], &arg[1]);
2467 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2468 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2469 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2475 exec_dp2(struct tgsi_exec_machine *mach,
2476 const struct tgsi_full_instruction *inst)
2479 union tgsi_exec_channel arg[3];
2481 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2482 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2483 micro_mul(&arg[2], &arg[0], &arg[1]);
2485 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2486 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2487 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2489 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2490 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2491 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2497 exec_nrm4(struct tgsi_exec_machine *mach,
2498 const struct tgsi_full_instruction *inst)
2501 union tgsi_exec_channel arg[4];
2502 union tgsi_exec_channel scale;
2504 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2505 micro_mul(&scale, &arg[0], &arg[0]);
2507 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2508 union tgsi_exec_channel product;
2510 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2511 micro_mul(&product, &arg[chan], &arg[chan]);
2512 micro_add(&scale, &scale, &product);
2515 micro_rsq(&scale, &scale);
2517 for (chan = CHAN_X; chan <= CHAN_W; chan++) {
2518 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2519 micro_mul(&arg[chan], &arg[chan], &scale);
2520 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2526 exec_nrm3(struct tgsi_exec_machine *mach,
2527 const struct tgsi_full_instruction *inst)
2529 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2531 union tgsi_exec_channel arg[3];
2532 union tgsi_exec_channel scale;
2534 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2535 micro_mul(&scale, &arg[0], &arg[0]);
2537 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2538 union tgsi_exec_channel product;
2540 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2541 micro_mul(&product, &arg[chan], &arg[chan]);
2542 micro_add(&scale, &scale, &product);
2545 micro_rsq(&scale, &scale);
2547 for (chan = CHAN_X; chan <= CHAN_Z; chan++) {
2548 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2549 micro_mul(&arg[chan], &arg[chan], &scale);
2550 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2555 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2556 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2561 exec_scs(struct tgsi_exec_machine *mach,
2562 const struct tgsi_full_instruction *inst)
2564 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2565 union tgsi_exec_channel arg;
2566 union tgsi_exec_channel result;
2568 fetch_source(mach, &arg, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2570 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2571 micro_cos(&result, &arg);
2572 store_dest(mach, &result, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2574 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2575 micro_sin(&result, &arg);
2576 store_dest(mach, &result, &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2579 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2580 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2582 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2583 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2588 exec_x2d(struct tgsi_exec_machine *mach,
2589 const struct tgsi_full_instruction *inst)
2591 union tgsi_exec_channel r[4];
2592 union tgsi_exec_channel d[2];
2594 fetch_source(mach, &r[0], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2595 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2596 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2597 fetch_source(mach, &r[2], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2598 micro_mul(&r[2], &r[2], &r[0]);
2599 fetch_source(mach, &r[3], &inst->Src[2], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2600 micro_mul(&r[3], &r[3], &r[1]);
2601 micro_add(&r[2], &r[2], &r[3]);
2602 fetch_source(mach, &r[3], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2603 micro_add(&d[0], &r[2], &r[3]);
2605 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2606 fetch_source(mach, &r[2], &inst->Src[2], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2607 micro_mul(&r[2], &r[2], &r[0]);
2608 fetch_source(mach, &r[3], &inst->Src[2], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2609 micro_mul(&r[3], &r[3], &r[1]);
2610 micro_add(&r[2], &r[2], &r[3]);
2611 fetch_source(mach, &r[3], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2612 micro_add(&d[1], &r[2], &r[3]);
2614 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2615 store_dest(mach, &d[0], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2617 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2618 store_dest(mach, &d[1], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2620 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2621 store_dest(mach, &d[0], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2623 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2624 store_dest(mach, &d[1], &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2629 exec_rfl(struct tgsi_exec_machine *mach,
2630 const struct tgsi_full_instruction *inst)
2632 union tgsi_exec_channel r[9];
2634 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2635 /* r0 = dp3(src0, src0) */
2636 fetch_source(mach, &r[2], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2637 micro_mul(&r[0], &r[2], &r[2]);
2638 fetch_source(mach, &r[4], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2639 micro_mul(&r[8], &r[4], &r[4]);
2640 micro_add(&r[0], &r[0], &r[8]);
2641 fetch_source(mach, &r[6], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2642 micro_mul(&r[8], &r[6], &r[6]);
2643 micro_add(&r[0], &r[0], &r[8]);
2645 /* r1 = dp3(src0, src1) */
2646 fetch_source(mach, &r[3], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2647 micro_mul(&r[1], &r[2], &r[3]);
2648 fetch_source(mach, &r[5], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2649 micro_mul(&r[8], &r[4], &r[5]);
2650 micro_add(&r[1], &r[1], &r[8]);
2651 fetch_source(mach, &r[7], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2652 micro_mul(&r[8], &r[6], &r[7]);
2653 micro_add(&r[1], &r[1], &r[8]);
2655 /* r1 = 2 * r1 / r0 */
2656 micro_add(&r[1], &r[1], &r[1]);
2657 micro_div(&r[1], &r[1], &r[0]);
2659 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2660 micro_mul(&r[2], &r[2], &r[1]);
2661 micro_sub(&r[2], &r[2], &r[3]);
2662 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2664 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2665 micro_mul(&r[4], &r[4], &r[1]);
2666 micro_sub(&r[4], &r[4], &r[5]);
2667 store_dest(mach, &r[4], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2669 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2670 micro_mul(&r[6], &r[6], &r[1]);
2671 micro_sub(&r[6], &r[6], &r[7]);
2672 store_dest(mach, &r[6], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2675 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2676 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2681 exec_xpd(struct tgsi_exec_machine *mach,
2682 const struct tgsi_full_instruction *inst)
2684 union tgsi_exec_channel r[6];
2685 union tgsi_exec_channel d[3];
2687 fetch_source(mach, &r[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2688 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2690 micro_mul(&r[2], &r[0], &r[1]);
2692 fetch_source(mach, &r[3], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2693 fetch_source(mach, &r[4], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2695 micro_mul(&r[5], &r[3], &r[4] );
2696 micro_sub(&d[CHAN_X], &r[2], &r[5]);
2698 fetch_source(mach, &r[2], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2700 micro_mul(&r[3], &r[3], &r[2]);
2702 fetch_source(mach, &r[5], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2704 micro_mul(&r[1], &r[1], &r[5]);
2705 micro_sub(&d[CHAN_Y], &r[3], &r[1]);
2707 micro_mul(&r[5], &r[5], &r[4]);
2708 micro_mul(&r[0], &r[0], &r[2]);
2709 micro_sub(&d[CHAN_Z], &r[5], &r[0]);
2711 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2712 store_dest(mach, &d[CHAN_X], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2714 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2715 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2717 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2718 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2720 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2721 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2726 exec_dst(struct tgsi_exec_machine *mach,
2727 const struct tgsi_full_instruction *inst)
2729 union tgsi_exec_channel r[2];
2730 union tgsi_exec_channel d[4];
2732 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2733 fetch_source(mach, &r[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2734 fetch_source(mach, &r[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2735 micro_mul(&d[CHAN_Y], &r[0], &r[1]);
2737 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2738 fetch_source(mach, &d[CHAN_Z], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2740 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2741 fetch_source(mach, &d[CHAN_W], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2744 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2745 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2747 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2748 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2750 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2751 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2753 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2754 store_dest(mach, &d[CHAN_W], &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2759 exec_log(struct tgsi_exec_machine *mach,
2760 const struct tgsi_full_instruction *inst)
2762 union tgsi_exec_channel r[3];
2764 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2765 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
2766 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
2767 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
2768 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2769 store_dest(mach, &r[0], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2771 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2772 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
2773 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
2774 store_dest(mach, &r[0], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2776 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2777 store_dest(mach, &r[1], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2779 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2780 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2785 exec_exp(struct tgsi_exec_machine *mach,
2786 const struct tgsi_full_instruction *inst)
2788 union tgsi_exec_channel r[3];
2790 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2791 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
2792 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2793 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
2794 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2796 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2797 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
2798 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2800 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2801 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
2802 store_dest(mach, &r[2], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2804 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2805 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2810 exec_lit(struct tgsi_exec_machine *mach,
2811 const struct tgsi_full_instruction *inst)
2813 union tgsi_exec_channel r[3];
2814 union tgsi_exec_channel d[3];
2816 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2817 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_X, TGSI_EXEC_DATA_FLOAT);
2819 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
2820 fetch_source(mach, &r[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2821 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2822 micro_max(&d[CHAN_Y], &r[0], &ZeroVec);
2823 store_dest(mach, &d[CHAN_Y], &inst->Dst[0], inst, CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2826 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2827 fetch_source(mach, &r[1], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2828 micro_max(&r[1], &r[1], &ZeroVec);
2830 fetch_source(mach, &r[2], &inst->Src[0], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2831 micro_min(&r[2], &r[2], &P128Vec);
2832 micro_max(&r[2], &r[2], &M128Vec);
2833 micro_pow(&r[1], &r[1], &r[2]);
2834 micro_lt(&d[CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
2835 store_dest(mach, &d[CHAN_Z], &inst->Dst[0], inst, CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2838 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2839 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2844 exec_break(struct tgsi_exec_machine *mach)
2846 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
2847 /* turn off loop channels for each enabled exec channel */
2848 mach->LoopMask &= ~mach->ExecMask;
2849 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2850 UPDATE_EXEC_MASK(mach);
2852 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
2854 mach->Switch.mask = 0x0;
2856 UPDATE_EXEC_MASK(mach);
2861 exec_switch(struct tgsi_exec_machine *mach,
2862 const struct tgsi_full_instruction *inst)
2864 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
2865 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
2867 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
2868 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2869 mach->Switch.mask = 0x0;
2870 mach->Switch.defaultMask = 0x0;
2872 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
2873 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
2875 UPDATE_EXEC_MASK(mach);
2879 exec_case(struct tgsi_exec_machine *mach,
2880 const struct tgsi_full_instruction *inst)
2882 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2883 union tgsi_exec_channel src;
2886 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2888 if (mach->Switch.selector.u[0] == src.u[0]) {
2891 if (mach->Switch.selector.u[1] == src.u[1]) {
2894 if (mach->Switch.selector.u[2] == src.u[2]) {
2897 if (mach->Switch.selector.u[3] == src.u[3]) {
2901 mach->Switch.defaultMask |= mask;
2903 mach->Switch.mask |= mask & prevMask;
2905 UPDATE_EXEC_MASK(mach);
2909 exec_default(struct tgsi_exec_machine *mach)
2911 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2913 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
2915 UPDATE_EXEC_MASK(mach);
2919 exec_endswitch(struct tgsi_exec_machine *mach)
2921 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
2922 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
2924 UPDATE_EXEC_MASK(mach);
2928 micro_i2f(union tgsi_exec_channel *dst,
2929 const union tgsi_exec_channel *src)
2931 dst->f[0] = (float)src->i[0];
2932 dst->f[1] = (float)src->i[1];
2933 dst->f[2] = (float)src->i[2];
2934 dst->f[3] = (float)src->i[3];
2938 micro_not(union tgsi_exec_channel *dst,
2939 const union tgsi_exec_channel *src)
2941 dst->u[0] = ~src->u[0];
2942 dst->u[1] = ~src->u[1];
2943 dst->u[2] = ~src->u[2];
2944 dst->u[3] = ~src->u[3];
2948 micro_shl(union tgsi_exec_channel *dst,
2949 const union tgsi_exec_channel *src0,
2950 const union tgsi_exec_channel *src1)
2952 dst->u[0] = src0->u[0] << src1->u[0];
2953 dst->u[1] = src0->u[1] << src1->u[1];
2954 dst->u[2] = src0->u[2] << src1->u[2];
2955 dst->u[3] = src0->u[3] << src1->u[3];
2959 micro_and(union tgsi_exec_channel *dst,
2960 const union tgsi_exec_channel *src0,
2961 const union tgsi_exec_channel *src1)
2963 dst->u[0] = src0->u[0] & src1->u[0];
2964 dst->u[1] = src0->u[1] & src1->u[1];
2965 dst->u[2] = src0->u[2] & src1->u[2];
2966 dst->u[3] = src0->u[3] & src1->u[3];
2970 micro_or(union tgsi_exec_channel *dst,
2971 const union tgsi_exec_channel *src0,
2972 const union tgsi_exec_channel *src1)
2974 dst->u[0] = src0->u[0] | src1->u[0];
2975 dst->u[1] = src0->u[1] | src1->u[1];
2976 dst->u[2] = src0->u[2] | src1->u[2];
2977 dst->u[3] = src0->u[3] | src1->u[3];
2981 micro_xor(union tgsi_exec_channel *dst,
2982 const union tgsi_exec_channel *src0,
2983 const union tgsi_exec_channel *src1)
2985 dst->u[0] = src0->u[0] ^ src1->u[0];
2986 dst->u[1] = src0->u[1] ^ src1->u[1];
2987 dst->u[2] = src0->u[2] ^ src1->u[2];
2988 dst->u[3] = src0->u[3] ^ src1->u[3];
2992 micro_mod(union tgsi_exec_channel *dst,
2993 const union tgsi_exec_channel *src0,
2994 const union tgsi_exec_channel *src1)
2996 dst->i[0] = src0->i[0] % src1->i[0];
2997 dst->i[1] = src0->i[1] % src1->i[1];
2998 dst->i[2] = src0->i[2] % src1->i[2];
2999 dst->i[3] = src0->i[3] % src1->i[3];
3003 micro_f2i(union tgsi_exec_channel *dst,
3004 const union tgsi_exec_channel *src)
3006 dst->i[0] = (int)src->f[0];
3007 dst->i[1] = (int)src->f[1];
3008 dst->i[2] = (int)src->f[2];
3009 dst->i[3] = (int)src->f[3];
3013 micro_idiv(union tgsi_exec_channel *dst,
3014 const union tgsi_exec_channel *src0,
3015 const union tgsi_exec_channel *src1)
3017 dst->i[0] = src0->i[0] / src1->i[0];
3018 dst->i[1] = src0->i[1] / src1->i[1];
3019 dst->i[2] = src0->i[2] / src1->i[2];
3020 dst->i[3] = src0->i[3] / src1->i[3];
3024 micro_imax(union tgsi_exec_channel *dst,
3025 const union tgsi_exec_channel *src0,
3026 const union tgsi_exec_channel *src1)
3028 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3029 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3030 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3031 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3035 micro_imin(union tgsi_exec_channel *dst,
3036 const union tgsi_exec_channel *src0,
3037 const union tgsi_exec_channel *src1)
3039 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3040 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3041 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3042 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3046 micro_isge(union tgsi_exec_channel *dst,
3047 const union tgsi_exec_channel *src0,
3048 const union tgsi_exec_channel *src1)
3050 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3051 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3052 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3053 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3057 micro_ishr(union tgsi_exec_channel *dst,
3058 const union tgsi_exec_channel *src0,
3059 const union tgsi_exec_channel *src1)
3061 dst->i[0] = src0->i[0] >> src1->i[0];
3062 dst->i[1] = src0->i[1] >> src1->i[1];
3063 dst->i[2] = src0->i[2] >> src1->i[2];
3064 dst->i[3] = src0->i[3] >> src1->i[3];
3068 micro_islt(union tgsi_exec_channel *dst,
3069 const union tgsi_exec_channel *src0,
3070 const union tgsi_exec_channel *src1)
3072 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3073 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3074 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3075 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3079 micro_f2u(union tgsi_exec_channel *dst,
3080 const union tgsi_exec_channel *src)
3082 dst->u[0] = (uint)src->f[0];
3083 dst->u[1] = (uint)src->f[1];
3084 dst->u[2] = (uint)src->f[2];
3085 dst->u[3] = (uint)src->f[3];
3089 micro_u2f(union tgsi_exec_channel *dst,
3090 const union tgsi_exec_channel *src)
3092 dst->f[0] = (float)src->u[0];
3093 dst->f[1] = (float)src->u[1];
3094 dst->f[2] = (float)src->u[2];
3095 dst->f[3] = (float)src->u[3];
3099 micro_uadd(union tgsi_exec_channel *dst,
3100 const union tgsi_exec_channel *src0,
3101 const union tgsi_exec_channel *src1)
3103 dst->u[0] = src0->u[0] + src1->u[0];
3104 dst->u[1] = src0->u[1] + src1->u[1];
3105 dst->u[2] = src0->u[2] + src1->u[2];
3106 dst->u[3] = src0->u[3] + src1->u[3];
3110 micro_udiv(union tgsi_exec_channel *dst,
3111 const union tgsi_exec_channel *src0,
3112 const union tgsi_exec_channel *src1)
3114 dst->u[0] = src0->u[0] / src1->u[0];
3115 dst->u[1] = src0->u[1] / src1->u[1];
3116 dst->u[2] = src0->u[2] / src1->u[2];
3117 dst->u[3] = src0->u[3] / src1->u[3];
3121 micro_umad(union tgsi_exec_channel *dst,
3122 const union tgsi_exec_channel *src0,
3123 const union tgsi_exec_channel *src1,
3124 const union tgsi_exec_channel *src2)
3126 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3127 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3128 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3129 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3133 micro_umax(union tgsi_exec_channel *dst,
3134 const union tgsi_exec_channel *src0,
3135 const union tgsi_exec_channel *src1)
3137 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3138 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3139 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3140 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3144 micro_umin(union tgsi_exec_channel *dst,
3145 const union tgsi_exec_channel *src0,
3146 const union tgsi_exec_channel *src1)
3148 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3149 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3150 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3151 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3155 micro_umod(union tgsi_exec_channel *dst,
3156 const union tgsi_exec_channel *src0,
3157 const union tgsi_exec_channel *src1)
3159 dst->u[0] = src0->u[0] % src1->u[0];
3160 dst->u[1] = src0->u[1] % src1->u[1];
3161 dst->u[2] = src0->u[2] % src1->u[2];
3162 dst->u[3] = src0->u[3] % src1->u[3];
3166 micro_umul(union tgsi_exec_channel *dst,
3167 const union tgsi_exec_channel *src0,
3168 const union tgsi_exec_channel *src1)
3170 dst->u[0] = src0->u[0] * src1->u[0];
3171 dst->u[1] = src0->u[1] * src1->u[1];
3172 dst->u[2] = src0->u[2] * src1->u[2];
3173 dst->u[3] = src0->u[3] * src1->u[3];
3177 micro_useq(union tgsi_exec_channel *dst,
3178 const union tgsi_exec_channel *src0,
3179 const union tgsi_exec_channel *src1)
3181 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3182 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3183 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3184 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3188 micro_usge(union tgsi_exec_channel *dst,
3189 const union tgsi_exec_channel *src0,
3190 const union tgsi_exec_channel *src1)
3192 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3193 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3194 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3195 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3199 micro_ushr(union tgsi_exec_channel *dst,
3200 const union tgsi_exec_channel *src0,
3201 const union tgsi_exec_channel *src1)
3203 dst->u[0] = src0->u[0] >> src1->u[0];
3204 dst->u[1] = src0->u[1] >> src1->u[1];
3205 dst->u[2] = src0->u[2] >> src1->u[2];
3206 dst->u[3] = src0->u[3] >> src1->u[3];
3210 micro_uslt(union tgsi_exec_channel *dst,
3211 const union tgsi_exec_channel *src0,
3212 const union tgsi_exec_channel *src1)
3214 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3215 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3216 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3217 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3221 micro_usne(union tgsi_exec_channel *dst,
3222 const union tgsi_exec_channel *src0,
3223 const union tgsi_exec_channel *src1)
3225 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3226 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3227 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3228 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3233 struct tgsi_exec_machine *mach,
3234 const struct tgsi_full_instruction *inst,
3237 union tgsi_exec_channel r[10];
3241 switch (inst->Instruction.Opcode) {
3242 case TGSI_OPCODE_ARL:
3243 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3246 case TGSI_OPCODE_MOV:
3247 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3250 case TGSI_OPCODE_LIT:
3251 exec_lit(mach, inst);
3254 case TGSI_OPCODE_RCP:
3255 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3258 case TGSI_OPCODE_RSQ:
3259 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3262 case TGSI_OPCODE_EXP:
3263 exec_exp(mach, inst);
3266 case TGSI_OPCODE_LOG:
3267 exec_log(mach, inst);
3270 case TGSI_OPCODE_MUL:
3271 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3274 case TGSI_OPCODE_ADD:
3275 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3278 case TGSI_OPCODE_DP3:
3279 exec_dp3(mach, inst);
3282 case TGSI_OPCODE_DP4:
3283 exec_dp4(mach, inst);
3286 case TGSI_OPCODE_DST:
3287 exec_dst(mach, inst);
3290 case TGSI_OPCODE_MIN:
3291 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3294 case TGSI_OPCODE_MAX:
3295 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3298 case TGSI_OPCODE_SLT:
3299 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3302 case TGSI_OPCODE_SGE:
3303 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3306 case TGSI_OPCODE_MAD:
3307 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3310 case TGSI_OPCODE_SUB:
3311 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3314 case TGSI_OPCODE_LRP:
3315 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3318 case TGSI_OPCODE_CND:
3319 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3322 case TGSI_OPCODE_DP2A:
3323 exec_dp2a(mach, inst);
3326 case TGSI_OPCODE_FRC:
3327 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3330 case TGSI_OPCODE_CLAMP:
3331 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3334 case TGSI_OPCODE_FLR:
3335 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3338 case TGSI_OPCODE_ROUND:
3339 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3342 case TGSI_OPCODE_EX2:
3343 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3346 case TGSI_OPCODE_LG2:
3347 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3350 case TGSI_OPCODE_POW:
3351 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3354 case TGSI_OPCODE_XPD:
3355 exec_xpd(mach, inst);
3358 case TGSI_OPCODE_ABS:
3359 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3362 case TGSI_OPCODE_RCC:
3363 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3366 case TGSI_OPCODE_DPH:
3367 exec_dph(mach, inst);
3370 case TGSI_OPCODE_COS:
3371 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3374 case TGSI_OPCODE_DDX:
3375 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3378 case TGSI_OPCODE_DDY:
3379 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3382 case TGSI_OPCODE_KILP:
3383 exec_kilp (mach, inst);
3386 case TGSI_OPCODE_KIL:
3387 exec_kil (mach, inst);
3390 case TGSI_OPCODE_PK2H:
3394 case TGSI_OPCODE_PK2US:
3398 case TGSI_OPCODE_PK4B:
3402 case TGSI_OPCODE_PK4UB:
3406 case TGSI_OPCODE_RFL:
3407 exec_rfl(mach, inst);
3410 case TGSI_OPCODE_SEQ:
3411 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3414 case TGSI_OPCODE_SFL:
3415 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3418 case TGSI_OPCODE_SGT:
3419 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3422 case TGSI_OPCODE_SIN:
3423 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3426 case TGSI_OPCODE_SLE:
3427 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3430 case TGSI_OPCODE_SNE:
3431 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3434 case TGSI_OPCODE_STR:
3435 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3438 case TGSI_OPCODE_TEX:
3439 /* simple texture lookup */
3440 /* src[0] = texcoord */
3441 /* src[1] = sampler unit */
3442 exec_tex(mach, inst, TEX_MODIFIER_NONE);
3445 case TGSI_OPCODE_TXB:
3446 /* Texture lookup with lod bias */
3447 /* src[0] = texcoord (src[0].w = LOD bias) */
3448 /* src[1] = sampler unit */
3449 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS);
3452 case TGSI_OPCODE_TXD:
3453 /* Texture lookup with explict partial derivatives */
3454 /* src[0] = texcoord */
3455 /* src[1] = d[strq]/dx */
3456 /* src[2] = d[strq]/dy */
3457 /* src[3] = sampler unit */
3458 exec_txd(mach, inst);
3461 case TGSI_OPCODE_TXL:
3462 /* Texture lookup with explit LOD */
3463 /* src[0] = texcoord (src[0].w = LOD) */
3464 /* src[1] = sampler unit */
3465 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
3468 case TGSI_OPCODE_TXP:
3469 /* Texture lookup with projection */
3470 /* src[0] = texcoord (src[0].w = projection) */
3471 /* src[1] = sampler unit */
3472 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED);
3475 case TGSI_OPCODE_UP2H:
3479 case TGSI_OPCODE_UP2US:
3483 case TGSI_OPCODE_UP4B:
3487 case TGSI_OPCODE_UP4UB:
3491 case TGSI_OPCODE_X2D:
3492 exec_x2d(mach, inst);
3495 case TGSI_OPCODE_ARA:
3499 case TGSI_OPCODE_ARR:
3500 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3503 case TGSI_OPCODE_BRA:
3507 case TGSI_OPCODE_CAL:
3508 /* skip the call if no execution channels are enabled */
3509 if (mach->ExecMask) {
3512 /* First, record the depths of the execution stacks.
3513 * This is important for deeply nested/looped return statements.
3514 * We have to unwind the stacks by the correct amount. For a
3515 * real code generator, we could determine the number of entries
3516 * to pop off each stack with simple static analysis and avoid
3517 * implementing this data structure at run time.
3519 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3520 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3521 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3522 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3523 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3524 /* note that PC was already incremented above */
3525 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3527 mach->CallStackTop++;
3529 /* Second, push the Cond, Loop, Cont, Func stacks */
3530 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3531 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3532 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3533 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3534 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3535 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3537 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3538 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3539 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3540 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3541 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3542 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3544 /* Finally, jump to the subroutine */
3545 *pc = inst->Label.Label;
3549 case TGSI_OPCODE_RET:
3550 mach->FuncMask &= ~mach->ExecMask;
3551 UPDATE_EXEC_MASK(mach);
3553 if (mach->FuncMask == 0x0) {
3554 /* really return now (otherwise, keep executing */
3556 if (mach->CallStackTop == 0) {
3557 /* returning from main() */
3558 mach->CondStackTop = 0;
3559 mach->LoopStackTop = 0;
3564 assert(mach->CallStackTop > 0);
3565 mach->CallStackTop--;
3567 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3568 mach->CondMask = mach->CondStack[mach->CondStackTop];
3570 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3571 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3573 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3574 mach->ContMask = mach->ContStack[mach->ContStackTop];
3576 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3577 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3579 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3580 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3582 assert(mach->FuncStackTop > 0);
3583 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3585 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3587 UPDATE_EXEC_MASK(mach);
3591 case TGSI_OPCODE_SSG:
3592 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3595 case TGSI_OPCODE_CMP:
3596 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3599 case TGSI_OPCODE_SCS:
3600 exec_scs(mach, inst);
3603 case TGSI_OPCODE_NRM:
3604 exec_nrm3(mach, inst);
3607 case TGSI_OPCODE_NRM4:
3608 exec_nrm4(mach, inst);
3611 case TGSI_OPCODE_DIV:
3612 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3615 case TGSI_OPCODE_DP2:
3616 exec_dp2(mach, inst);
3619 case TGSI_OPCODE_IF:
3621 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3622 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3623 FETCH( &r[0], 0, CHAN_X );
3624 /* update CondMask */
3626 mach->CondMask &= ~0x1;
3629 mach->CondMask &= ~0x2;
3632 mach->CondMask &= ~0x4;
3635 mach->CondMask &= ~0x8;
3637 UPDATE_EXEC_MASK(mach);
3638 /* Todo: If CondMask==0, jump to ELSE */
3641 case TGSI_OPCODE_ELSE:
3642 /* invert CondMask wrt previous mask */
3645 assert(mach->CondStackTop > 0);
3646 prevMask = mach->CondStack[mach->CondStackTop - 1];
3647 mach->CondMask = ~mach->CondMask & prevMask;
3648 UPDATE_EXEC_MASK(mach);
3649 /* Todo: If CondMask==0, jump to ENDIF */
3653 case TGSI_OPCODE_ENDIF:
3655 assert(mach->CondStackTop > 0);
3656 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3657 UPDATE_EXEC_MASK(mach);
3660 case TGSI_OPCODE_END:
3661 /* make sure we end primitives which haven't
3662 * been explicitly emitted */
3663 conditional_emit_primitive(mach);
3664 /* halt execution */
3668 case TGSI_OPCODE_PUSHA:
3672 case TGSI_OPCODE_POPA:
3676 case TGSI_OPCODE_CEIL:
3677 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3680 case TGSI_OPCODE_I2F:
3681 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3684 case TGSI_OPCODE_NOT:
3685 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3688 case TGSI_OPCODE_TRUNC:
3689 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3692 case TGSI_OPCODE_SHL:
3693 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3696 case TGSI_OPCODE_AND:
3697 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3700 case TGSI_OPCODE_OR:
3701 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3704 case TGSI_OPCODE_MOD:
3705 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3708 case TGSI_OPCODE_XOR:
3709 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3712 case TGSI_OPCODE_SAD:
3716 case TGSI_OPCODE_TXF:
3720 case TGSI_OPCODE_TXQ:
3724 case TGSI_OPCODE_EMIT:
3728 case TGSI_OPCODE_ENDPRIM:
3729 emit_primitive(mach);
3732 case TGSI_OPCODE_BGNLOOP:
3733 /* push LoopMask and ContMasks */
3734 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3735 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3736 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3737 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3739 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3740 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3741 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3742 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3743 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
3746 case TGSI_OPCODE_ENDLOOP:
3747 /* Restore ContMask, but don't pop */
3748 assert(mach->ContStackTop > 0);
3749 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3750 UPDATE_EXEC_MASK(mach);
3751 if (mach->ExecMask) {
3752 /* repeat loop: jump to instruction just past BGNLOOP */
3753 assert(mach->LoopLabelStackTop > 0);
3754 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3757 /* exit loop: pop LoopMask */
3758 assert(mach->LoopStackTop > 0);
3759 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3761 assert(mach->ContStackTop > 0);
3762 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3763 assert(mach->LoopLabelStackTop > 0);
3764 --mach->LoopLabelStackTop;
3766 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3768 UPDATE_EXEC_MASK(mach);
3771 case TGSI_OPCODE_BRK:
3775 case TGSI_OPCODE_CONT:
3776 /* turn off cont channels for each enabled exec channel */
3777 mach->ContMask &= ~mach->ExecMask;
3778 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3779 UPDATE_EXEC_MASK(mach);
3782 case TGSI_OPCODE_BGNSUB:
3786 case TGSI_OPCODE_ENDSUB:
3788 * XXX: This really should be a no-op. We should never reach this opcode.
3791 assert(mach->CallStackTop > 0);
3792 mach->CallStackTop--;
3794 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3795 mach->CondMask = mach->CondStack[mach->CondStackTop];
3797 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3798 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3800 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3801 mach->ContMask = mach->ContStack[mach->ContStackTop];
3803 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3804 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3806 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3807 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3809 assert(mach->FuncStackTop > 0);
3810 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3812 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3814 UPDATE_EXEC_MASK(mach);
3817 case TGSI_OPCODE_NOP:
3820 case TGSI_OPCODE_BREAKC:
3821 FETCH(&r[0], 0, CHAN_X);
3822 /* update CondMask */
3823 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
3824 mach->LoopMask &= ~0x1;
3826 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
3827 mach->LoopMask &= ~0x2;
3829 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
3830 mach->LoopMask &= ~0x4;
3832 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
3833 mach->LoopMask &= ~0x8;
3835 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3836 UPDATE_EXEC_MASK(mach);
3839 case TGSI_OPCODE_F2I:
3840 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3843 case TGSI_OPCODE_IDIV:
3844 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3847 case TGSI_OPCODE_IMAX:
3848 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3851 case TGSI_OPCODE_IMIN:
3852 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3855 case TGSI_OPCODE_INEG:
3856 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3859 case TGSI_OPCODE_ISGE:
3860 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3863 case TGSI_OPCODE_ISHR:
3864 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3867 case TGSI_OPCODE_ISLT:
3868 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3871 case TGSI_OPCODE_F2U:
3872 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3875 case TGSI_OPCODE_U2F:
3876 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
3879 case TGSI_OPCODE_UADD:
3880 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3883 case TGSI_OPCODE_UDIV:
3884 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3887 case TGSI_OPCODE_UMAD:
3888 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3891 case TGSI_OPCODE_UMAX:
3892 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3895 case TGSI_OPCODE_UMIN:
3896 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3899 case TGSI_OPCODE_UMOD:
3900 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3903 case TGSI_OPCODE_UMUL:
3904 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3907 case TGSI_OPCODE_USEQ:
3908 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3911 case TGSI_OPCODE_USGE:
3912 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3915 case TGSI_OPCODE_USHR:
3916 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3919 case TGSI_OPCODE_USLT:
3920 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3923 case TGSI_OPCODE_USNE:
3924 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3927 case TGSI_OPCODE_SWITCH:
3928 exec_switch(mach, inst);
3931 case TGSI_OPCODE_CASE:
3932 exec_case(mach, inst);
3935 case TGSI_OPCODE_DEFAULT:
3939 case TGSI_OPCODE_ENDSWITCH:
3940 exec_endswitch(mach);
3943 case TGSI_OPCODE_LOAD:
3947 case TGSI_OPCODE_LOAD_MS:
3951 case TGSI_OPCODE_SAMPLE:
3952 exec_sample(mach, inst, TEX_MODIFIER_NONE);
3955 case TGSI_OPCODE_SAMPLE_B:
3956 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS);
3959 case TGSI_OPCODE_SAMPLE_C:
3960 exec_sample(mach, inst, TEX_MODIFIER_NONE);
3963 case TGSI_OPCODE_SAMPLE_C_LZ:
3964 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS);
3967 case TGSI_OPCODE_SAMPLE_D:
3968 exec_sample_d(mach, inst);
3971 case TGSI_OPCODE_SAMPLE_L:
3972 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
3975 case TGSI_OPCODE_GATHER4:
3979 case TGSI_OPCODE_RESINFO:
3983 case TGSI_OPCODE_SAMPLE_POS:
3987 case TGSI_OPCODE_SAMPLE_INFO:
3997 #define DEBUG_EXECUTION 0
4001 * Run TGSI interpreter.
4002 * \return bitmask of "alive" quad components
4005 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4010 mach->CondMask = 0xf;
4011 mach->LoopMask = 0xf;
4012 mach->ContMask = 0xf;
4013 mach->FuncMask = 0xf;
4014 mach->ExecMask = 0xf;
4016 mach->Switch.mask = 0xf;
4018 assert(mach->CondStackTop == 0);
4019 assert(mach->LoopStackTop == 0);
4020 assert(mach->ContStackTop == 0);
4021 assert(mach->SwitchStackTop == 0);
4022 assert(mach->BreakStackTop == 0);
4023 assert(mach->CallStackTop == 0);
4025 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4026 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4028 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4029 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4030 mach->Primitives[0] = 0;
4033 /* execute declarations (interpolants) */
4034 for (i = 0; i < mach->NumDeclarations; i++) {
4035 exec_declaration( mach, mach->Declarations+i );
4040 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4041 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4044 memcpy(temps, mach->Temps, sizeof(temps));
4045 memcpy(outputs, mach->Outputs, sizeof(outputs));
4048 /* execute instructions, until pc is set to -1 */
4054 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4057 assert(pc < (int) mach->NumInstructions);
4058 exec_instruction(mach, mach->Instructions + pc, &pc);
4061 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4062 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4065 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4066 debug_printf("TEMP[%2u] = ", i);
4067 for (j = 0; j < 4; j++) {
4071 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4072 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4073 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4074 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4075 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4079 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4080 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4083 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4084 debug_printf("OUT[%2u] = ", i);
4085 for (j = 0; j < 4; j++) {
4089 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4090 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4091 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4092 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4093 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4102 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4103 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4105 * Scale back depth component.
4107 for (i = 0; i < 4; i++)
4108 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4112 /* Strictly speaking, these assertions aren't really needed but they
4113 * can potentially catch some bugs in the control flow code.
4115 assert(mach->CondStackTop == 0);
4116 assert(mach->LoopStackTop == 0);
4117 assert(mach->ContStackTop == 0);
4118 assert(mach->SwitchStackTop == 0);
4119 assert(mach->BreakStackTop == 0);
4120 assert(mach->CallStackTop == 0);
4122 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];