src/drm/cairo-drm-intel-private.h

   1 /* Cairo - a vector graphics library with display and print output
   2  *
   3  * Copyright © 2009 Chris Wilson
   4  *
   5  * This library is free software; you can redistribute it and/or
   6  * modify it either under the terms of the GNU Lesser General Public
   7  * License version 2.1 as published by the Free Software Foundation
   8  * (the "LGPL") or, at your option, under the terms of the Mozilla
   9  * Public License Version 1.1 (the "MPL"). If you do not alter this
  10  * notice, a recipient may use your version of this file under either
  11  * the MPL or the LGPL.
  12  *
  13  * You should have received a copy of the LGPL along with this library
  14  * in the file COPYING-LGPL-2.1; if not, write to the Free Software
  15  * Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA
  16  * You should have received a copy of the MPL along with this library
  17  * in the file COPYING-MPL-1.1
  18  *
  19  * The contents of this file are subject to the Mozilla Public License
  20  * Version 1.1 (the "License"); you may not use this file except in
  21  * compliance with the License. You may obtain a copy of the License at
  22  * http://www.mozilla.org/MPL/
  23  *
  24  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY
  25  * OF ANY KIND, either express or implied. See the LGPL or the MPL for
  26  * the specific language governing rights and limitations.
  27  *
  28  */
  29
  30 #ifndef CAIRO_DRM_INTEL_PRIVATE_H
  31 #define CAIRO_DRM_INTEL_PRIVATE_H
  32
  33 #include "cairoint.h"
  34 #include "cairo-cache-private.h"
  35 #include "cairo-compiler-private.h"
  36 #include "cairo-drm-private.h"
  37 #include "cairo-freelist-private.h"
  38 #include "cairo-list-private.h"
  39 #include "cairo-mutex-private.h"
  40 #include "cairo-rtree-private.h"
  41 #include "cairo-types-private.h"
  42
  43 #include "cairo-drm-intel-ioctl-private.h"
  44
  45 #define INTEL_TILING_DEFAULT I915_TILING_Y
  46
  47 #define INTEL_BO_CACHE_BUCKETS 12 /* cache surfaces up to 16 MiB */
  48
  49 #define INTEL_GLYPH_CACHE_WIDTH 1024
  50 #define INTEL_GLYPH_CACHE_HEIGHT 1024
  51 #define INTEL_GLYPH_CACHE_MIN_SIZE 1
  52 #define INTEL_GLYPH_CACHE_MAX_SIZE 128
  53
  54 typedef struct _intel_bo {
  55     cairo_drm_bo_t base;
  56
  57     cairo_list_t link;
  58     cairo_list_t cache_list;
  59
  60     uint32_t offset;
  61     uint32_t batch_read_domains;
  62     uint32_t batch_write_domain;
  63
  64     uint32_t opaque0;
  65     uint32_t opaque1;
  66
  67     uint32_t full_size;
  68     uint16_t stride;
  69     uint16_t _stride;
  70     uint32_t tiling :4;
  71     uint32_t _tiling :4;
  72     uint32_t purgeable :1;
  73     uint32_t busy :1;
  74     uint32_t cpu :1;
  75
  76     struct drm_i915_gem_exec_object2 *exec;
  77     void *virtual;
  78 } intel_bo_t;
  79
  80 #define INTEL_BATCH_SIZE (64*1024)
  81 #define INTEL_VERTEX_BUFFER_SIZE (512*1024)
  82 #define INTEL_MAX_RELOCS 2048
  83
  84 static inline void
  85 intel_bo_mark_purgeable (intel_bo_t *bo)
  86 {
  87     if (bo->base.name == 0)
  88         bo->purgeable = 1;
  89 }
  90
  91 typedef struct _intel_vertex_buffer intel_vertex_buffer_t;
  92
  93 typedef void (*intel_vertex_buffer_new_func_t) (intel_vertex_buffer_t *vertex_buffer);
  94 typedef void (*intel_vertex_buffer_start_rectangles_func_t) (intel_vertex_buffer_t *vertex_buffer,
  95                                                              uint32_t floats_per_vertex);
  96 typedef void (*intel_vertex_buffer_flush_func_t) (intel_vertex_buffer_t *vertex_buffer);
  97 typedef void (*intel_vertex_buffer_finish_func_t) (intel_vertex_buffer_t *vertex_buffer);
  98
  99 struct _intel_vertex_buffer {
 100     uint32_t vbo_batch; /* reloc position in batch, 0 -> not yet allocated */
 101     uint32_t vbo_offset;
 102     uint32_t vbo_used;
 103
 104     uint32_t vertex_index;
 105     uint32_t vertex_count;
 106
 107     uint32_t floats_per_vertex;
 108     uint32_t rectangle_size;
 109
 110     intel_bo_t *last_vbo;
 111     uint32_t last_vbo_offset;
 112     uint32_t last_vbo_space;
 113
 114     intel_vertex_buffer_new_func_t new;
 115     intel_vertex_buffer_start_rectangles_func_t start_rectangles;
 116     intel_vertex_buffer_flush_func_t flush;
 117     intel_vertex_buffer_finish_func_t finish;
 118
 119     uint32_t base[INTEL_VERTEX_BUFFER_SIZE / sizeof (uint32_t)];
 120 };
 121
 122 typedef struct _intel_batch intel_batch_t;
 123
 124 typedef void (*intel_batch_commit_func_t) (intel_batch_t *batch);
 125 typedef void (*intel_batch_reset_func_t) (intel_batch_t *batch);
 126
 127 struct _intel_batch {
 128     size_t gtt_size;
 129     size_t gtt_avail_size;
 130
 131     intel_batch_commit_func_t commit;
 132     intel_batch_reset_func_t reset;
 133
 134     uint16_t exec_count;
 135     uint16_t reloc_count;
 136     uint16_t used;
 137     uint16_t header;
 138
 139     intel_bo_t *target_bo[INTEL_MAX_RELOCS];
 140     struct drm_i915_gem_exec_object2 exec[INTEL_MAX_RELOCS];
 141     struct drm_i915_gem_relocation_entry reloc[INTEL_MAX_RELOCS];
 142
 143     uint32_t base[INTEL_BATCH_SIZE / sizeof (uint32_t)];
 144
 145     intel_vertex_buffer_t vertex_buffer;
 146 };
 147
 148 typedef struct _intel_buffer {
 149     intel_bo_t *bo;
 150     uint32_t offset;
 151     cairo_format_t format;
 152     uint32_t map0, map1;
 153     uint32_t width;
 154     uint32_t height;
 155     uint32_t stride;
 156 } intel_buffer_t;
 157
 158 typedef struct _intel_buffer_cache {
 159     int ref_count;
 160     intel_buffer_t buffer;
 161     cairo_rtree_t rtree;
 162     cairo_list_t link;
 163 } intel_buffer_cache_t;
 164
 165 typedef struct _intel_glyph {
 166     cairo_rtree_node_t node;
 167     intel_buffer_cache_t *cache;
 168     void **owner;
 169     float texcoord[3];
 170     int width, height;
 171 } intel_glyph_t;
 172
 173 typedef struct _intel_gradient_cache {
 174     cairo_pattern_union_t pattern;
 175     intel_buffer_t buffer;
 176 } intel_gradient_cache_t;
 177 #define GRADIENT_CACHE_SIZE 16
 178
 179 typedef struct _intel_surface {
 180     cairo_drm_surface_t drm;
 181
 182     cairo_cache_entry_t snapshot_cache_entry;
 183 } intel_surface_t;
 184
 185 typedef void (*intel_reset_context_func_t) (void *device);
 186
 187 typedef struct _intel_device {
 188     cairo_drm_device_t base;
 189
 190     size_t gtt_max_size;
 191     size_t gtt_avail_size;
 192
 193     cairo_freepool_t bo_pool;
 194     cairo_list_t bo_in_flight;
 195
 196     cairo_mutex_t mutex;
 197     intel_batch_t batch;
 198
 199     intel_buffer_cache_t glyph_cache[2];
 200     cairo_list_t fonts;
 201
 202     struct {
 203         intel_gradient_cache_t cache[GRADIENT_CACHE_SIZE];
 204         unsigned int size;
 205     } gradient_cache;
 206
 207     cairo_cache_t snapshot_cache;
 208     size_t snapshot_cache_max_size;
 209
 210     intel_reset_context_func_t reset_context;
 211
 212     cairo_status_t (*flush) (struct _intel_device *);
 213 } intel_device_t;
 214
 215 static inline intel_device_t *
 216 to_intel_device (cairo_device_t *base)
 217 {
 218     return (intel_device_t *) base;
 219 }
 220
 221 static inline intel_bo_t *
 222 to_intel_bo (cairo_drm_bo_t *base)
 223 {
 224     return (intel_bo_t *) base;
 225 }
 226
 227 static inline intel_bo_t *
 228 intel_bo_reference (intel_bo_t *bo)
 229 {
 230     return to_intel_bo (cairo_drm_bo_reference (&bo->base));
 231 }
 232
 233 cairo_private cairo_bool_t
 234 intel_bo_madvise (intel_device_t *device, intel_bo_t *bo, int madv);
 235
 236 static cairo_always_inline void
 237 intel_bo_destroy (intel_device_t *device, intel_bo_t *bo)
 238 {
 239     cairo_drm_bo_destroy (&device->base.base, &bo->base);
 240 }
 241
 242 static inline void
 243 intel_bo_in_flight_add (intel_device_t *device,
 244                         intel_bo_t *bo)
 245 {
 246     if (bo->base.name == 0 && bo->exec != NULL && cairo_list_is_empty (&bo->cache_list))
 247         cairo_list_add (&bo->cache_list, &device->bo_in_flight);
 248 }
 249
 250 cairo_private int
 251 intel_get (int fd, int param);
 252
 253 cairo_private cairo_bool_t
 254 intel_info (int fd, uint64_t *gtt_size);
 255
 256 cairo_private cairo_status_t
 257 intel_device_init (intel_device_t *device, int fd);
 258
 259 cairo_private void
 260 intel_device_fini (intel_device_t *dev);
 261
 262 cairo_private intel_bo_t *
 263 intel_bo_create (intel_device_t *dev,
 264                  uint32_t max_size,
 265                  uint32_t real_size,
 266                  cairo_bool_t gpu_target,
 267                  uint32_t tiling,
 268                  uint32_t stride);
 269
 270 cairo_private intel_bo_t *
 271 intel_bo_create_for_name (intel_device_t *dev, uint32_t name);
 272
 273 cairo_private void
 274 intel_bo_set_tiling (const intel_device_t *dev,
 275                      intel_bo_t *bo);
 276
 277 cairo_private cairo_bool_t
 278 intel_bo_is_inactive (const intel_device_t *device,
 279                       intel_bo_t *bo);
 280
 281 cairo_private cairo_bool_t
 282 intel_bo_wait (const intel_device_t *device, const intel_bo_t *bo);
 283
 284 cairo_private void
 285 intel_bo_write (const intel_device_t *dev,
 286                 intel_bo_t *bo,
 287                 unsigned long offset,
 288                 unsigned long size,
 289                 const void *data);
 290
 291 cairo_private void
 292 intel_bo_read (const intel_device_t *dev,
 293                intel_bo_t *bo,
 294                unsigned long offset,
 295                unsigned long size,
 296                void *data);
 297
 298 cairo_private void *
 299 intel_bo_map (const intel_device_t *dev, intel_bo_t *bo);
 300
 301 cairo_private void
 302 intel_bo_unmap (intel_bo_t *bo);
 303
 304 cairo_private cairo_status_t
 305 intel_bo_init (const intel_device_t *dev,
 306                intel_bo_t *bo,
 307                uint32_t size,
 308                uint32_t initial_domain);
 309
 310 cairo_private cairo_status_t
 311 intel_bo_init_for_name (const intel_device_t *dev,
 312                         intel_bo_t *bo,
 313                         uint32_t size,
 314                         uint32_t name);
 315
 316 cairo_private cairo_surface_t *
 317 intel_bo_get_image (const intel_device_t *device,
 318                     intel_bo_t *bo,
 319                     const cairo_drm_surface_t *surface);
 320
 321 cairo_private cairo_status_t
 322 intel_bo_put_image (intel_device_t *dev,
 323                     intel_bo_t *bo,
 324                     cairo_image_surface_t *src,
 325                     int src_x, int src_y,
 326                     int width, int height,
 327                     int dst_x, int dst_y);
 328
 329 cairo_private void
 330 intel_surface_init (intel_surface_t *surface,
 331                     const cairo_surface_backend_t *backend,
 332                     cairo_drm_device_t *device,
 333                     cairo_format_t format,
 334                     int width, int height);
 335
 336 cairo_private cairo_status_t
 337 intel_buffer_cache_init (intel_buffer_cache_t *cache,
 338                         intel_device_t *device,
 339                         cairo_format_t format,
 340                         int width, int height);
 341
 342 cairo_private cairo_status_t
 343 intel_gradient_render (intel_device_t *device,
 344                        const cairo_gradient_pattern_t *pattern,
 345                        intel_buffer_t *buffer);
 346
 347 cairo_private cairo_int_status_t
 348 intel_get_glyph (intel_device_t *device,
 349                  cairo_scaled_font_t *scaled_font,
 350                  cairo_scaled_glyph_t *scaled_glyph);
 351
 352 cairo_private void
 353 intel_scaled_glyph_fini (cairo_scaled_glyph_t *scaled_glyph,
 354                          cairo_scaled_font_t  *scaled_font);
 355
 356 cairo_private void
 357 intel_scaled_font_fini (cairo_scaled_font_t *scaled_font);
 358
 359 cairo_private void
 360 intel_glyph_cache_unpin (intel_device_t *device);
 361
 362 static inline intel_glyph_t *
 363 intel_glyph_pin (intel_glyph_t *glyph)
 364 {
 365     cairo_rtree_node_t *node = &glyph->node;
 366     if (unlikely (node->pinned == 0))
 367         return _cairo_rtree_pin (&glyph->cache->rtree, node);
 368     return glyph;
 369 }
 370
 371 cairo_private cairo_status_t
 372 intel_snapshot_cache_insert (intel_device_t *device,
 373                              intel_surface_t *surface);
 374
 375 cairo_private void
 376 intel_surface_detach_snapshot (cairo_surface_t *abstract_surface);
 377
 378 cairo_private void
 379 intel_snapshot_cache_thaw (intel_device_t *device);
 380
 381 cairo_private void
 382 intel_throttle (intel_device_t *device);
 383
 384 cairo_private cairo_status_t
 385 intel_surface_acquire_source_image (void *abstract_surface,
 386                                     cairo_image_surface_t **image_out,
 387                                     void **image_extra);
 388
 389 cairo_private void
 390 intel_surface_release_source_image (void *abstract_surface,
 391                                     cairo_image_surface_t *image,
 392                                     void *image_extra);
 393 cairo_private cairo_surface_t *
 394 intel_surface_map_to_image (void *abstract_surface);
 395
 396 cairo_private cairo_status_t
 397 intel_surface_flush (void *abstract_surface,
 398                      unsigned flags);
 399
 400 cairo_private cairo_status_t
 401 intel_surface_finish (void *abstract_surface);
 402
 403 cairo_private void
 404 intel_dump_batchbuffer (const void *batch,
 405                         uint32_t length,
 406                         int devid);
 407
 408 static inline uint32_t cairo_const
 409 MS3_tiling (uint32_t tiling)
 410 {
 411     switch (tiling) {
 412     default:
 413     case I915_TILING_NONE: return 0;
 414     case I915_TILING_X: return MS3_TILED_SURFACE;
 415     case I915_TILING_Y: return MS3_TILED_SURFACE | MS3_TILE_WALK;
 416     }
 417 }
 418
 419 static inline float cairo_const
 420 texcoord_2d_16 (double x, double y)
 421 {
 422     union {
 423         uint32_t ui;
 424         float f;
 425     } u;
 426     u.ui = (_cairo_half_from_float (y) << 16) | _cairo_half_from_float (x);
 427     return u.f;
 428 }
 429
 430 #define PCI_CHIP_I810                   0x7121
 431 #define PCI_CHIP_I810_DC100             0x7123
 432 #define PCI_CHIP_I810_E                 0x7125
 433 #define PCI_CHIP_I815                   0x1132
 434
 435 #define PCI_CHIP_I830_M                 0x3577
 436 #define PCI_CHIP_845_G                  0x2562
 437 #define PCI_CHIP_I855_GM                0x3582
 438 #define PCI_CHIP_I865_G                 0x2572
 439
 440 #define PCI_CHIP_I915_G                 0x2582
 441 #define PCI_CHIP_E7221_G                0x258A
 442 #define PCI_CHIP_I915_GM                0x2592
 443 #define PCI_CHIP_I945_G                 0x2772
 444 #define PCI_CHIP_I945_GM                0x27A2
 445 #define PCI_CHIP_I945_GME               0x27AE
 446
 447 #define PCI_CHIP_Q35_G                  0x29B2
 448 #define PCI_CHIP_G33_G                  0x29C2
 449 #define PCI_CHIP_Q33_G                  0x29D2
 450
 451 #define PCI_CHIP_IGD_GM                 0xA011
 452 #define PCI_CHIP_IGD_G                  0xA001
 453
 454 #define IS_IGDGM(devid) (devid == PCI_CHIP_IGD_GM)
 455 #define IS_IGDG(devid)  (devid == PCI_CHIP_IGD_G)
 456 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
 457
 458 #define PCI_CHIP_I965_G                 0x29A2
 459 #define PCI_CHIP_I965_Q                 0x2992
 460 #define PCI_CHIP_I965_G_1               0x2982
 461 #define PCI_CHIP_I946_GZ                0x2972
 462 #define PCI_CHIP_I965_GM                0x2A02
 463 #define PCI_CHIP_I965_GME               0x2A12
 464
 465 #define PCI_CHIP_GM45_GM                0x2A42
 466
 467 #define PCI_CHIP_IGD_E_G                0x2E02
 468 #define PCI_CHIP_Q45_G                  0x2E12
 469 #define PCI_CHIP_G45_G                  0x2E22
 470 #define PCI_CHIP_G41_G                  0x2E32
 471
 472 #define PCI_CHIP_ILD_G                  0x0042
 473 #define PCI_CHIP_ILM_G                  0x0046
 474
 475 #define IS_MOBILE(devid)        (devid == PCI_CHIP_I855_GM || \
 476                                  devid == PCI_CHIP_I915_GM || \
 477                                  devid == PCI_CHIP_I945_GM || \
 478                                  devid == PCI_CHIP_I945_GME || \
 479                                  devid == PCI_CHIP_I965_GM || \
 480                                  devid == PCI_CHIP_I965_GME || \
 481                                  devid == PCI_CHIP_GM45_GM || IS_IGD(devid))
 482
 483 #define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G || \
 484                                  devid == PCI_CHIP_Q45_G || \
 485                                  devid == PCI_CHIP_G45_G || \
 486                                  devid == PCI_CHIP_G41_G)
 487 #define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
 488 #define IS_G4X(devid)           (IS_G45(devid) || IS_GM45(devid))
 489
 490 #define IS_ILD(devid)           (devid == PCI_CHIP_ILD_G)
 491 #define IS_ILM(devid)           (devid == PCI_CHIP_ILM_G)
 492 #define IS_IRONLAKE(devid)      (IS_ILD(devid) || IS_ILM(devid))
 493
 494 #define IS_915(devid)           (devid == PCI_CHIP_I915_G || \
 495                                  devid == PCI_CHIP_E7221_G || \
 496                                  devid == PCI_CHIP_I915_GM)
 497
 498 #define IS_945(devid)           (devid == PCI_CHIP_I945_G || \
 499                                  devid == PCI_CHIP_I945_GM || \
 500                                  devid == PCI_CHIP_I945_GME || \
 501                                  devid == PCI_CHIP_G33_G || \
 502                                  devid == PCI_CHIP_Q33_G || \
 503                                  devid == PCI_CHIP_Q35_G || IS_IGD(devid))
 504
 505 #define IS_965(devid)           (devid == PCI_CHIP_I965_G || \
 506                                  devid == PCI_CHIP_I965_Q || \
 507                                  devid == PCI_CHIP_I965_G_1 || \
 508                                  devid == PCI_CHIP_I965_GM || \
 509                                  devid == PCI_CHIP_I965_GME || \
 510                                  devid == PCI_CHIP_I946_GZ || \
 511                                  IS_G4X(devid) || \
 512                                  IS_IRONLAKE(devid))
 513
 514 #define IS_9XX(devid)           (IS_915(devid) || \
 515                                  IS_945(devid) || \
 516                                  IS_965(devid))
 517
 518
 519 #endif /* CAIRO_DRM_INTEL_PRIVATE_H */