1 /* Cairo - a vector graphics library with display and print output
3 * Copyright © 2009 Chris Wilson
5 * This library is free software; you can redistribute it and/or
6 * modify it either under the terms of the GNU Lesser General Public
7 * License version 2.1 as published by the Free Software Foundation
8 * (the "LGPL") or, at your option, under the terms of the Mozilla
9 * Public License Version 1.1 (the "MPL"). If you do not alter this
10 * notice, a recipient may use your version of this file under either
11 * the MPL or the LGPL.
13 * You should have received a copy of the LGPL along with this library
14 * in the file COPYING-LGPL-2.1; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA
16 * You should have received a copy of the MPL along with this library
17 * in the file COPYING-MPL-1.1
19 * The contents of this file are subject to the Mozilla Public License
20 * Version 1.1 (the "License"); you may not use this file except in
21 * compliance with the License. You may obtain a copy of the License at
22 * http://www.mozilla.org/MPL/
24 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY
25 * OF ANY KIND, either express or implied. See the LGPL or the MPL for
26 * the specific language governing rights and limitations.
30 #ifndef CAIRO_DRM_INTEL_IOCTL_PRIVATE_H
31 #define CAIRO_DRM_INTEL_IOCTL_PRIVATE_H
33 #include "cairo-drm-intel-command-private.h"
35 #define I915_PARAM_IRQ_ACTIVE 1
36 #define I915_PARAM_ALLOW_BATCHBUFFER 2
37 #define I915_PARAM_LAST_DISPATCH 3
38 #define I915_PARAM_CHIPSET_ID 4
39 #define I915_PARAM_HAS_GEM 5
40 #define I915_PARAM_NUM_FENCES_AVAIL 6
41 #define I915_PARAM_HAS_OVERLAY 7
42 #define I915_PARAM_HAS_PAGEFLIPPING 8
43 #define I915_PARAM_HAS_EXECBUF2 9
45 struct intel_getparam {
52 * Intel memory domains
54 * Most of these just align with the various caches in
55 * the system and are used to flush and invalidate as
56 * objects end up cached in different domains.
59 #define I915_GEM_DOMAIN_CPU 0x00000001
60 /* Render cache, used by 2D and 3D drawing */
61 #define I915_GEM_DOMAIN_RENDER 0x00000002
62 /* Sampler cache, used by texture engine */
63 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
64 /* Command queue, used to load batch buffers */
65 #define I915_GEM_DOMAIN_COMMAND 0x00000008
66 /* Instruction cache, used by shader programs */
67 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
68 /* Vertex address cache */
69 #define I915_GEM_DOMAIN_VERTEX 0x00000020
70 /* GTT domain - aperture and scanout */
71 #define I915_GEM_DOMAIN_GTT 0x00000040
74 #define I915_TILING_NONE 0
75 #define I915_TILING_X 1
76 #define I915_TILING_Y 2
78 #define I915_BIT_6_SWIZZLE_NONE 0
79 #define I915_BIT_6_SWIZZLE_9 1
80 #define I915_BIT_6_SWIZZLE_9_10 2
81 #define I915_BIT_6_SWIZZLE_9_11 3
82 #define I915_BIT_6_SWIZZLE_9_10_11 4
84 #define DRM_I915_GEM_EXECBUFFER 0x14
85 #define DRM_I915_GEM_BUSY 0x17
86 #define DRM_I915_GEM_THROTTLE 0x18
87 #define DRM_I915_GEM_CREATE 0x1b
88 #define DRM_I915_GEM_PREAD 0x1c
89 #define DRM_I915_GEM_PWRITE 0x1d
90 #define DRM_I915_GEM_MMAP 0x1e
91 #define DRM_I915_GEM_SET_DOMAIN 0x1f
92 #define DRM_I915_GEM_SET_TILING 0x21
93 #define DRM_I915_GEM_GET_TILING 0x22
94 #define DRM_I915_GEM_GET_APERTURE 0x23
95 #define DRM_I915_GEM_MMAP_GTT 0x24
97 struct drm_i915_gem_create {
99 * Requested size for the object.
101 * The (page-aligned) allocated size for the object will be returned.
105 * Returned handle for the object.
107 * Object handles are nonzero.
113 struct drm_i915_gem_pread {
114 /* Handle for the object being read. */
117 /* Offset into the object to read from */
119 /* Length of data to read */
122 * Pointer to write the data into.
124 * This is a fixed-size type for 32/64 compatibility.
129 struct drm_i915_gem_pwrite {
130 /* Handle for the object being written to. */
133 /* Offset into the object to write to */
135 /* Length of data to write */
138 * Pointer to read the data from.
140 * This is a fixed-size type for 32/64 compatibility.
145 struct drm_i915_gem_mmap {
146 /* Handle for the object being mapped. */
149 /* Offset in the object to map. */
152 * Length of data to map.
154 * The value will be page-aligned.
158 * Returned pointer the data was mapped at.
160 * This is a fixed-size type for 32/64 compatibility.
165 struct drm_i915_gem_mmap_gtt {
166 /* Handle for the object being mapped. */
170 * Fake offset to use for subsequent mmap call
172 * This is a fixed-size type for 32/64 compatibility.
177 struct drm_i915_gem_set_domain {
178 /* Handle for the object */
181 /* New read domains */
182 uint32_t read_domains;
184 /* New write domain */
185 uint32_t write_domain;
188 struct drm_i915_gem_relocation_entry {
190 * Handle of the buffer being pointed to by this relocation entry.
192 * It's appealing to make this be an index into the mm_validate_entry
193 * list to refer to the buffer, but this allows the driver to create
194 * a relocation list for state buffers and not re-write it per
195 * exec using the buffer.
197 uint32_t target_handle;
200 * Value to be added to the offset of the target buffer to make up
201 * the relocation entry.
205 /* Offset in the buffer the relocation entry will be written into */
209 * Offset value of the target buffer that the relocation entry was last
212 * If the buffer has the same offset as last time, we can skip syncing
213 * and writing the relocation. This value is written back out by
214 * the execbuffer ioctl when the relocation is written.
216 uint64_t presumed_offset;
219 * Target memory domains read by this operation.
221 uint32_t read_domains;
224 * Target memory domains written by this operation.
226 * Note that only one domain may be written by the whole
227 * execbuffer operation, so that where there are conflicts,
228 * the application will get -EINVAL back.
230 uint32_t write_domain;
233 struct drm_i915_gem_exec_object {
235 * User's handle for a buffer to be bound into the GTT for this
240 /* Number of relocations to be performed on this buffer */
241 uint32_t relocation_count;
243 * Pointer to array of struct drm_i915_gem_relocation_entry containing
244 * the relocations to be performed in this buffer.
248 /* Required alignment in graphics aperture */
252 * Returned value of the updated offset of the object, for future
253 * presumed_offset writes.
258 struct drm_i915_gem_execbuffer {
260 * List of buffers to be validated with their relocations to be
261 * performend on them.
263 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
265 * These buffers must be listed in an order such that all relocations
266 * a buffer is performing refer to buffers that have already appeared
267 * in the validate list.
269 uint64_t buffers_ptr;
270 uint32_t buffer_count;
272 /* Offset in the batchbuffer to start execution from. */
273 uint32_t batch_start_offset;
274 /* Bytes used in batchbuffer from batch_start_offset */
278 uint32_t num_cliprects;
279 /* This is a struct drm_clip_rect *cliprects */
280 uint64_t cliprects_ptr;
283 struct drm_i915_gem_busy {
284 /* Handle of the buffer to check for busy */
287 /* Return busy status (1 if busy, 0 if idle) */
291 struct drm_i915_gem_set_tiling {
292 /* Handle of the buffer to have its tiling state updated */
296 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
299 * This value is to be set on request, and will be updated by the
300 * kernel on successful return with the actual chosen tiling layout.
302 * The tiling mode may be demoted to I915_TILING_NONE when the system
303 * has bit 6 swizzling that can't be managed correctly by GEM.
305 * Buffer contents become undefined when changing tiling_mode.
307 uint32_t tiling_mode;
310 * Stride in bytes for the object when in I915_TILING_X or
316 * Returned address bit 6 swizzling required for CPU access through
319 uint32_t swizzle_mode;
322 struct drm_i915_gem_get_tiling {
323 /* Handle of the buffer to get tiling state for. */
327 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
330 uint32_t tiling_mode;
333 * Returned address bit 6 swizzling required for CPU access through
336 uint32_t swizzle_mode;
339 struct drm_i915_gem_get_aperture {
340 /* Total size of the aperture used by i915_gem_execbuffer, in bytes */
344 * Available space in the aperture used by i915_gem_execbuffer, in
347 uint64_t aper_available_size;
350 #define DRM_I915_GETPARAM 0x06
352 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, struct intel_getparam)
353 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
354 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
355 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
356 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
357 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
358 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
359 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
360 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
361 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
362 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
363 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
364 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
366 #define I915_MADV_WILLNEED 0
367 #define I915_MADV_DONTNEED 1
369 struct drm_i915_gem_madvise {
374 #define DRM_I915_GEM_MADVISE 0x26
375 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
378 /* XXX execbuffer2 */
379 struct drm_i915_gem_exec_object2 {
381 * User's handle for a buffer to be bound into the GTT for this
386 /* Number of relocations to be performed on this buffer */
387 uint32_t relocation_count;
389 * Pointer to array of struct drm_i915_gem_relocation_entry containing
390 * the relocations to be performed in this buffer.
394 /* Required alignment in graphics aperture */
398 * Returned value of the updated offset of the object, for future
399 * presumed_offset writes.
403 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
409 struct drm_i915_gem_execbuffer2 {
411 * List of gem_exec_object2 structs
413 uint64_t buffers_ptr;
414 uint32_t buffer_count;
416 /* Offset in the batchbuffer to start execution from. */
417 uint32_t batch_start_offset;
418 /* Bytes used in batchbuffer from batch_start_offset */
422 uint32_t num_cliprects;
423 /* This is a struct drm_clip_rect *cliprects */
424 uint64_t cliprects_ptr;
430 #define I915_GEM_3D_PIPELINE 0x1
431 #define I915_GEM_MEDIA_PIPELINE 0x2
432 #define DRM_I915_GEM_EXECBUFFER2 0x29
433 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
435 struct drm_i915_gem_real_size {
439 #define DRM_I915_GEM_REAL_SIZE 0x2a
440 #define DRM_IOCTL_I915_GEM_REAL_SIZE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_REAL_SIZE, struct drm_i915_gem_real_size)
442 #endif /* CAIRO_DRM_INTEL_IOCTL_PRIVATE_H */