2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #ifndef CAIRO_DRM_INTEL_BRW_EU_H
33 #define CAIRO_DRM_INTEL_BRW_EU_H
35 #include "cairo-drm-intel-brw-structs.h"
36 #include "cairo-drm-intel-brw-defines.h"
42 * Writemask values, 1 bit per component.
44 #define WRITEMASK_X 0x1
45 #define WRITEMASK_Y 0x2
46 #define WRITEMASK_Z 0x4
47 #define WRITEMASK_W 0x8
48 #define WRITEMASK_XY (WRITEMASK_X | WRITEMASK_Y)
49 #define WRITEMASK_XZ (WRITEMASK_X | WRITEMASK_Z)
50 #define WRITEMASK_YZ (WRITEMASK_Y | WRITEMASK_Z)
51 #define WRITEMASK_XYZ (WRITEMASK_X | WRITEMASK_Y | WRITEMASK_Z)
52 #define WRITEMASK_XW (WRITEMASK_X | WRITEMASK_W)
53 #define WRITEMASK_YW (WRITEMASK_Y | WRITEMASK_W)
54 #define WRITEMASK_XYW (WRITEMASK_X | WRITEMASK_Y | WRITEMASK_W)
55 #define WRITEMASK_ZW (WRITEMASK_Z | WRITEMASK_W)
56 #define WRITEMASK_XZW (WRITEMASK_X | WRITEMASK_Z | WRITEMASK_W)
57 #define WRITEMASK_YZW (WRITEMASK_Y | WRITEMASK_Z | WRITEMASK_W)
58 #define WRITEMASK_XYZW (WRITEMASK_X | WRITEMASK_Y | WRITEMASK_Z | WRITEMASK_W)
60 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
61 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
63 #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4 (0,1,2,3)
64 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4 (0,1,2,3)
65 #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4 (0,0,0,0)
66 #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4 (0,1,0,1)
68 #define REG_SIZE (8*4)
70 /* These aren't hardware structs, just something useful for us to pass around:
72 * Align1 operation has a lot of control over input ranges. Used in
73 * WM programs to implement shaders decomposed into "channel serial"
74 * or "structure of array" form:
80 uint32_t subnr:5; /* :1 in align16 */
81 uint32_t negate:1; /* source only */
82 uint32_t abs:1; /* source only */
83 uint32_t vstride:4; /* source only */
84 uint32_t width:3; /* src only, align1 only */
85 uint32_t hstride:2; /* align1 only */
86 uint32_t address_mode:1; /* relative addressing, hopefully! */
91 uint32_t swizzle:8; /* src only, align16 only */
92 uint32_t writemask:4; /* dest only, align16 only */
93 int32_t indirect_offset:10; /* relative addressing offset */
94 uint32_t pad1:10; /* two dwords total */
103 struct brw_indirect {
104 uint32_t addr_subnr:4;
105 int32_t addr_offset:10;
109 struct brw_glsl_label;
110 struct brw_glsl_call;
112 #define BRW_EU_MAX_INSN_STACK 5
113 #define BRW_EU_MAX_INSN 200
116 struct brw_instruction store[BRW_EU_MAX_INSN];
121 /* Allow clients to push/pop instruction state:
123 struct brw_instruction stack[BRW_EU_MAX_INSN_STACK];
124 struct brw_instruction *current;
127 int single_program_flow;
128 struct brw_context *brw;
130 struct brw_glsl_label *first_label; /*< linked list of labels */
131 struct brw_glsl_call *first_call; /*< linked list of CALs */
135 brw_save_label (struct brw_compile *c,
140 brw_save_call (struct brw_compile *c,
145 brw_resolve_cals (struct brw_compile *c);
147 static cairo_always_inline int
148 type_sz (uint32_t type)
151 case BRW_REGISTER_TYPE_UD:
152 case BRW_REGISTER_TYPE_D:
153 case BRW_REGISTER_TYPE_F:
155 case BRW_REGISTER_TYPE_HF:
156 case BRW_REGISTER_TYPE_UW:
157 case BRW_REGISTER_TYPE_W:
159 case BRW_REGISTER_TYPE_UB:
160 case BRW_REGISTER_TYPE_B:
168 * Construct a brw_reg.
169 * \param file one of the BRW_x_REGISTER_FILE values
170 * \param nr register number/index
171 * \param subnr register sub number
172 * \param type one of BRW_REGISTER_TYPE_x
173 * \param vstride one of BRW_VERTICAL_STRIDE_x
174 * \param width one of BRW_WIDTH_x
175 * \param hstride one of BRW_HORIZONTAL_STRIDE_x
176 * \param swizzle one of BRW_SWIZZLE_x
177 * \param writemask WRITEMASK_X/Y/Z/W bitfield
179 static cairo_always_inline struct brw_reg
180 brw_reg (uint32_t file,
192 if (type == BRW_GENERAL_REGISTER_FILE)
194 else if (type == BRW_MESSAGE_REGISTER_FILE)
196 else if (type == BRW_ARCHITECTURE_REGISTER_FILE)
197 assert(nr <= BRW_ARF_IP);
202 reg.subnr = subnr * type_sz(type);
205 reg.vstride = vstride;
207 reg.hstride = hstride;
208 reg.address_mode = BRW_ADDRESS_DIRECT;
211 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
212 * set swizzle and writemask to W, as the lower bits of subnr will
213 * be lost when converted to align16. This is probably too much to
214 * keep track of as you'd want it adjusted by suboffset(), etc.
215 * Perhaps fix up when converting to align16?
217 reg.dw1.bits.swizzle = swizzle;
218 reg.dw1.bits.writemask = writemask;
219 reg.dw1.bits.indirect_offset = 0;
220 reg.dw1.bits.pad1 = 0;
225 /* Construct float[16] register */
226 static cairo_always_inline struct brw_reg
227 brw_vec16_reg (uint32_t file,
231 return brw_reg (file, nr, subnr,
233 BRW_VERTICAL_STRIDE_16,
235 BRW_HORIZONTAL_STRIDE_1,
240 /* Construct float[8] register */
241 static cairo_always_inline struct brw_reg
242 brw_vec8_reg (uint32_t file,
246 return brw_reg (file, nr, subnr,
248 BRW_VERTICAL_STRIDE_8,
250 BRW_HORIZONTAL_STRIDE_1,
255 /* Construct float[4] register */
256 static cairo_always_inline struct brw_reg
257 brw_vec4_reg (uint32_t file,
261 return brw_reg (file, nr, subnr,
263 BRW_VERTICAL_STRIDE_4,
265 BRW_HORIZONTAL_STRIDE_1,
270 /* Construct float[2] register */
271 static cairo_always_inline struct brw_reg
272 brw_vec2_reg (uint32_t file,
276 return brw_reg (file, nr, subnr,
278 BRW_VERTICAL_STRIDE_2,
280 BRW_HORIZONTAL_STRIDE_1,
285 /* Construct float[1] register */
286 static cairo_always_inline struct brw_reg
287 brw_vec1_reg (uint32_t file,
291 return brw_reg (file, nr, subnr,
293 BRW_VERTICAL_STRIDE_0,
295 BRW_HORIZONTAL_STRIDE_0,
300 static cairo_always_inline struct brw_reg
301 retype (struct brw_reg reg,
308 static cairo_always_inline struct brw_reg
309 suboffset (struct brw_reg reg,
312 reg.subnr += delta * type_sz (reg.type);
316 static cairo_always_inline struct brw_reg
317 offset (struct brw_reg reg,
324 static cairo_always_inline struct brw_reg
325 byte_offset (struct brw_reg reg,
328 uint32_t newoffset = reg.nr * REG_SIZE + reg.subnr + bytes;
329 reg.nr = newoffset / REG_SIZE;
330 reg.subnr = newoffset % REG_SIZE;
334 /* Construct unsigned word[16] register */
335 static cairo_always_inline struct brw_reg
336 brw_uw16_reg (uint32_t file,
340 return suboffset (retype (brw_vec16_reg (file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
343 /* Construct unsigned word[8] register */
344 static cairo_always_inline struct brw_reg
345 brw_uw8_reg (uint32_t file,
349 return suboffset (retype (brw_vec8_reg (file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
352 /* Construct unsigned word[2] register */
353 static cairo_always_inline struct brw_reg
354 brw_uw2_reg (uint32_t file,
358 return suboffset (retype (brw_vec2_reg (file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
361 /* Construct unsigned word[1] register */
362 static cairo_always_inline struct brw_reg
363 brw_uw1_reg (uint32_t file,
367 return suboffset (retype (brw_vec1_reg (file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
370 static cairo_always_inline struct brw_reg
371 brw_imm_reg (uint32_t type)
373 return brw_reg (BRW_IMMEDIATE_VALUE,
377 BRW_VERTICAL_STRIDE_0,
379 BRW_HORIZONTAL_STRIDE_0,
384 /* Construct float immediate register */
385 static cairo_always_inline struct brw_reg brw_imm_f( float f )
387 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
392 /* Construct integer immediate register */
393 static cairo_always_inline struct brw_reg brw_imm_d( int32_t d )
395 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
400 /* Construct uint immediate register */
401 static cairo_always_inline struct brw_reg brw_imm_ud( uint32_t ud )
403 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
408 /* Construct ushort immediate register */
409 static cairo_always_inline struct brw_reg brw_imm_uw( uint16_t uw )
411 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
412 imm.dw1.ud = uw | (uw << 16);
416 /* Construct short immediate register */
417 static cairo_always_inline struct brw_reg brw_imm_w( int16_t w )
419 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
420 imm.dw1.d = w | (w << 16);
424 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
425 * numbers alias with _V and _VF below:
428 /* Construct vector of eight signed half-byte values */
429 static cairo_always_inline
430 struct brw_reg brw_imm_v (uint32_t v)
432 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
433 imm.vstride = BRW_VERTICAL_STRIDE_0;
434 imm.width = BRW_WIDTH_8;
435 imm.hstride = BRW_HORIZONTAL_STRIDE_1;
440 /* Construct vector of four 8-bit float values */
441 static cairo_always_inline struct brw_reg
442 brw_imm_vf (uint32_t v)
444 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
445 imm.vstride = BRW_VERTICAL_STRIDE_0;
446 imm.width = BRW_WIDTH_4;
447 imm.hstride = BRW_HORIZONTAL_STRIDE_1;
454 #define VF_NEG (1<<7)
456 static cairo_always_inline struct brw_reg
457 brw_imm_vf4 (uint32_t v0,
462 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
463 imm.vstride = BRW_VERTICAL_STRIDE_0;
464 imm.width = BRW_WIDTH_4;
465 imm.hstride = BRW_HORIZONTAL_STRIDE_1;
466 imm.dw1.ud = ((v0 << 0) |
473 static cairo_always_inline struct brw_reg
474 brw_address (struct brw_reg reg)
476 return brw_imm_uw (reg.nr * REG_SIZE + reg.subnr);
479 /* Construct float[1] general-purpose register */
480 static cairo_always_inline struct brw_reg
481 brw_vec1_grf (uint32_t nr, uint32_t subnr)
483 return brw_vec1_reg (BRW_GENERAL_REGISTER_FILE, nr, subnr);
486 /* Construct float[2] general-purpose register */
487 static cairo_always_inline struct brw_reg
488 brw_vec2_grf (uint32_t nr, uint32_t subnr)
490 return brw_vec2_reg (BRW_GENERAL_REGISTER_FILE, nr, subnr);
493 /* Construct float[4] general-purpose register */
494 static cairo_always_inline struct brw_reg
495 brw_vec4_grf (uint32_t nr, uint32_t subnr)
497 return brw_vec4_reg (BRW_GENERAL_REGISTER_FILE, nr, subnr);
500 /* Construct float[8] general-purpose register */
501 static cairo_always_inline struct brw_reg
502 brw_vec8_grf (uint32_t nr)
504 return brw_vec8_reg (BRW_GENERAL_REGISTER_FILE, nr, 0);
507 static cairo_always_inline struct brw_reg
508 brw_uw8_grf (uint32_t nr, uint32_t subnr)
510 return brw_uw8_reg (BRW_GENERAL_REGISTER_FILE, nr, subnr);
513 static cairo_always_inline struct brw_reg
514 brw_uw16_grf (uint32_t nr, uint32_t subnr)
516 return brw_uw16_reg (BRW_GENERAL_REGISTER_FILE, nr, subnr);
519 /* Construct null register (usually used for setting condition codes) */
520 static cairo_always_inline struct brw_reg
523 return brw_vec8_reg (BRW_ARCHITECTURE_REGISTER_FILE,
528 static cairo_always_inline struct brw_reg
529 brw_address_reg (uint32_t subnr)
531 return brw_uw1_reg (BRW_ARCHITECTURE_REGISTER_FILE,
536 /* If/else instructions break in align16 mode if writemask & swizzle
537 * aren't xyzw. This goes against the convention for other scalar
540 static cairo_always_inline struct brw_reg
543 return brw_reg (BRW_ARCHITECTURE_REGISTER_FILE,
546 BRW_REGISTER_TYPE_UD,
547 BRW_VERTICAL_STRIDE_4, /* ? */
549 BRW_HORIZONTAL_STRIDE_0,
554 static cairo_always_inline struct brw_reg
557 return brw_vec8_reg (BRW_ARCHITECTURE_REGISTER_FILE,
562 static cairo_always_inline struct brw_reg
565 return brw_uw1_reg (BRW_ARCHITECTURE_REGISTER_FILE,
570 static cairo_always_inline struct brw_reg
571 brw_mask_reg (uint32_t subnr)
573 return brw_uw1_reg (BRW_ARCHITECTURE_REGISTER_FILE,
578 static cairo_always_inline struct brw_reg
579 brw_message4_reg (uint32_t nr)
581 return brw_vec4_reg (BRW_MESSAGE_REGISTER_FILE,
586 static cairo_always_inline struct brw_reg
587 brw_message_reg (uint32_t nr)
589 return brw_vec8_reg (BRW_MESSAGE_REGISTER_FILE,
594 /* This is almost always called with a numeric constant argument, so
595 * make things easy to evaluate at compile time:
597 static cairo_always_inline uint32_t
612 static cairo_always_inline struct brw_reg
613 stride (struct brw_reg reg,
618 reg.vstride = cvt (vstride);
619 reg.width = cvt (width) - 1;
620 reg.hstride = cvt (hstride);
624 static cairo_always_inline struct brw_reg
625 vec16 (struct brw_reg reg)
627 return stride (reg, 16,16,1);
630 static cairo_always_inline struct brw_reg
631 vec8 (struct brw_reg reg)
633 return stride (reg, 8,8,1);
636 static cairo_always_inline struct brw_reg
637 vec4 (struct brw_reg reg)
639 return stride (reg, 4,4,1);
642 static cairo_always_inline struct brw_reg
643 vec2 (struct brw_reg reg)
645 return stride (reg, 2,2,1);
648 static cairo_always_inline struct brw_reg
649 vec1 (struct brw_reg reg)
651 return stride (reg, 0,1,0);
654 static cairo_always_inline struct brw_reg
655 get_element (struct brw_reg reg, uint32_t elt)
657 return vec1 (suboffset (reg, elt));
660 static cairo_always_inline struct brw_reg
661 get_element_ud (struct brw_reg reg, uint32_t elt)
663 return vec1 (suboffset (retype (reg, BRW_REGISTER_TYPE_UD), elt));
666 static cairo_always_inline struct brw_reg
667 brw_swizzle (struct brw_reg reg,
673 reg.dw1.bits.swizzle = BRW_SWIZZLE4 (BRW_GET_SWZ (reg.dw1.bits.swizzle, x),
674 BRW_GET_SWZ (reg.dw1.bits.swizzle, y),
675 BRW_GET_SWZ (reg.dw1.bits.swizzle, z),
676 BRW_GET_SWZ (reg.dw1.bits.swizzle, w));
680 static cairo_always_inline struct brw_reg
681 brw_swizzle1 (struct brw_reg reg,
684 return brw_swizzle (reg, x, x, x, x);
687 static cairo_always_inline struct brw_reg
688 brw_writemask (struct brw_reg reg,
691 reg.dw1.bits.writemask &= mask;
695 static cairo_always_inline struct brw_reg
696 brw_set_writemask (struct brw_reg reg,
699 reg.dw1.bits.writemask = mask;
703 static cairo_always_inline struct brw_reg
704 negate (struct brw_reg reg)
710 static cairo_always_inline struct brw_reg
711 brw_abs (struct brw_reg reg)
717 static cairo_always_inline struct brw_reg
718 brw_vec4_indirect (uint32_t subnr,
721 struct brw_reg reg = brw_vec4_grf (0, 0);
723 reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
724 reg.dw1.bits.indirect_offset = offset;
728 static cairo_always_inline struct brw_reg
729 brw_vec1_indirect (uint32_t subnr,
732 struct brw_reg reg = brw_vec1_grf (0, 0);
734 reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
735 reg.dw1.bits.indirect_offset = offset;
739 static cairo_always_inline struct brw_reg
740 deref_4f (struct brw_indirect ptr, int32_t offset)
742 return brw_vec4_indirect (ptr.addr_subnr, ptr.addr_offset + offset);
745 static cairo_always_inline struct brw_reg
746 deref_1f(struct brw_indirect ptr, int32_t offset)
748 return brw_vec1_indirect (ptr.addr_subnr, ptr.addr_offset + offset);
751 static cairo_always_inline struct brw_reg
752 deref_4b(struct brw_indirect ptr, int32_t offset)
754 return retype (deref_4f (ptr, offset), BRW_REGISTER_TYPE_B);
757 static cairo_always_inline struct brw_reg
758 deref_1uw(struct brw_indirect ptr, int32_t offset)
760 return retype (deref_1f (ptr, offset), BRW_REGISTER_TYPE_UW);
763 static cairo_always_inline struct brw_reg
764 deref_1d (struct brw_indirect ptr, int32_t offset)
766 return retype (deref_1f (ptr, offset), BRW_REGISTER_TYPE_D);
769 static cairo_always_inline struct brw_reg
770 deref_1ud (struct brw_indirect ptr, int32_t offset)
772 return retype (deref_1f (ptr, offset), BRW_REGISTER_TYPE_UD);
775 static cairo_always_inline struct brw_reg
776 get_addr_reg (struct brw_indirect ptr)
778 return brw_address_reg (ptr.addr_subnr);
781 static cairo_always_inline struct brw_indirect
782 brw_indirect_offset (struct brw_indirect ptr, int32_t offset)
784 ptr.addr_offset += offset;
788 static cairo_always_inline struct brw_indirect
789 brw_indirect (uint32_t addr_subnr, int32_t offset)
791 struct brw_indirect ptr;
792 ptr.addr_subnr = addr_subnr;
793 ptr.addr_offset = offset;
798 static cairo_always_inline struct brw_instruction *
799 current_insn (struct brw_compile *p)
801 return &p->store[p->nr_insn];
804 cairo_private void brw_pop_insn_state (struct brw_compile *p);
805 cairo_private void brw_push_insn_state (struct brw_compile *p);
806 cairo_private void brw_set_mask_control (struct brw_compile *p, uint32_t value);
807 cairo_private void brw_set_saturate (struct brw_compile *p, uint32_t value);
808 cairo_private void brw_set_access_mode (struct brw_compile *p, uint32_t access_mode);
809 cairo_private void brw_set_compression_control (struct brw_compile *p, int control);
810 cairo_private void brw_set_predicate_control_flag_value (struct brw_compile *p, uint32_t value);
811 cairo_private void brw_set_predicate_control (struct brw_compile *p, uint32_t pc);
812 cairo_private void brw_set_conditionalmod (struct brw_compile *p, uint32_t conditional);
815 brw_compile_init (struct brw_compile *p,
816 cairo_bool_t is_g4x);
817 cairo_private const uint32_t *brw_get_program (struct brw_compile *p, uint32_t *sz);
819 /* Helpers for regular instructions:
822 cairo_private_no_warn struct brw_instruction * \
823 brw_##OP(struct brw_compile *p, \
824 struct brw_reg dest, \
825 struct brw_reg src0);
828 cairo_private_no_warn struct brw_instruction * \
829 brw_##OP(struct brw_compile *p, \
830 struct brw_reg dest, \
831 struct brw_reg src0, \
832 struct brw_reg src1);
863 /* Helpers for SEND instruction: */
865 brw_urb_WRITE (struct brw_compile *p,
872 uint32_t response_length,
879 brw_fb_WRITE (struct brw_compile *p,
883 uint32_t binding_table_index,
885 uint32_t response_length,
889 brw_SAMPLE (struct brw_compile *p,
893 uint32_t binding_table_index,
897 uint32_t response_length,
902 brw_math_16 (struct brw_compile *p,
911 brw_math (struct brw_compile *p,
921 brw_dp_READ_16 (struct brw_compile *p,
924 uint32_t scratch_offset);
927 brw_dp_WRITE_16 (struct brw_compile *p,
930 uint32_t scratch_offset);
932 /* If/else/endif. Works by manipulating the execution flags on each
935 cairo_private struct brw_instruction *
936 brw_IF (struct brw_compile *p,
937 uint32_t execute_size);
939 cairo_private struct brw_instruction *
940 brw_ELSE (struct brw_compile *p,
941 struct brw_instruction *if_insn);
944 brw_ENDIF (struct brw_compile *p,
945 struct brw_instruction *if_or_else_insn);
948 /* DO/WHILE loops: */
949 cairo_private struct brw_instruction *
950 brw_DO (struct brw_compile *p,
951 uint32_t execute_size);
953 cairo_private struct brw_instruction *
954 brw_WHILE (struct brw_compile *p,
955 struct brw_instruction *patch_insn);
957 cairo_private struct brw_instruction *
958 brw_BREAK (struct brw_compile *p);
960 cairo_private struct brw_instruction *
961 brw_CONT (struct brw_compile *p);
965 brw_land_fwd_jump (struct brw_compile *p,
966 struct brw_instruction *jmp_insn);
969 brw_NOP (struct brw_compile *p);
971 /* Special case: there is never a destination, execution size will be
975 brw_CMP (struct brw_compile *p,
977 uint32_t conditional,
979 struct brw_reg src1);
982 brw_print_reg (struct brw_reg reg);
984 cairo_private struct brw_instruction *
985 brw_next_instruction (struct brw_compile *p,
989 brw_instruction_set_destination (struct brw_instruction *insn,
990 struct brw_reg dest);
993 brw_instruction_set_source0 (struct brw_instruction *insn,
997 brw_instruction_set_dp_write_message (struct brw_instruction *insn,
998 uint32_t binding_table_index,
999 uint32_t msg_control,
1001 uint32_t msg_length,
1002 uint32_t pixel_scoreboard_clear,
1003 uint32_t response_length,
1004 uint32_t end_of_thread);
1006 /***********************************************************************
1011 brw_copy_indirect_to_indirect (struct brw_compile *p,
1012 struct brw_indirect dst_ptr,
1013 struct brw_indirect src_ptr,
1017 brw_copy_from_indirect (struct brw_compile *p,
1019 struct brw_indirect ptr,
1023 brw_copy4 (struct brw_compile *p,
1029 brw_copy8 (struct brw_compile *p,
1035 brw_math_invert (struct brw_compile *p,
1037 struct brw_reg src);
1040 brw_set_src1 (struct brw_instruction *insn,
1041 struct brw_reg reg);