src/drm/cairo-drm-i965-private.h

   1 #ifndef CAIRO_DRM_I965_PRIVATE_H
   2 #define CAIRO_DRM_I965_PRIVATE_H
   3
   4 #include "cairo-drm-intel-private.h"
   5
   6 #include "cairo-hash-private.h"
   7 #include "cairo-freelist-private.h"
   8
   9 #include "cairo-drm-intel-brw-defines.h"
  10
  11 #include <setjmp.h>
  12
  13 #define BRW_MI_GLOBAL_SNAPSHOT_RESET   (1 << 3)
  14
  15 /*
  16  * New regs for broadwater -- we need to split this file up sensibly somehow.
  17  */
  18 #define BRW_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \
  19                                            ((Pipeline) << 27) | \
  20                                            ((Opcode) << 24) | \
  21                                            ((Subopcode) << 16))
  22
  23 #define BRW_URB_FENCE                           BRW_3D(0, 0, 0)
  24 #define BRW_CS_URB_STATE                        BRW_3D(0, 0, 1)
  25 #define BRW_CONSTANT_BUFFER                     BRW_3D(0, 0, 2)
  26 #define BRW_STATE_PREFETCH                      BRW_3D(0, 0, 3)
  27
  28 #define BRW_STATE_BASE_ADDRESS                  BRW_3D(0, 1, 1)
  29 #define BRW_STATE_SIP                           BRW_3D(0, 1, 2)
  30 #define BRW_PIPELINE_SELECT                     BRW_3D(0, 1, 4)
  31
  32 #define NEW_PIPELINE_SELECT                     BRW_3D(1, 1, 4)
  33
  34 #define BRW_MEDIA_STATE_POINTERS                BRW_3D(2, 0, 0)
  35 #define BRW_MEDIA_OBJECT                        BRW_3D(2, 1, 0)
  36
  37 #define BRW_3DSTATE_PIPELINED_POINTERS          BRW_3D(3, 0, 0)
  38 #define BRW_3DSTATE_BINDING_TABLE_POINTERS      BRW_3D(3, 0, 1)
  39 #define BRW_3DSTATE_VERTEX_BUFFERS              BRW_3D(3, 0, 8)
  40 #define BRW_3DSTATE_VERTEX_ELEMENTS             BRW_3D(3, 0, 9)
  41 #define BRW_3DSTATE_INDEX_BUFFER                BRW_3D(3, 0, 0xa)
  42 #define BRW_3DSTATE_VF_STATISTICS               BRW_3D(3, 0, 0xb)
  43
  44 #define BRW_3DSTATE_DRAWING_RECTANGLE           BRW_3D(3, 1, 0)
  45 #define BRW_3DSTATE_CONSTANT_COLOR              BRW_3D(3, 1, 1)
  46 #define BRW_3DSTATE_SAMPLER_PALETTE_LOAD        BRW_3D(3, 1, 2)
  47 #define BRW_3DSTATE_CHROMA_KEY                  BRW_3D(3, 1, 4)
  48 #define BRW_3DSTATE_DEPTH_BUFFER                BRW_3D(3, 1, 5)
  49 #define BRW_3DSTATE_POLY_STIPPLE_OFFSET         BRW_3D(3, 1, 6)
  50 #define BRW_3DSTATE_POLY_STIPPLE_PATTERN        BRW_3D(3, 1, 7)
  51 #define BRW_3DSTATE_LINE_STIPPLE                BRW_3D(3, 1, 8)
  52 #define BRW_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP   BRW_3D(3, 1, 9)
  53 /* These two are BLC and CTG only, not BW or CL */
  54 #define BRW_3DSTATE_AA_LINE_PARAMS              BRW_3D(3, 1, 0xa)
  55 #define BRW_3DSTATE_GS_SVB_INDEX                BRW_3D(3, 1, 0xb)
  56
  57 #define BRW_PIPE_CONTROL                        BRW_3D(3, 2, 0)
  58
  59 #define BRW_3DPRIMITIVE                         BRW_3D(3, 3, 0)
  60
  61 #define PIPELINE_SELECT_3D              0
  62 #define PIPELINE_SELECT_MEDIA           1
  63
  64 #define UF0_CS_REALLOC                  (1 << 13)
  65 #define UF0_VFE_REALLOC                 (1 << 12)
  66 #define UF0_SF_REALLOC                  (1 << 11)
  67 #define UF0_CLIP_REALLOC                (1 << 10)
  68 #define UF0_GS_REALLOC                  (1 << 9)
  69 #define UF0_VS_REALLOC                  (1 << 8)
  70 #define UF1_CLIP_FENCE_SHIFT            20
  71 #define UF1_GS_FENCE_SHIFT              10
  72 #define UF1_VS_FENCE_SHIFT              0
  73 #define UF2_CS_FENCE_SHIFT              20
  74 #define UF2_VFE_FENCE_SHIFT             10
  75 #define UF2_SF_FENCE_SHIFT              0
  76
  77 /* for BRW_STATE_BASE_ADDRESS */
  78 #define BASE_ADDRESS_MODIFY             (1 << 0)
  79
  80 /* for BRW_3DSTATE_PIPELINED_POINTERS */
  81 #define BRW_GS_DISABLE                 0
  82 #define BRW_GS_ENABLE                  1
  83 #define BRW_CLIP_DISABLE               0
  84 #define BRW_CLIP_ENABLE                1
  85
  86 /* for BRW_PIPE_CONTROL */
  87 #define BRW_PIPE_CONTROL_NOWRITE       (0 << 14)
  88 #define BRW_PIPE_CONTROL_WRITE_QWORD   (1 << 14)
  89 #define BRW_PIPE_CONTROL_WRITE_DEPTH   (2 << 14)
  90 #define BRW_PIPE_CONTROL_WRITE_TIME    (3 << 14)
  91 #define BRW_PIPE_CONTROL_DEPTH_STALL   (1 << 13)
  92 #define BRW_PIPE_CONTROL_WC_FLUSH      (1 << 12)
  93 #define BRW_PIPE_CONTROL_IS_FLUSH      (1 << 11)
  94 #define BRW_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
  95 #define BRW_PIPE_CONTROL_GLOBAL_GTT    (1 << 2)
  96 #define BRW_PIPE_CONTROL_LOCAL_PGTT    (0 << 2)
  97
  98 /* VERTEX_BUFFER_STATE Structure */
  99 #define VB0_BUFFER_INDEX_SHIFT          27
 100 #define VB0_VERTEXDATA                  (0 << 26)
 101 #define VB0_INSTANCEDATA                (1 << 26)
 102 #define VB0_BUFFER_PITCH_SHIFT          0
 103
 104 /* VERTEX_ELEMENT_STATE Structure */
 105 #define VE0_VERTEX_BUFFER_INDEX_SHIFT   27
 106 #define VE0_VALID                       (1 << 26)
 107 #define VE0_FORMAT_SHIFT                16
 108 #define VE0_OFFSET_SHIFT                0
 109 #define VE1_VFCOMPONENT_0_SHIFT         28
 110 #define VE1_VFCOMPONENT_1_SHIFT         24
 111 #define VE1_VFCOMPONENT_2_SHIFT         20
 112 #define VE1_VFCOMPONENT_3_SHIFT         16
 113 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT    0
 114
 115 /* 3DPRIMITIVE bits */
 116 #define BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15)
 117 #define BRW_3DPRIMITIVE_VERTEX_RANDOM     (1 << 15)
 118 /* Primitive types are in brw_defines.h */
 119 #define BRW_3DPRIMITIVE_TOPOLOGY_SHIFT    10
 120
 121 #define BRW_SVG_CTL                    0x7400
 122
 123 #define BRW_SVG_CTL_GS_BA              (0 << 8)
 124 #define BRW_SVG_CTL_SS_BA              (1 << 8)
 125 #define BRW_SVG_CTL_IO_BA              (2 << 8)
 126 #define BRW_SVG_CTL_GS_AUB             (3 << 8)
 127 #define BRW_SVG_CTL_IO_AUB             (4 << 8)
 128 #define BRW_SVG_CTL_SIP                (5 << 8)
 129
 130 #define BRW_SVG_RDATA                  0x7404
 131 #define BRW_SVG_WORK_CTL               0x7408
 132
 133 #define BRW_VF_CTL                     0x7500
 134
 135 #define BRW_VF_CTL_SNAPSHOT_COMPLETE               (1 << 31)
 136 #define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_THREADID    (0 << 8)
 137 #define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_VF_DEBUG    (1 << 8)
 138 #define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_SEQUENCE   (0 << 4)
 139 #define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_INDEX      (1 << 4)
 140 #define BRW_VF_CTL_SKIP_INITIAL_PRIMITIVES         (1 << 3)
 141 #define BRW_VF_CTL_MAX_PRIMITIVES_LIMIT_ENABLE     (1 << 2)
 142 #define BRW_VF_CTL_VERTEX_RANGE_LIMIT_ENABLE       (1 << 1)
 143 #define BRW_VF_CTL_SNAPSHOT_ENABLE                 (1 << 0)
 144
 145 #define BRW_VF_STRG_VAL                0x7504
 146 #define BRW_VF_STR_VL_OVR              0x7508
 147 #define BRW_VF_VC_OVR                  0x750c
 148 #define BRW_VF_STR_PSKIP               0x7510
 149 #define BRW_VF_MAX_PRIM                0x7514
 150 #define BRW_VF_RDATA                   0x7518
 151
 152 #define BRW_VS_CTL                     0x7600
 153 #define BRW_VS_CTL_SNAPSHOT_COMPLETE               (1 << 31)
 154 #define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_0           (0 << 8)
 155 #define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_1           (1 << 8)
 156 #define BRW_VS_CTL_SNAPSHOT_MUX_VALID_COUNT        (2 << 8)
 157 #define BRW_VS_CTL_SNAPSHOT_MUX_VS_KERNEL_POINTER  (3 << 8)
 158 #define BRW_VS_CTL_SNAPSHOT_ALL_THREADS            (1 << 2)
 159 #define BRW_VS_CTL_THREAD_SNAPSHOT_ENABLE          (1 << 1)
 160 #define BRW_VS_CTL_SNAPSHOT_ENABLE                 (1 << 0)
 161
 162 #define BRW_VS_STRG_VAL                0x7604
 163 #define BRW_VS_RDATA                   0x7608
 164
 165 #define BRW_SF_CTL                     0x7b00
 166 #define BRW_SF_CTL_SNAPSHOT_COMPLETE               (1 << 31)
 167 #define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_FF_ID     (0 << 8)
 168 #define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_REL_COUNT (1 << 8)
 169 #define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_FF_ID     (2 << 8)
 170 #define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_REL_COUNT (3 << 8)
 171 #define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_FF_ID     (4 << 8)
 172 #define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_REL_COUNT (5 << 8)
 173 #define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_COUNT       (6 << 8)
 174 #define BRW_SF_CTL_SNAPSHOT_MUX_SF_KERNEL_POINTER  (7 << 8)
 175 #define BRW_SF_CTL_MIN_MAX_PRIMITIVE_RANGE_ENABLE  (1 << 4)
 176 #define BRW_SF_CTL_DEBUG_CLIP_RECTANGLE_ENABLE     (1 << 3)
 177 #define BRW_SF_CTL_SNAPSHOT_ALL_THREADS            (1 << 2)
 178 #define BRW_SF_CTL_THREAD_SNAPSHOT_ENABLE          (1 << 1)
 179 #define BRW_SF_CTL_SNAPSHOT_ENABLE                 (1 << 0)
 180
 181 #define BRW_SF_STRG_VAL                0x7b04
 182 #define BRW_SF_RDATA                   0x7b18
 183
 184 #define BRW_WIZ_CTL                    0x7c00
 185 #define BRW_WIZ_CTL_SNAPSHOT_COMPLETE              (1 << 31)
 186 #define BRW_WIZ_CTL_SUBSPAN_INSTANCE_SHIFT         16
 187 #define BRW_WIZ_CTL_SNAPSHOT_MUX_WIZ_KERNEL_POINTER   (0 << 8)
 188 #define BRW_WIZ_CTL_SNAPSHOT_MUX_SUBSPAN_INSTANCE     (1 << 8)
 189 #define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE   (2 << 8)
 190 #define BRW_WIZ_CTL_SINGLE_SUBSPAN_DISPATCH           (1 << 6)
 191 #define BRW_WIZ_CTL_IGNORE_COLOR_SCOREBOARD_STALLS    (1 << 5)
 192 #define BRW_WIZ_CTL_ENABLE_SUBSPAN_INSTANCE_COMPARE   (1 << 4)
 193 #define BRW_WIZ_CTL_USE_UPSTREAM_SNAPSHOT_FLAG        (1 << 3)
 194 #define BRW_WIZ_CTL_SNAPSHOT_ALL_THREADS              (1 << 2)
 195 #define BRW_WIZ_CTL_THREAD_SNAPSHOT_ENABLE            (1 << 1)
 196 #define BRW_WIZ_CTL_SNAPSHOT_ENABLE                   (1 << 0)
 197
 198 #define BRW_WIZ_STRG_VAL                              0x7c04
 199 #define BRW_WIZ_RDATA                                 0x7c18
 200
 201 #define BRW_TS_CTL                     0x7e00
 202 #define BRW_TS_CTL_SNAPSHOT_COMPLETE               (1 << 31)
 203 #define BRW_TS_CTL_SNAPSHOT_MESSAGE_ERROR          (0 << 8)
 204 #define BRW_TS_CTL_SNAPSHOT_INTERFACE_DESCRIPTOR   (3 << 8)
 205 #define BRW_TS_CTL_SNAPSHOT_ALL_CHILD_THREADS      (1 << 2)
 206 #define BRW_TS_CTL_SNAPSHOT_ALL_ROOT_THREADS       (1 << 1)
 207 #define BRW_TS_CTL_SNAPSHOT_ENABLE                 (1 << 0)
 208
 209 #define BRW_TS_STRG_VAL                0x7e04
 210 #define BRW_TS_RDATA                   0x7e08
 211
 212 #define BRW_TD_CTL                     0x8000
 213 #define BRW_TD_CTL_MUX_SHIFT           8
 214 #define BRW_TD_CTL_EXTERNAL_HALT_R0_DEBUG_MATCH    (1 << 7)
 215 #define BRW_TD_CTL_FORCE_EXTERNAL_HALT             (1 << 6)
 216 #define BRW_TD_CTL_EXCEPTION_MASK_OVERRIDE         (1 << 5)
 217 #define BRW_TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE  (1 << 4)
 218 #define BRW_TD_CTL_BREAKPOINT_ENABLE               (1 << 2)
 219 #define BRW_TD_CTL2                    0x8004
 220 #define BRW_TD_CTL2_ILLEGAL_OPCODE_EXCEPTION_OVERRIDE (1 << 28)
 221 #define BRW_TD_CTL2_MASKSTACK_EXCEPTION_OVERRIDE      (1 << 26)
 222 #define BRW_TD_CTL2_SOFTWARE_EXCEPTION_OVERRIDE       (1 << 25)
 223 #define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_SHIFT         16
 224 #define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_ENABLE        (1 << 8)
 225 #define BRW_TD_CTL2_THREAD_SPAWNER_EXECUTION_MASK_ENABLE (1 << 7)
 226 #define BRW_TD_CTL2_WIZ_EXECUTION_MASK_ENABLE         (1 << 6)
 227 #define BRW_TD_CTL2_SF_EXECUTION_MASK_ENABLE          (1 << 5)
 228 #define BRW_TD_CTL2_CLIPPER_EXECUTION_MASK_ENABLE     (1 << 4)
 229 #define BRW_TD_CTL2_GS_EXECUTION_MASK_ENABLE          (1 << 3)
 230 #define BRW_TD_CTL2_VS_EXECUTION_MASK_ENABLE          (1 << 0)
 231 #define BRW_TD_VF_VS_EMSK              0x8008
 232 #define BRW_TD_GS_EMSK                 0x800c
 233 #define BRW_TD_CLIP_EMSK               0x8010
 234 #define BRW_TD_SF_EMSK                 0x8014
 235 #define BRW_TD_WIZ_EMSK                0x8018
 236 #define BRW_TD_0_6_EHTRG_VAL           0x801c
 237 #define BRW_TD_0_7_EHTRG_VAL           0x8020
 238 #define BRW_TD_0_6_EHTRG_MSK           0x8024
 239 #define BRW_TD_0_7_EHTRG_MSK           0x8028
 240 #define BRW_TD_RDATA                   0x802c
 241 #define BRW_TD_TS_EMSK                 0x8030
 242
 243 #define BRW_EU_CTL                     0x8800
 244 #define BRW_EU_CTL_SELECT_SHIFT        16
 245 #define BRW_EU_CTL_DATA_MUX_SHIFT      8
 246 #define BRW_EU_ATT_0                   0x8810
 247 #define BRW_EU_ATT_1                   0x8814
 248 #define BRW_EU_ATT_DATA_0              0x8820
 249 #define BRW_EU_ATT_DATA_1              0x8824
 250 #define BRW_EU_ATT_CLR_0               0x8830
 251 #define BRW_EU_ATT_CLR_1               0x8834
 252 #define BRW_EU_RDATA                   0x8840
 253
 254 typedef struct i965_device i965_device_t;
 255 typedef struct i965_surface i965_surface_t;
 256 typedef struct i965_shader i965_shader_t;
 257 typedef struct i965_stream i965_stream_t;
 258
 259 struct i965_sf_state {
 260     cairo_hash_entry_t entry;
 261     uint32_t offset;
 262 };
 263
 264 cairo_private cairo_bool_t
 265 i965_sf_state_equal (const void *, const void *);
 266
 267 struct i965_cc_state {
 268     cairo_hash_entry_t entry;
 269     uint32_t offset;
 270 };
 271
 272 cairo_private cairo_bool_t
 273 i965_cc_state_equal (const void *, const void *);
 274
 275 struct i965_wm_kernel {
 276     cairo_hash_entry_t entry;
 277     uint32_t offset;
 278 };
 279
 280 struct i965_wm_state {
 281     cairo_hash_entry_t entry;
 282     uint32_t kernel;
 283     uint32_t sampler;
 284     uint32_t offset;
 285 };
 286
 287 cairo_private cairo_bool_t
 288 i965_wm_state_equal (const void *, const void *);
 289
 290 struct i965_wm_binding {
 291     cairo_hash_entry_t entry;
 292     uint32_t table[4];
 293     int size;
 294     uint32_t offset;
 295 };
 296
 297 cairo_private cairo_bool_t
 298 i965_wm_binding_equal (const void *, const void *);
 299
 300 struct i965_sampler {
 301     cairo_hash_entry_t entry;
 302     uint32_t offset;
 303 };
 304
 305 struct i965_vbo {
 306     struct i965_vbo *next;
 307     intel_bo_t *bo;
 308     unsigned int count;
 309 };
 310
 311 struct i965_surface {
 312     intel_surface_t intel;
 313
 314     uint32_t stream;
 315     uint32_t offset;
 316 };
 317
 318 struct i965_pending_relocation {
 319     uint32_t offset;
 320     uint32_t read_domains;
 321     uint32_t write_domain;
 322     uint32_t delta;
 323 };
 324
 325 struct i965_stream {
 326     uint32_t used;
 327     uint32_t committed;
 328     uint32_t size;
 329     uint8_t *data;
 330     uint32_t serial;
 331
 332     int num_pending_relocations;
 333     int max_pending_relocations;
 334     struct i965_pending_relocation *pending_relocations;
 335
 336     int num_relocations;
 337     int max_relocations;
 338     struct drm_i915_gem_relocation_entry *relocations;
 339 };
 340
 341 #define I965_BATCH_SIZE (16 * 4096)
 342 #define I965_GENERAL_SIZE (16 * 4096)
 343 #define I965_SURFACE_SIZE (32 * 4096)
 344 #define I965_VERTEX_SIZE (128 * 4096)
 345
 346 #define I965_TILING_DEFAULT I915_TILING_Y
 347
 348
 349 struct i965_device {
 350     intel_device_t intel;
 351
 352     cairo_bool_t is_g4x;
 353
 354     i965_shader_t *shader; /* note: only valid during geometry emission */
 355
 356     /* track state changes */
 357     struct i965_sf_state sf_state;
 358     struct i965_cc_state cc_state;
 359     struct i965_wm_state wm_state;
 360     struct i965_wm_binding wm_binding;
 361
 362     i965_surface_t *target;
 363     uint32_t target_offset;
 364
 365     intel_bo_t *source;
 366     uint32_t source_offset;
 367
 368     intel_bo_t *mask;
 369     uint32_t mask_offset;
 370
 371     intel_bo_t *clip;
 372     uint32_t clip_offset;
 373
 374     uint32_t draw_rectangle;
 375
 376     uint32_t vs_offset;
 377     uint32_t border_color_offset;
 378     cairo_hash_table_t *sf_states;
 379     cairo_hash_table_t *cc_states;
 380     cairo_hash_table_t *wm_kernels;
 381     cairo_hash_table_t *wm_states;
 382     cairo_hash_table_t *wm_bindings;
 383     cairo_hash_table_t *samplers;
 384     intel_bo_t *general_state;
 385
 386     cairo_freelist_t sf_freelist;
 387     cairo_freelist_t cc_freelist;
 388     cairo_freelist_t wm_kernel_freelist;
 389     cairo_freelist_t wm_state_freelist;
 390     cairo_freelist_t wm_binding_freelist;
 391     cairo_freelist_t sampler_freelist;
 392
 393     uint32_t vertex_type;
 394     uint32_t vertex_size;
 395     uint32_t rectangle_size;
 396     uint32_t last_vertex_size;
 397
 398     float *constants; /* 4 x matrix + 2 x source */
 399     unsigned constants_size;
 400     cairo_bool_t have_urb_fences;
 401
 402     i965_stream_t batch;
 403     uint8_t batch_base[I965_BATCH_SIZE];
 404     struct drm_i915_gem_relocation_entry batch_relocations[2048];
 405
 406     i965_stream_t surface;
 407     uint8_t surface_base[I965_SURFACE_SIZE];
 408     struct i965_pending_relocation surface_pending_relocations[1];
 409     struct drm_i915_gem_relocation_entry surface_relocations[1024];
 410
 411     i965_stream_t general;
 412     uint8_t general_base[I965_GENERAL_SIZE];
 413     struct i965_pending_relocation general_pending_relocations[1];
 414
 415     i965_stream_t vertex;
 416     uint8_t vertex_base[I965_VERTEX_SIZE];
 417     struct i965_pending_relocation vertex_pending_relocations[512];
 418
 419     struct {
 420         size_t gtt_size;
 421
 422         intel_bo_t *bo[1024];
 423         int count;
 424
 425         struct drm_i915_gem_exec_object2 exec[1024];
 426     } exec;
 427     cairo_list_t flush;
 428 };
 429
 430 typedef enum {
 431     VS_NONE = 0,
 432     VS_GLYPHS,
 433     VS_SPANS,
 434 } i965_vertex_shader_t;
 435
 436 typedef enum {
 437     FS_NONE = 0,
 438     FS_CONSTANT,
 439     FS_LINEAR,
 440     FS_RADIAL,
 441     FS_SURFACE,
 442     FS_GLYPHS,
 443     FS_SPANS,
 444 } i965_fragment_shader_t;
 445
 446 typedef enum {
 447     PATTERN_BASE,
 448     PATTERN_SOLID,
 449     PATTERN_LINEAR,
 450     PATTERN_RADIAL,
 451     PATTERN_SURFACE,
 452 } i965_shader_channel_t;
 453 #define PATTERN_NONE (i965_shader_channel_t)-1
 454
 455 struct i965_shader {
 456     i965_device_t *device;
 457     i965_surface_t *target;
 458
 459     cairo_operator_t op;
 460
 461     cairo_bool_t committed;
 462     cairo_bool_t need_combine;
 463
 464     float constants[4*8 + 2*8]; /* 4 x matrix + 2 x source */
 465     unsigned constants_size;
 466
 467     union i965_shader_channel {
 468         struct {
 469             i965_vertex_shader_t vertex;
 470             i965_fragment_shader_t fragment;
 471             i965_shader_channel_t pattern;
 472         } type;
 473         struct i965_shader_base {
 474             i965_vertex_shader_t vertex;
 475             i965_fragment_shader_t fragment;
 476             i965_shader_channel_t pattern;
 477
 478             uint32_t mode;
 479
 480             float constants[8];
 481             unsigned constants_size;
 482
 483             intel_bo_t *bo;
 484             cairo_format_t format;
 485             cairo_content_t content;
 486             int width, height, stride;
 487             int filter, extend;
 488             cairo_matrix_t matrix;
 489             cairo_bool_t has_component_alpha;
 490         } base;
 491         struct i965_shader_solid {
 492             struct i965_shader_base base;
 493         } solid;
 494         struct i965_shader_linear {
 495             struct i965_shader_base base;
 496         } linear;
 497         struct i965_shader_radial {
 498             struct i965_shader_base base;
 499         } radial;
 500         struct i965_shader_surface {
 501             struct i965_shader_base base;
 502             cairo_surface_t *surface;
 503         } surface;
 504     } source, mask, clip, dst;
 505
 506     jmp_buf unwind;
 507 };
 508
 509 enum i965_shader_linear_mode {
 510     /* XXX REFLECT */
 511     LINEAR_TEXTURE,
 512     LINEAR_NONE,
 513     LINEAR_REPEAT,
 514     LINEAR_PAD,
 515 };
 516
 517 enum i965_shader_radial_mode {
 518     RADIAL_ONE,
 519     RADIAL_TWO
 520 };
 521
 522 typedef cairo_status_t
 523 (*i965_spans_func_t) (void                      *closure,
 524                       cairo_span_renderer_t     *renderer,
 525                       const cairo_rectangle_int_t       *extents);
 526
 527 static inline i965_device_t *
 528 i965_device (i965_surface_t *surface)
 529 {
 530     return (i965_device_t *) surface->intel.drm.base.device;
 531 }
 532
 533 cairo_private void
 534 i965_emit_relocation (i965_device_t *device,
 535                       i965_stream_t *stream,
 536                       intel_bo_t *target,
 537                       uint32_t target_offset,
 538                       uint32_t read_domains,
 539                       uint32_t write_domain,
 540                       uint32_t offset);
 541
 542 static cairo_always_inline uint32_t
 543 i965_stream_emit (i965_stream_t *stream, const void *data, size_t size)
 544 {
 545     uint32_t offset;
 546
 547     offset = stream->used;
 548     assert (offset + size <= stream->size);
 549     memcpy (stream->data + offset, data, size);
 550     stream->used += size;
 551
 552     return offset;
 553 }
 554
 555 static cairo_always_inline void
 556 i965_stream_align (i965_stream_t *stream, uint32_t size)
 557 {
 558     stream->used = (stream->used + size - 1) & -size;
 559 }
 560
 561 static cairo_always_inline void *
 562 i965_stream_alloc (i965_stream_t *stream, uint32_t align, uint32_t size)
 563 {
 564     void *ptr;
 565
 566     if (align)
 567         i965_stream_align (stream, align);
 568
 569     assert (stream->used + size <= stream->size);
 570     ptr = stream->data + stream->used;
 571     stream->used += size;
 572
 573     return ptr;
 574 }
 575
 576 static cairo_always_inline uint32_t
 577 i965_stream_offsetof (i965_stream_t *stream, const void *ptr)
 578 {
 579     return (char *) ptr - (char *) stream->data;
 580 }
 581
 582 cairo_private void
 583 i965_stream_commit (i965_device_t *device,
 584                     i965_stream_t *stream);
 585
 586 cairo_private void
 587 i965_general_state_reset (i965_device_t *device);
 588
 589 static inline void
 590 i965_batch_emit_dword (i965_device_t *device, uint32_t dword)
 591 {
 592     *(uint32_t *) (device->batch.data + device->batch.used) = dword;
 593     device->batch.used += 4;
 594 }
 595
 596 #define OUT_BATCH(dword) i965_batch_emit_dword(device, dword)
 597
 598 cairo_private void
 599 i965_clipped_vertices (i965_device_t *device,
 600                        struct i965_vbo *vbo,
 601                        cairo_region_t *clip_region);
 602
 603 cairo_private void
 604 i965_flush_vertices (i965_device_t *device);
 605
 606 cairo_private void
 607 i965_finish_vertices (i965_device_t *device);
 608
 609 static inline float *
 610 i965_add_rectangle (i965_device_t *device)
 611 {
 612     float *vertices;
 613     uint32_t size;
 614
 615     size = device->rectangle_size;
 616     if (unlikely (device->vertex.used + size > device->vertex.size))
 617         i965_finish_vertices (device);
 618
 619     vertices = (float *) (device->vertex.data + device->vertex.used);
 620     device->vertex.used += size;
 621
 622     return vertices;
 623 }
 624
 625 static inline void
 626 i965_shader_add_rectangle (const i965_shader_t *shader,
 627                            int x, int y,
 628                            int w, int h)
 629 {
 630     float *v;
 631
 632     v= i965_add_rectangle (shader->device);
 633
 634     /* bottom-right */
 635     *v++ = x + w;
 636     *v++ = y + h;
 637
 638     /* bottom-left */
 639     *v++ = x;
 640     *v++ = y + h;
 641
 642     /* top-left */
 643     *v++ = x;
 644     *v++ = y;
 645 }
 646
 647 cairo_private cairo_surface_t *
 648 i965_surface_create_internal (cairo_drm_device_t *base_dev,
 649                               cairo_format_t format,
 650                               int width, int height,
 651                               uint32_t tiling,
 652                               cairo_bool_t gpu_target);
 653
 654 cairo_private cairo_status_t
 655 i965_clip_and_composite_spans (i965_surface_t           *dst,
 656                                cairo_operator_t          op,
 657                                const cairo_pattern_t    *pattern,
 658                                cairo_antialias_t         antialias,
 659                                i965_spans_func_t         draw_func,
 660                                void                     *draw_closure,
 661                                const cairo_composite_rectangles_t*extents,
 662                                cairo_clip_t             *clip);
 663
 664 cairo_private cairo_int_status_t
 665 i965_surface_glyphs (void                       *abstract_surface,
 666                      cairo_operator_t            op,
 667                      const cairo_pattern_t      *source,
 668                      cairo_glyph_t              *glyphs,
 669                      int                         num_glyphs,
 670                      cairo_scaled_font_t        *scaled_font,
 671                      cairo_clip_t               *clip,
 672                      int *num_remaining);
 673
 674 cairo_private void
 675 i965_shader_init (i965_shader_t *shader,
 676                   i965_surface_t *dst,
 677                   cairo_operator_t op);
 678
 679 cairo_private cairo_status_t
 680 i965_shader_acquire_pattern (i965_shader_t *shader,
 681                              union i965_shader_channel *src,
 682                              const cairo_pattern_t *pattern,
 683                              const cairo_rectangle_int_t *extents);
 684
 685 cairo_private void
 686 i965_shader_set_clip (i965_shader_t *shader,
 687                       cairo_clip_t *clip);
 688
 689 cairo_private cairo_status_t
 690 i965_shader_commit (i965_shader_t *shader,
 691                     i965_device_t *device);
 692
 693 cairo_private void
 694 i965_shader_fini (i965_shader_t *shader);
 695
 696 cairo_private cairo_status_t
 697 i965_device_flush (i965_device_t *device);
 698
 699 cairo_private cairo_status_t
 700 i965_fixup_unbounded (i965_surface_t *dst,
 701                       const cairo_composite_rectangles_t *extents,
 702                       cairo_clip_t *clip);
 703
 704 static inline int
 705 i965_filter (cairo_filter_t filter)
 706 {
 707     switch (filter) {
 708     default:
 709     case CAIRO_FILTER_FAST:
 710     case CAIRO_FILTER_NEAREST:
 711         return BRW_MAPFILTER_NEAREST;
 712
 713     case CAIRO_FILTER_GOOD:
 714     case CAIRO_FILTER_BEST:
 715     case CAIRO_FILTER_BILINEAR:
 716     case CAIRO_FILTER_GAUSSIAN:
 717         return BRW_MAPFILTER_LINEAR;
 718     }
 719 }
 720
 721 static inline int
 722 i965_extend (cairo_extend_t extend)
 723 {
 724     switch (extend) {
 725     default:
 726     case CAIRO_EXTEND_NONE:
 727         return BRW_TEXCOORDMODE_CLAMP_BORDER;
 728     case CAIRO_EXTEND_REPEAT:
 729         return BRW_TEXCOORDMODE_WRAP;
 730     case CAIRO_EXTEND_PAD:
 731         return BRW_TEXCOORDMODE_CLAMP;
 732     case CAIRO_EXTEND_REFLECT:
 733         return BRW_TEXCOORDMODE_MIRROR;
 734     }
 735 }
 736
 737 #endif /* CAIRO_DRM_I965_PRIVATE_H */