1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
12 // ARM64-specific opcodes that specify which assembly sequence to emit.
13 // Most opcodes specify a single instruction.
14 #define TARGET_ARCH_OPCODE_LIST(V) \
77 V(Arm64PokePairZero) \
86 V(Arm64Float64Floor) \
88 V(Arm64Float64RoundTruncate) \
89 V(Arm64Float64RoundTiesAway) \
90 V(Arm64Float32ToFloat64) \
91 V(Arm64Float64ToFloat32) \
92 V(Arm64Float64ToInt32) \
93 V(Arm64Float64ToUint32) \
94 V(Arm64Int32ToFloat64) \
95 V(Arm64Uint32ToFloat64) \
110 V(Arm64StoreWriteBarrier)
113 // Addressing modes represent the "shape" of inputs to an instruction.
114 // Many instructions support multiple addressing modes. Addressing modes
115 // are encoded into the InstructionCode of the instruction and tell the
116 // code generator after register allocation which assembler method to call.
118 // We use the following local notation for addressing modes:
121 // O = register or stack slot
122 // D = double register
123 // I = immediate (handle, external, int32)
124 // MRI = [register + immediate]
125 // MRR = [register + register]
126 #define TARGET_ADDRESSING_MODE_LIST(V) \
127 V(MRI) /* [%r0 + K] */ \
128 V(MRR) /* [%r0 + %r1] */ \
129 V(Operand2_R_LSL_I) /* %r0 LSL K */ \
130 V(Operand2_R_LSR_I) /* %r0 LSR K */ \
131 V(Operand2_R_ASR_I) /* %r0 ASR K */ \
132 V(Operand2_R_ROR_I) /* %r0 ROR K */
134 } // namespace internal
135 } // namespace compiler
138 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_