src/compiler/arm64/instruction-codes-arm64.h

   1 // Copyright 2014 the V8 project authors. All rights reserved.
   2 // Use of this source code is governed by a BSD-style license that can be
   3 // found in the LICENSE file.
   4
   5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
   6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
   7
   8 namespace v8 {
   9 namespace internal {
  10 namespace compiler {
  11
  12 // ARM64-specific opcodes that specify which assembly sequence to emit.
  13 // Most opcodes specify a single instruction.
  14 #define TARGET_ARCH_OPCODE_LIST(V) \
  15   V(Arm64Add)                      \
  16   V(Arm64Add32)                    \
  17   V(Arm64And)                      \
  18   V(Arm64And32)                    \
  19   V(Arm64Bic)                      \
  20   V(Arm64Bic32)                    \
  21   V(Arm64Cmp)                      \
  22   V(Arm64Cmp32)                    \
  23   V(Arm64Cmn)                      \
  24   V(Arm64Cmn32)                    \
  25   V(Arm64Tst)                      \
  26   V(Arm64Tst32)                    \
  27   V(Arm64Or)                       \
  28   V(Arm64Or32)                     \
  29   V(Arm64Orn)                      \
  30   V(Arm64Orn32)                    \
  31   V(Arm64Eor)                      \
  32   V(Arm64Eor32)                    \
  33   V(Arm64Eon)                      \
  34   V(Arm64Eon32)                    \
  35   V(Arm64Sub)                      \
  36   V(Arm64Sub32)                    \
  37   V(Arm64Mul)                      \
  38   V(Arm64Mul32)                    \
  39   V(Arm64Madd)                     \
  40   V(Arm64Madd32)                   \
  41   V(Arm64Msub)                     \
  42   V(Arm64Msub32)                   \
  43   V(Arm64Mneg)                     \
  44   V(Arm64Mneg32)                   \
  45   V(Arm64Idiv)                     \
  46   V(Arm64Idiv32)                   \
  47   V(Arm64Udiv)                     \
  48   V(Arm64Udiv32)                   \
  49   V(Arm64Imod)                     \
  50   V(Arm64Imod32)                   \
  51   V(Arm64Umod)                     \
  52   V(Arm64Umod32)                   \
  53   V(Arm64Not)                      \
  54   V(Arm64Not32)                    \
  55   V(Arm64Neg)                      \
  56   V(Arm64Neg32)                    \
  57   V(Arm64Shl)                      \
  58   V(Arm64Shl32)                    \
  59   V(Arm64Shr)                      \
  60   V(Arm64Shr32)                    \
  61   V(Arm64Sar)                      \
  62   V(Arm64Sar32)                    \
  63   V(Arm64Ror)                      \
  64   V(Arm64Ror32)                    \
  65   V(Arm64Mov32)                    \
  66   V(Arm64Sxtw)                     \
  67   V(Arm64Claim)                    \
  68   V(Arm64Poke)                     \
  69   V(Arm64PokePairZero)             \
  70   V(Arm64PokePair)                 \
  71   V(Arm64Float64Cmp)               \
  72   V(Arm64Float64Add)               \
  73   V(Arm64Float64Sub)               \
  74   V(Arm64Float64Mul)               \
  75   V(Arm64Float64Div)               \
  76   V(Arm64Float64Mod)               \
  77   V(Arm64Float64Sqrt)              \
  78   V(Arm64Float32ToFloat64)         \
  79   V(Arm64Float64ToFloat32)         \
  80   V(Arm64Float64ToInt32)           \
  81   V(Arm64Float64ToUint32)          \
  82   V(Arm64Int32ToFloat64)           \
  83   V(Arm64Uint32ToFloat64)          \
  84   V(Arm64LdrS)                     \
  85   V(Arm64StrS)                     \
  86   V(Arm64LdrD)                     \
  87   V(Arm64StrD)                     \
  88   V(Arm64Ldrb)                     \
  89   V(Arm64Ldrsb)                    \
  90   V(Arm64Strb)                     \
  91   V(Arm64Ldrh)                     \
  92   V(Arm64Ldrsh)                    \
  93   V(Arm64Strh)                     \
  94   V(Arm64LdrW)                     \
  95   V(Arm64StrW)                     \
  96   V(Arm64Ldr)                      \
  97   V(Arm64Str)                      \
  98   V(Arm64StoreWriteBarrier)
  99
 100
 101 // Addressing modes represent the "shape" of inputs to an instruction.
 102 // Many instructions support multiple addressing modes. Addressing modes
 103 // are encoded into the InstructionCode of the instruction and tell the
 104 // code generator after register allocation which assembler method to call.
 105 //
 106 // We use the following local notation for addressing modes:
 107 //
 108 // R = register
 109 // O = register or stack slot
 110 // D = double register
 111 // I = immediate (handle, external, int32)
 112 // MRI = [register + immediate]
 113 // MRR = [register + register]
 114 #define TARGET_ADDRESSING_MODE_LIST(V) \
 115   V(MRI) /* [%r0 + K] */               \
 116   V(MRR) /* [%r0 + %r1] */
 117
 118 }  // namespace internal
 119 }  // namespace compiler
 120 }  // namespace v8
 121
 122 #endif  // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_