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26 * \file common_capability.c
27 * Platform independent PCI capability related routines.
29 * In addition to including the interface glue for \c pci_device_get_agp_info,
30 * this file also contains a generic implementation of that function.
32 * \author Ian Romanick <idr@us.ibm.com>
39 #include "pciaccess.h"
40 #include "pciaccess_private.h"
43 * Generic implementation of \c pci_system_methods::fill_capabilities.
45 * \param dev Device whose capability information is to be processed.
48 * Zero on success or an errno value on failure.
51 * Once more than just the AGP capability is supported, the body of each of
52 * the cases in the capability processing loop should probably be broken out
53 * into its own function.
56 * Once more than just the AGP capability is supported, some care will need
57 * to be taken in partial failure cases. If, say, the first capability is
58 * correctly processed but the second fails, the function would be re-called
59 * later to try again for the second capability. This could lead to memory
60 * leaks or other quirky behavior.
63 pci_fill_capabilities_generic( struct pci_device * dev )
65 struct pci_device_private * const dev_priv =
66 (struct pci_device_private *) dev;
72 err = pci_device_cfg_read_u16( dev, & status, 6 );
77 /* Are PCI capabilities supported by this device?
79 if ( (status & 0x0010) == 0 ) {
83 err = pci_device_cfg_read_u8( dev, & cap_offset, 52 );
89 /* Process each of the capabilities list in the PCI header.
91 while ( cap_offset != 0 ) {
95 err = pci_device_cfg_read_u8( dev, & cap_id, cap_offset );
100 err = pci_device_cfg_read_u8( dev, & next_cap, cap_offset + 1 );
107 struct pci_agp_info * agp_info;
112 err = pci_device_cfg_read_u8( dev, & agp_ver, cap_offset + 2 );
117 err = pci_device_cfg_read_u32( dev, & agp_status, cap_offset + 4 );
122 agp_info = calloc( 1, sizeof( struct pci_agp_info ) );
123 if ( agp_info == NULL ) {
127 agp_info->config_offset = cap_offset;
129 agp_info->major_version = (agp_ver & 0x0f0) >> 4;
130 agp_info->minor_version = (agp_ver & 0x00f);
132 agp_info->rates = (agp_status & 0x07);
134 /* If AGP3 is supported, then the meaning of the rates values
137 if ( (agp_status & 0x08) != 0 ) {
138 agp_info->rates <<= 2;
141 /* Some devices, notably motherboard chipsets, have the AGP3
142 * capability set and the 4x bit set. This results in an
143 * impossible 16x mode being listed as available. I'm not 100%
144 * sure this is the right solution.
146 agp_info->rates &= 0x0f;
149 agp_info->fast_writes = (agp_status & 0x0010) != 0;
150 agp_info->addr64 = (agp_status & 0x0020) != 0;
151 agp_info->htrans = (agp_status & 0x0040) == 0;
152 agp_info->gart64 = (agp_status & 0x0080) != 0;
153 agp_info->coherent = (agp_status & 0x0100) != 0;
154 agp_info->sideband = (agp_status & 0x0200) != 0;
155 agp_info->isochronus = (agp_status & 0x10000) != 0;
157 agp_info->async_req_size = 4 + (1 << ((agp_status & 0xe000) >> 13));
158 agp_info->calibration_cycle_timing = ((agp_status & 0x1c00) >> 10);
159 agp_info->max_requests = 1 + ((agp_status & 0xff000000) >> 24);
161 dev_priv->agp = agp_info;
165 /* No other capabilities are currently handled.
168 printf( "Unknown cap 0x%02x @ 0x%02x\n", cap_id, cap_offset );
172 cap_offset = next_cap;
180 * Get AGP capability data for a device.
182 const struct pci_agp_info *
183 pci_device_get_agp_info( struct pci_device * dev )
185 struct pci_device_private * dev_priv = (struct pci_device_private *) dev;
191 if ( dev_priv->agp == NULL ) {
192 (void) (*pci_sys->methods->fill_capabilities)( dev );
195 return dev_priv->agp;