1 // Copyright 2010 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 // This file is an internal atomic implementation, use atomicops.h instead.
7 #ifndef V8_BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
8 #define V8_BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
13 // This struct is not part of the public API of this module; clients may not
15 // Features of this x86. Values may not be correct before main() is run,
16 // but are set conservatively.
17 struct AtomicOps_x86CPUFeatureStruct {
18 bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
19 // after acquire compare-and-swap.
20 #if !defined(__SSE2__)
21 bool has_sse2; // Processor has SSE2.
24 extern struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures;
26 #define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
28 // 32-bit low-level operations on any platform.
30 inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
34 __asm__ __volatile__("lock; cmpxchgl %1,%2"
36 : "q" (new_value), "m" (*ptr), "0" (old_value)
41 inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
43 __asm__ __volatile__("xchgl %1,%0" // The lock prefix is implicit for xchg.
45 : "m" (*ptr), "0" (new_value)
47 return new_value; // Now it's the previous value.
50 inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
52 Atomic32 temp = increment;
53 __asm__ __volatile__("lock; xaddl %0,%1"
54 : "+r" (temp), "+m" (*ptr)
56 // temp now holds the old value of *ptr
57 return temp + increment;
60 inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
62 Atomic32 temp = increment;
63 __asm__ __volatile__("lock; xaddl %0,%1"
64 : "+r" (temp), "+m" (*ptr)
66 // temp now holds the old value of *ptr
67 if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
68 __asm__ __volatile__("lfence" : : : "memory");
70 return temp + increment;
73 inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
76 Atomic32 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
77 if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
78 __asm__ __volatile__("lfence" : : : "memory");
83 inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
86 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
89 inline void NoBarrier_Store(volatile Atomic8* ptr, Atomic8 value) {
93 inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
97 #if defined(__x86_64__) || defined(__SSE2__)
99 // 64-bit implementations of memory barrier can be simpler, because it
100 // "mfence" is guaranteed to exist.
101 inline void MemoryBarrier() {
102 __asm__ __volatile__("mfence" : : : "memory");
105 inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
112 inline void MemoryBarrier() {
113 if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
114 __asm__ __volatile__("mfence" : : : "memory");
115 } else { // mfence is faster but not present on PIII
117 NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
121 inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
122 if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
124 __asm__ __volatile__("mfence" : : : "memory");
126 NoBarrier_AtomicExchange(ptr, value);
127 // acts as a barrier on PIII
132 inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
133 ATOMICOPS_COMPILER_BARRIER();
134 *ptr = value; // An x86 store acts as a release barrier.
135 // See comments in Atomic64 version of Release_Store(), below.
138 inline Atomic8 NoBarrier_Load(volatile const Atomic8* ptr) {
142 inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
146 inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
147 Atomic32 value = *ptr; // An x86 load acts as a acquire barrier.
148 // See comments in Atomic64 version of Release_Store(), below.
149 ATOMICOPS_COMPILER_BARRIER();
153 inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
158 #if defined(__x86_64__) && defined(V8_HOST_ARCH_64_BIT)
160 // 64-bit low-level operations on 64-bit platform.
162 inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
164 Atomic64 new_value) {
166 __asm__ __volatile__("lock; cmpxchgq %1,%2"
168 : "q" (new_value), "m" (*ptr), "0" (old_value)
173 inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
174 Atomic64 new_value) {
175 __asm__ __volatile__("xchgq %1,%0" // The lock prefix is implicit for xchg.
177 : "m" (*ptr), "0" (new_value)
179 return new_value; // Now it's the previous value.
182 inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
183 Atomic64 increment) {
184 Atomic64 temp = increment;
185 __asm__ __volatile__("lock; xaddq %0,%1"
186 : "+r" (temp), "+m" (*ptr)
188 // temp now contains the previous value of *ptr
189 return temp + increment;
192 inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
193 Atomic64 increment) {
194 Atomic64 temp = increment;
195 __asm__ __volatile__("lock; xaddq %0,%1"
196 : "+r" (temp), "+m" (*ptr)
198 // temp now contains the previous value of *ptr
199 if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
200 __asm__ __volatile__("lfence" : : : "memory");
202 return temp + increment;
205 inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
209 inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
214 inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
215 ATOMICOPS_COMPILER_BARRIER();
217 *ptr = value; // An x86 store acts as a release barrier
218 // for current AMD/Intel chips as of Jan 2008.
219 // See also Acquire_Load(), below.
221 // When new chips come out, check:
222 // IA-32 Intel Architecture Software Developer's Manual, Volume 3:
223 // System Programming Guide, Chatper 7: Multiple-processor management,
224 // Section 7.2, Memory Ordering.
226 // http://developer.intel.com/design/pentium4/manuals/index_new.htm
228 // x86 stores/loads fail to act as barriers for a few instructions (clflush
229 // maskmovdqu maskmovq movntdq movnti movntpd movntps movntq) but these are
230 // not generated by the compiler, and are rare. Users of these instructions
231 // need to know about cache behaviour in any case since all of these involve
232 // either flushing cache lines or non-temporal cache hints.
235 inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
239 inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
240 Atomic64 value = *ptr; // An x86 load acts as a acquire barrier,
241 // for current AMD/Intel chips as of Jan 2008.
242 // See also Release_Store(), above.
243 ATOMICOPS_COMPILER_BARRIER();
247 inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
252 inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
254 Atomic64 new_value) {
255 Atomic64 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
256 if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
257 __asm__ __volatile__("lfence" : : : "memory");
262 inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
264 Atomic64 new_value) {
265 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
268 #endif // defined(__x86_64__)
273 #undef ATOMICOPS_COMPILER_BARRIER
275 #endif // V8_BASE_ATOMICOPS_INTERNALS_X86_GCC_H_