2 // Copyright © 2017 Arm Ltd. All rights reserved.
3 // SPDX-License-Identifier: MIT
7 #include <armnn/Tensor.hpp>
14 template <typename QueueDescriptor>
15 void AddInputToWorkload(QueueDescriptor& descriptor,
16 armnn::WorkloadInfo& info,
17 const armnn::TensorInfo& tensorInfo,
18 armnn::ITensorHandle* tensorHandle)
20 descriptor.m_Inputs.push_back(tensorHandle);
21 info.m_InputTensorInfos.push_back(tensorInfo);
24 template <typename QueueDescriptor>
25 void AddOutputToWorkload(QueueDescriptor& descriptor,
26 armnn::WorkloadInfo& info,
27 const armnn::TensorInfo& tensorInfo,
28 armnn::ITensorHandle* tensorHandle)
30 descriptor.m_Outputs.push_back(tensorHandle);
31 info.m_OutputTensorInfos.push_back(tensorInfo);
34 template <typename QueueDescriptor>
35 void SetWorkloadInput(QueueDescriptor& descriptor,
36 armnn::WorkloadInfo& info,
38 const armnn::TensorInfo& tensorInfo,
39 armnn::ITensorHandle* tensorHandle)
41 descriptor.m_Inputs[index] = tensorHandle;
42 info.m_InputTensorInfos[index] = tensorInfo;
45 template <typename QueueDescriptor>
46 void SetWorkloadOutput(QueueDescriptor& descriptor,
47 armnn::WorkloadInfo& info,
49 const armnn::TensorInfo& tensorInfo,
50 armnn::ITensorHandle* tensorHandle)
52 descriptor.m_Outputs[index] = tensorHandle;
53 info.m_OutputTensorInfos[index] = tensorInfo;