2 * Copyright (c) 2003 Hewlett-Packard Development Company, L.P.
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * Derived from the corresponsing header file for gcc.
26 #include "../atomic_load_store.h"
28 /* Some architecture set descriptions include special "ordered" memory */
29 /* operations. As far as we can tell, no existing processors actually */
30 /* require those. Nor does it appear likely that future processors */
33 /* The PA emulator on Itanium may obey weaker restrictions. */
34 /* There should be a mode in which we don't assume sequential */
35 /* consistency here. */
36 #include "../ordered.h"
38 #include <machine/inline.h>
40 /* GCC will not guarantee the alignment we need, use four lock words */
41 /* and select the correctly aligned datum. See the glibc 2.3.2 */
42 /* linuxthread port for the original implementation. */
43 struct AO_pa_clearable_loc {
47 #undef AO_TS_INITIALIZER
48 #define AO_TS_t struct AO_pa_clearable_loc
49 #define AO_TS_INITIALIZER {1,1,1,1}
50 /* Switch meaning of set and clear, since we only have an atomic clear */
52 typedef enum {AO_PA_TS_set = 0, AO_PA_TS_clear = 1} AO_PA_TS_val;
53 #define AO_TS_VAL_t AO_PA_TS_val
54 #define AO_TS_CLEAR AO_PA_TS_clear
55 #define AO_TS_SET AO_PA_TS_set
57 /* The hppa only has one atomic read and modify memory operation, */
58 /* load and clear, so hppa spinlocks must use zero to signify that */
59 /* someone is holding the lock. The address used for the ldcw */
60 /* semaphore must be 16-byte aligned. */
62 #define __ldcw(a, ret) \
63 _LDCWX(0 /* index */, 0 /* s */, a /* base */, ret);
65 /* Because malloc only guarantees 8-byte alignment for malloc'd data, */
66 /* and GCC only guarantees 8-byte alignment for stack locals, we can't */
67 /* be assured of 16-byte alignment for atomic lock data even if we */
68 /* specify "__attribute ((aligned(16)))" in the type declaration. So, */
69 /* we use a struct containing an array of four ints for the atomic lock */
70 /* type and dynamically select the 16-byte aligned int from the array */
71 /* for the semaphore. */
72 #define __PA_LDCW_ALIGNMENT 16
74 #define __ldcw_align(a, ret) { \
75 ret = (unsigned long) a; \
76 ret += __PA_LDCW_ALIGNMENT - 1; \
77 ret &= ~(__PA_LDCW_ALIGNMENT - 1); \
80 /* Works on PA 1.1 and PA 2.0 systems */
82 AO_test_and_set_full(volatile AO_TS_t * addr)
84 register unsigned int ret;
85 register unsigned long a;
86 __ldcw_align (addr, a);
92 AO_pa_clear(volatile AO_TS_t * addr)
95 __ldcw_align (addr,a);
96 AO_compiler_barrier();
97 *(volatile unsigned int *)a = 1;
99 #define AO_CLEAR(addr) AO_pa_clear(addr)
101 #define AO_HAVE_test_and_set_full