1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 #ifndef V8_ARM64_INSTRUCTIONS_ARM64_H_
6 #define V8_ARM64_INSTRUCTIONS_ARM64_H_
8 #include "src/arm64/constants-arm64.h"
9 #include "src/arm64/utils-arm64.h"
10 #include "src/globals.h"
11 #include "src/utils.h"
17 // ISA constants. --------------------------------------------------------------
19 typedef uint32_t Instr;
21 // The following macros initialize a float/double variable with a bit pattern
22 // without using static initializers: If ARM64_DEFINE_FP_STATICS is defined, the
23 // symbol is defined as uint32_t/uint64_t initialized with the desired bit
24 // pattern. Otherwise, the same symbol is declared as an external float/double.
25 #if defined(ARM64_DEFINE_FP_STATICS)
26 #define DEFINE_FLOAT(name, value) extern const uint32_t name = value
27 #define DEFINE_DOUBLE(name, value) extern const uint64_t name = value
29 #define DEFINE_FLOAT(name, value) extern const float name
30 #define DEFINE_DOUBLE(name, value) extern const double name
31 #endif // defined(ARM64_DEFINE_FP_STATICS)
33 DEFINE_FLOAT(kFP32PositiveInfinity, 0x7f800000);
34 DEFINE_FLOAT(kFP32NegativeInfinity, 0xff800000);
35 DEFINE_DOUBLE(kFP64PositiveInfinity, 0x7ff0000000000000UL);
36 DEFINE_DOUBLE(kFP64NegativeInfinity, 0xfff0000000000000UL);
38 // This value is a signalling NaN as both a double and as a float (taking the
39 // least-significant word).
40 DEFINE_DOUBLE(kFP64SignallingNaN, 0x7ff000007f800001);
41 DEFINE_FLOAT(kFP32SignallingNaN, 0x7f800001);
43 // A similar value, but as a quiet NaN.
44 DEFINE_DOUBLE(kFP64QuietNaN, 0x7ff800007fc00001);
45 DEFINE_FLOAT(kFP32QuietNaN, 0x7fc00001);
47 // The default NaN values (for FPCR.DN=1).
48 DEFINE_DOUBLE(kFP64DefaultNaN, 0x7ff8000000000000UL);
49 DEFINE_FLOAT(kFP32DefaultNaN, 0x7fc00000);
62 LSDataSize CalcLSPairDataSize(LoadStorePairOp op);
65 UnknownBranchType = 0,
68 CompareBranchType = 3,
79 // The first four values are encodable directly by FPCR<RMode>.
81 FPPositiveInfinity = 0x1,
82 FPNegativeInfinity = 0x2,
85 // The final rounding mode is only available when explicitly specified by the
86 // instruction (such as with fcvta). It cannot be set in FPCR.
95 // Instructions. ---------------------------------------------------------------
99 V8_INLINE Instr InstructionBits() const {
100 return *reinterpret_cast<const Instr*>(this);
103 V8_INLINE void SetInstructionBits(Instr new_instr) {
104 *reinterpret_cast<Instr*>(this) = new_instr;
107 int Bit(int pos) const {
108 return (InstructionBits() >> pos) & 1;
111 uint32_t Bits(int msb, int lsb) const {
112 return unsigned_bitextract_32(msb, lsb, InstructionBits());
115 int32_t SignedBits(int msb, int lsb) const {
116 int32_t bits = *(reinterpret_cast<const int32_t*>(this));
117 return signed_bitextract_32(msb, lsb, bits);
120 Instr Mask(uint32_t mask) const {
121 return InstructionBits() & mask;
124 V8_INLINE const Instruction* following(int count = 1) const {
125 return InstructionAtOffset(count * static_cast<int>(kInstructionSize));
128 V8_INLINE Instruction* following(int count = 1) {
129 return InstructionAtOffset(count * static_cast<int>(kInstructionSize));
132 V8_INLINE const Instruction* preceding(int count = 1) const {
133 return following(-count);
136 V8_INLINE Instruction* preceding(int count = 1) {
137 return following(-count);
140 #define DEFINE_GETTER(Name, HighBit, LowBit, Func) \
141 int32_t Name() const { return Func(HighBit, LowBit); }
142 INSTRUCTION_FIELDS_LIST(DEFINE_GETTER)
145 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST),
146 // formed from ImmPCRelLo and ImmPCRelHi.
147 int ImmPCRel() const {
148 DCHECK(IsPCRelAddressing());
149 int offset = ((ImmPCRelHi() << ImmPCRelLo_width) | ImmPCRelLo());
150 int width = ImmPCRelLo_width + ImmPCRelHi_width;
151 return signed_bitextract_32(width - 1, 0, offset);
154 uint64_t ImmLogical();
158 LSDataSize SizeLSPair() const {
159 return CalcLSPairDataSize(
160 static_cast<LoadStorePairOp>(Mask(LoadStorePairMask)));
164 bool IsCondBranchImm() const {
165 return Mask(ConditionalBranchFMask) == ConditionalBranchFixed;
168 bool IsUncondBranchImm() const {
169 return Mask(UnconditionalBranchFMask) == UnconditionalBranchFixed;
172 bool IsCompareBranch() const {
173 return Mask(CompareBranchFMask) == CompareBranchFixed;
176 bool IsTestBranch() const {
177 return Mask(TestBranchFMask) == TestBranchFixed;
180 bool IsImmBranch() const {
181 return BranchType() != UnknownBranchType;
184 bool IsLdrLiteral() const {
185 return Mask(LoadLiteralFMask) == LoadLiteralFixed;
188 bool IsLdrLiteralX() const {
189 return Mask(LoadLiteralMask) == LDR_x_lit;
192 bool IsPCRelAddressing() const {
193 return Mask(PCRelAddressingFMask) == PCRelAddressingFixed;
197 return Mask(PCRelAddressingMask) == ADR;
200 bool IsBrk() const { return Mask(ExceptionMask) == BRK; }
202 bool IsUnresolvedInternalReference() const {
203 // Unresolved internal references are encoded as two consecutive brk
205 return IsBrk() && following()->IsBrk();
208 bool IsLogicalImmediate() const {
209 return Mask(LogicalImmediateFMask) == LogicalImmediateFixed;
212 bool IsAddSubImmediate() const {
213 return Mask(AddSubImmediateFMask) == AddSubImmediateFixed;
216 bool IsAddSubShifted() const {
217 return Mask(AddSubShiftedFMask) == AddSubShiftedFixed;
220 bool IsAddSubExtended() const {
221 return Mask(AddSubExtendedFMask) == AddSubExtendedFixed;
224 // Match any loads or stores, including pairs.
225 bool IsLoadOrStore() const {
226 return Mask(LoadStoreAnyFMask) == LoadStoreAnyFixed;
229 // Match any loads, including pairs.
231 // Match any stores, including pairs.
232 bool IsStore() const;
234 // Indicate whether Rd can be the stack pointer or the zero register. This
235 // does not check that the instruction actually has an Rd field.
236 Reg31Mode RdMode() const {
237 // The following instructions use csp or wsp as Rd:
238 // Add/sub (immediate) when not setting the flags.
239 // Add/sub (extended) when not setting the flags.
240 // Logical (immediate) when not setting the flags.
241 // Otherwise, r31 is the zero register.
242 if (IsAddSubImmediate() || IsAddSubExtended()) {
243 if (Mask(AddSubSetFlagsBit)) {
244 return Reg31IsZeroRegister;
246 return Reg31IsStackPointer;
249 if (IsLogicalImmediate()) {
250 // Of the logical (immediate) instructions, only ANDS (and its aliases)
251 // can set the flags. The others can all write into csp.
252 // Note that some logical operations are not available to
253 // immediate-operand instructions, so we have to combine two masks here.
254 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) {
255 return Reg31IsZeroRegister;
257 return Reg31IsStackPointer;
260 return Reg31IsZeroRegister;
263 // Indicate whether Rn can be the stack pointer or the zero register. This
264 // does not check that the instruction actually has an Rn field.
265 Reg31Mode RnMode() const {
266 // The following instructions use csp or wsp as Rn:
267 // All loads and stores.
268 // Add/sub (immediate).
269 // Add/sub (extended).
270 // Otherwise, r31 is the zero register.
271 if (IsLoadOrStore() || IsAddSubImmediate() || IsAddSubExtended()) {
272 return Reg31IsStackPointer;
274 return Reg31IsZeroRegister;
277 ImmBranchType BranchType() const {
278 if (IsCondBranchImm()) {
279 return CondBranchType;
280 } else if (IsUncondBranchImm()) {
281 return UncondBranchType;
282 } else if (IsCompareBranch()) {
283 return CompareBranchType;
284 } else if (IsTestBranch()) {
285 return TestBranchType;
287 return UnknownBranchType;
291 static int ImmBranchRangeBitwidth(ImmBranchType branch_type) {
292 switch (branch_type) {
293 case UncondBranchType:
294 return ImmUncondBranch_width;
296 return ImmCondBranch_width;
297 case CompareBranchType:
298 return ImmCmpBranch_width;
300 return ImmTestBranch_width;
307 // The range of the branch instruction, expressed as 'instr +- range'.
308 static int32_t ImmBranchRange(ImmBranchType branch_type) {
310 (1 << (ImmBranchRangeBitwidth(branch_type) + kInstructionSizeLog2)) / 2 -
314 int ImmBranch() const {
315 switch (BranchType()) {
316 case CondBranchType: return ImmCondBranch();
317 case UncondBranchType: return ImmUncondBranch();
318 case CompareBranchType: return ImmCmpBranch();
319 case TestBranchType: return ImmTestBranch();
320 default: UNREACHABLE();
325 int ImmUnresolvedInternalReference() const {
326 DCHECK(IsUnresolvedInternalReference());
327 // Unresolved references are encoded as two consecutive brk instructions.
328 // The associated immediate is made of the two 16-bit payloads.
329 int32_t high16 = ImmException();
330 int32_t low16 = following()->ImmException();
331 return (high16 << 16) | low16;
334 bool IsBranchAndLinkToRegister() const {
335 return Mask(UnconditionalBranchToRegisterMask) == BLR;
338 bool IsMovz() const {
339 return (Mask(MoveWideImmediateMask) == MOVZ_x) ||
340 (Mask(MoveWideImmediateMask) == MOVZ_w);
343 bool IsMovk() const {
344 return (Mask(MoveWideImmediateMask) == MOVK_x) ||
345 (Mask(MoveWideImmediateMask) == MOVK_w);
348 bool IsMovn() const {
349 return (Mask(MoveWideImmediateMask) == MOVN_x) ||
350 (Mask(MoveWideImmediateMask) == MOVN_w);
354 // A marking nop is an instruction
356 // which is encoded as
357 // orr r<n>, xzr, r<n>
358 return (Mask(LogicalShiftedMask) == ORR_x) &&
363 // Find the PC offset encoded in this instruction. 'this' may be a branch or
364 // a PC-relative addressing instruction.
365 // The offset returned is unscaled.
366 int64_t ImmPCOffset();
368 // Find the target of this instruction. 'this' may be a branch or a
369 // PC-relative addressing instruction.
370 Instruction* ImmPCOffsetTarget();
372 static bool IsValidImmPCOffset(ImmBranchType branch_type, ptrdiff_t offset);
373 bool IsTargetInImmPCOffsetRange(Instruction* target);
374 // Patch a PC-relative offset to refer to 'target'. 'this' may be a branch or
375 // a PC-relative addressing instruction.
376 void SetImmPCOffsetTarget(Instruction* target);
377 void SetUnresolvedInternalReferenceImmTarget(Instruction* target);
378 // Patch a literal load instruction to load from 'source'.
379 void SetImmLLiteral(Instruction* source);
381 uintptr_t LiteralAddress() {
382 int offset = ImmLLiteral() << kLoadLiteralScaleLog2;
383 return reinterpret_cast<uintptr_t>(this) + offset;
386 enum CheckAlignment { NO_CHECK, CHECK_ALIGNMENT };
388 V8_INLINE const Instruction* InstructionAtOffset(
389 int64_t offset, CheckAlignment check = CHECK_ALIGNMENT) const {
390 // The FUZZ_disasm test relies on no check being done.
391 DCHECK(check == NO_CHECK || IsAligned(offset, kInstructionSize));
392 return this + offset;
395 V8_INLINE Instruction* InstructionAtOffset(
396 int64_t offset, CheckAlignment check = CHECK_ALIGNMENT) {
397 // The FUZZ_disasm test relies on no check being done.
398 DCHECK(check == NO_CHECK || IsAligned(offset, kInstructionSize));
399 return this + offset;
402 template<typename T> V8_INLINE static Instruction* Cast(T src) {
403 return reinterpret_cast<Instruction*>(src);
406 V8_INLINE ptrdiff_t DistanceTo(Instruction* target) {
407 return reinterpret_cast<Address>(target) - reinterpret_cast<Address>(this);
411 static const int ImmPCRelRangeBitwidth = 21;
412 static bool IsValidPCRelOffset(ptrdiff_t offset) { return is_int21(offset); }
413 void SetPCRelImmTarget(Instruction* target);
414 void SetBranchImmTarget(Instruction* target);
418 // Where Instruction looks at instructions generated by the Assembler,
419 // InstructionSequence looks at instructions sequences generated by the
421 class InstructionSequence : public Instruction {
423 static InstructionSequence* At(Address address) {
424 return reinterpret_cast<InstructionSequence*>(address);
427 // Sequences generated by MacroAssembler::InlineData().
428 bool IsInlineData() const;
429 uint64_t InlineData() const;
433 // Simulator/Debugger debug instructions ---------------------------------------
434 // Each debug marker is represented by a HLT instruction. The immediate comment
435 // field in the instruction is used to identify the type of debug marker. Each
436 // marker encodes arguments in a different way, as described below.
438 // Indicate to the Debugger that the instruction is a redirected call.
439 const Instr kImmExceptionIsRedirectedCall = 0xca11;
441 // Represent unreachable code. This is used as a guard in parts of the code that
442 // should not be reachable, such as in data encoded inline in the instructions.
443 const Instr kImmExceptionIsUnreachable = 0xdebf;
445 // A pseudo 'printf' instruction. The arguments will be passed to the platform
447 const Instr kImmExceptionIsPrintf = 0xdeb1;
448 // Most parameters are stored in ARM64 registers as if the printf
449 // pseudo-instruction was a call to the real printf method:
450 // x0: The format string.
451 // x1-x7: Optional arguments.
452 // d0-d7: Optional arguments.
454 // Also, the argument layout is described inline in the instructions:
455 // - arg_count: The number of arguments.
456 // - arg_pattern: A set of PrintfArgPattern values, packed into two-bit fields.
458 // Floating-point and integer arguments are passed in separate sets of registers
459 // in AAPCS64 (even for varargs functions), so it is not possible to determine
460 // the type of each argument without some information about the values that were
461 // passed in. This information could be retrieved from the printf format string,
462 // but the format string is not trivial to parse so we encode the relevant
463 // information with the HLT instruction.
464 const unsigned kPrintfArgCountOffset = 1 * kInstructionSize;
465 const unsigned kPrintfArgPatternListOffset = 2 * kInstructionSize;
466 const unsigned kPrintfLength = 3 * kInstructionSize;
468 const unsigned kPrintfMaxArgCount = 4;
470 // The argument pattern is a set of two-bit-fields, each with one of the
472 enum PrintfArgPattern {
475 // There is no kPrintfArgS because floats are always converted to doubles in C
479 static const unsigned kPrintfArgPatternBits = 2;
481 // A pseudo 'debug' instruction.
482 const Instr kImmExceptionIsDebug = 0xdeb0;
483 // Parameters are inlined in the code after a debug pseudo-instruction:
485 // - Debug parameters.
486 // - Debug message string. This is a NULL-terminated ASCII string, padded to
487 // kInstructionSize so that subsequent instructions are correctly aligned.
488 // - A kImmExceptionIsUnreachable marker, to catch accidental execution of the
490 const unsigned kDebugCodeOffset = 1 * kInstructionSize;
491 const unsigned kDebugParamsOffset = 2 * kInstructionSize;
492 const unsigned kDebugMessageOffset = 3 * kInstructionSize;
495 // Used without a TRACE_ option, the Debugger will print the arguments only
496 // once. Otherwise TRACE_ENABLE and TRACE_DISABLE will enable or disable tracing
497 // before every instruction for the specified LOG_ parameters.
499 // TRACE_OVERRIDE enables the specified LOG_ parameters, and disabled any
500 // others that were not specified.
504 // __ debug("print registers and fp registers", 0, LOG_REGS | LOG_FP_REGS);
505 // will print the registers and fp registers only once.
507 // __ debug("trace disasm", 1, TRACE_ENABLE | LOG_DISASM);
508 // starts disassembling the code.
510 // __ debug("trace rets", 2, TRACE_ENABLE | LOG_REGS);
511 // adds the general purpose registers to the trace.
513 // __ debug("stop regs", 3, TRACE_DISABLE | LOG_REGS);
514 // stops tracing the registers.
515 const unsigned kDebuggerTracingDirectivesMask = 3 << 6;
516 enum DebugParameters {
519 LOG_DISASM = 1 << 1, // Use only with TRACE. Disassemble the code.
520 LOG_REGS = 1 << 2, // Log general purpose registers.
521 LOG_FP_REGS = 1 << 3, // Log floating-point registers.
522 LOG_SYS_REGS = 1 << 4, // Log the status flags.
523 LOG_WRITE = 1 << 5, // Log any memory write.
525 LOG_STATE = LOG_REGS | LOG_FP_REGS | LOG_SYS_REGS,
526 LOG_ALL = LOG_DISASM | LOG_STATE | LOG_WRITE,
529 TRACE_ENABLE = 1 << 6,
530 TRACE_DISABLE = 2 << 6,
531 TRACE_OVERRIDE = 3 << 6
535 } } // namespace v8::internal
538 #endif // V8_ARM64_INSTRUCTIONS_ARM64_H_