src/amd/vulkan/radv_perfcounter.c

   1 /*
   2  * Copyright © 2021 Valve Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <inttypes.h>
  25
  26 #include "radv_cs.h"
  27 #include "radv_private.h"
  28 #include "sid.h"
  29
  30 void
  31 radv_perfcounter_emit_shaders(struct radeon_cmdbuf *cs, unsigned shaders)
  32 {
  33    radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2);
  34    radeon_emit(cs, shaders & 0x7f);
  35    radeon_emit(cs, 0xffffffff);
  36 }
  37
  38 void
  39 radv_perfcounter_emit_spm_reset(struct radeon_cmdbuf *cs)
  40 {
  41    radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
  42                               S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_DISABLE_AND_RESET) |
  43                               S_036020_SPM_PERFMON_STATE(V_036020_STRM_PERFMON_STATE_DISABLE_AND_RESET));
  44 }
  45
  46 void
  47 radv_perfcounter_emit_spm_start(struct radv_device *device, struct radeon_cmdbuf *cs, int family)
  48 {
  49    /* Start SPM counters. */
  50    radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
  51                               S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_DISABLE_AND_RESET) |
  52                               S_036020_SPM_PERFMON_STATE(V_036020_STRM_PERFMON_STATE_START_COUNTING));
  53
  54    /* Start windowed performance counters. */
  55    if (family == RADV_QUEUE_GENERAL) {
  56       radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
  57       radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_START) | EVENT_INDEX(0));
  58    }
  59    radeon_set_sh_reg(cs, R_00B82C_COMPUTE_PERFCOUNT_ENABLE, S_00B82C_PERFCOUNT_ENABLE(1));
  60 }
  61
  62 void
  63 radv_perfcounter_emit_spm_stop(struct radv_device *device, struct radeon_cmdbuf *cs, int family)
  64 {
  65    /* Stop windowed performance counters. */
  66    if (family == RADV_QUEUE_GENERAL) {
  67       if (!device->physical_device->rad_info.never_send_perfcounter_stop) {
  68          radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
  69          radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_STOP) | EVENT_INDEX(0));
  70       }
  71    }
  72    radeon_set_sh_reg(cs, R_00B82C_COMPUTE_PERFCOUNT_ENABLE, S_00B82C_PERFCOUNT_ENABLE(0));
  73
  74    /* Stop SPM counters. */
  75    radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
  76                               S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_DISABLE_AND_RESET) |
  77                               S_036020_SPM_PERFMON_STATE(device->physical_device->rad_info.never_stop_sq_perf_counters ?
  78                                                             V_036020_STRM_PERFMON_STATE_START_COUNTING :
  79                                                             V_036020_STRM_PERFMON_STATE_STOP_COUNTING));
  80 }