1 // Copyright 2010 the V8 project authors. All rights reserved.
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3 // modification, are permitted provided that the following conditions are
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7 // notice, this list of conditions and the following disclaimer.
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28 // This file is an internal atomic implementation, use atomicops.h instead.
30 #ifndef V8_ATOMICOPS_INTERNALS_X86_GCC_H_
31 #define V8_ATOMICOPS_INTERNALS_X86_GCC_H_
36 // This struct is not part of the public API of this module; clients may not
38 // Features of this x86. Values may not be correct before main() is run,
39 // but are set conservatively.
40 struct AtomicOps_x86CPUFeatureStruct {
41 bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
42 // after acquire compare-and-swap.
43 bool has_sse2; // Processor has SSE2.
45 extern struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures;
47 #define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
49 // 32-bit low-level operations on any platform.
51 inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
55 __asm__ __volatile__("lock; cmpxchgl %1,%2"
57 : "q" (new_value), "m" (*ptr), "0" (old_value)
62 inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
64 __asm__ __volatile__("xchgl %1,%0" // The lock prefix is implicit for xchg.
66 : "m" (*ptr), "0" (new_value)
68 return new_value; // Now it's the previous value.
71 inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
73 Atomic32 temp = increment;
74 __asm__ __volatile__("lock; xaddl %0,%1"
75 : "+r" (temp), "+m" (*ptr)
77 // temp now holds the old value of *ptr
78 return temp + increment;
81 inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
83 Atomic32 temp = increment;
84 __asm__ __volatile__("lock; xaddl %0,%1"
85 : "+r" (temp), "+m" (*ptr)
87 // temp now holds the old value of *ptr
88 if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
89 __asm__ __volatile__("lfence" : : : "memory");
91 return temp + increment;
94 inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
97 Atomic32 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
98 if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
99 __asm__ __volatile__("lfence" : : : "memory");
104 inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
106 Atomic32 new_value) {
107 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
110 inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
114 #if defined(__x86_64__)
116 // 64-bit implementations of memory barrier can be simpler, because it
117 // "mfence" is guaranteed to exist.
118 inline void MemoryBarrier() {
119 __asm__ __volatile__("mfence" : : : "memory");
122 inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
129 inline void MemoryBarrier() {
130 if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
131 __asm__ __volatile__("mfence" : : : "memory");
132 } else { // mfence is faster but not present on PIII
134 NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
138 inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
139 if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
141 __asm__ __volatile__("mfence" : : : "memory");
143 NoBarrier_AtomicExchange(ptr, value);
144 // acts as a barrier on PIII
149 inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
150 ATOMICOPS_COMPILER_BARRIER();
151 *ptr = value; // An x86 store acts as a release barrier.
152 // See comments in Atomic64 version of Release_Store(), below.
155 inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
159 inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
160 Atomic32 value = *ptr; // An x86 load acts as a acquire barrier.
161 // See comments in Atomic64 version of Release_Store(), below.
162 ATOMICOPS_COMPILER_BARRIER();
166 inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
171 #if defined(__x86_64__)
173 // 64-bit low-level operations on 64-bit platform.
175 inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
177 Atomic64 new_value) {
179 __asm__ __volatile__("lock; cmpxchgq %1,%2"
181 : "q" (new_value), "m" (*ptr), "0" (old_value)
186 inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
187 Atomic64 new_value) {
188 __asm__ __volatile__("xchgq %1,%0" // The lock prefix is implicit for xchg.
190 : "m" (*ptr), "0" (new_value)
192 return new_value; // Now it's the previous value.
195 inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
196 Atomic64 increment) {
197 Atomic64 temp = increment;
198 __asm__ __volatile__("lock; xaddq %0,%1"
199 : "+r" (temp), "+m" (*ptr)
201 // temp now contains the previous value of *ptr
202 return temp + increment;
205 inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
206 Atomic64 increment) {
207 Atomic64 temp = increment;
208 __asm__ __volatile__("lock; xaddq %0,%1"
209 : "+r" (temp), "+m" (*ptr)
211 // temp now contains the previous value of *ptr
212 if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
213 __asm__ __volatile__("lfence" : : : "memory");
215 return temp + increment;
218 inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
222 inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
227 inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
228 ATOMICOPS_COMPILER_BARRIER();
230 *ptr = value; // An x86 store acts as a release barrier
231 // for current AMD/Intel chips as of Jan 2008.
232 // See also Acquire_Load(), below.
234 // When new chips come out, check:
235 // IA-32 Intel Architecture Software Developer's Manual, Volume 3:
236 // System Programming Guide, Chatper 7: Multiple-processor management,
237 // Section 7.2, Memory Ordering.
239 // http://developer.intel.com/design/pentium4/manuals/index_new.htm
241 // x86 stores/loads fail to act as barriers for a few instructions (clflush
242 // maskmovdqu maskmovq movntdq movnti movntpd movntps movntq) but these are
243 // not generated by the compiler, and are rare. Users of these instructions
244 // need to know about cache behaviour in any case since all of these involve
245 // either flushing cache lines or non-temporal cache hints.
248 inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
252 inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
253 Atomic64 value = *ptr; // An x86 load acts as a acquire barrier,
254 // for current AMD/Intel chips as of Jan 2008.
255 // See also Release_Store(), above.
256 ATOMICOPS_COMPILER_BARRIER();
260 inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
265 inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
267 Atomic64 new_value) {
268 Atomic64 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
269 if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
270 __asm__ __volatile__("lfence" : : : "memory");
275 inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
277 Atomic64 new_value) {
278 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
281 #endif // defined(__x86_64__)
283 } } // namespace v8::internal
285 #undef ATOMICOPS_COMPILER_BARRIER
287 #endif // V8_ATOMICOPS_INTERNALS_X86_GCC_H_